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revise dl814_dj_48m

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the data counter of module tx_pn_seq was mod-32, now modified to mod-128 to cover the whole pn cycle
This commit is contained in:
josh
2023-03-26 14:18:20 +08:00
parent 7a555fab92
commit bd032a8474
1281 changed files with 161534 additions and 1577004 deletions
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projects/datalink_814/dl814_dj/ip/cmpy_18x8.xcix
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projects/datalink_814/dl814_dj/ip/dds_32b_8b.xcix
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projects/datalink_814/dl814_dj/ip/hop_rom.xcix
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projects/datalink_814/dl814_dj/ip/hrc_64_12_025.xcix
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projects/datalink_814/dl814_dj/ip/ila_ctrl_signal.xcix
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_sim_netlist.v
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_sim_netlist.vhdl
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:22:44 2023
// Date : Fri Mar 17 22:22:43 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top cmpy_18x8 -prefix
// cmpy_18x8_ cmpy_18x8_stub.v
// Design : cmpy_18x8
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/cmpy_18x8/cmpy_18x8_stub.vhdl
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@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:44 2023
-- Date : Fri Mar 17 22:22:43 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top cmpy_18x8 -prefix
-- cmpy_18x8_ cmpy_18x8_stub.vhdl
-- Design : cmpy_18x8
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_sim_netlist.v
+862 -868
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_sim_netlist.vhdl
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_stub.v
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@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:22:40 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top dds_32b_8b -prefix
// dds_32b_8b_ dds_32b_8b_stub.v
// Design : dds_32b_8b
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/dds_32b_8b/dds_32b_8b_stub.vhdl
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@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:40 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top dds_32b_8b -prefix
-- dds_32b_8b_ dds_32b_8b_stub.vhdl
-- Design : dds_32b_8b
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hop_rom/hop_rom_sim_netlist.v
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@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:23:06 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top hop_rom -prefix
// hop_rom_ hop_rom_sim_netlist.v
// Design : hop_rom
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -188,7 +188,6 @@ module hop_rom
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module hop_rom_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -464,7 +463,6 @@ module hop_rom_blk_mem_gen_generic_cstr
.ram_douta(ram_douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module hop_rom_blk_mem_gen_prim_width
(ram_douta,
clka,
@@ -483,7 +481,6 @@ module hop_rom_blk_mem_gen_prim_width
.ram_douta(ram_douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module hop_rom_blk_mem_gen_prim_wrapper_init
(ram_douta,
clka,
@@ -626,7 +623,6 @@ module hop_rom_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module hop_rom_blk_mem_gen_top
(douta,
clka,
@@ -670,7 +666,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "256" *)
(* C_WRITE_DEPTH_B = "256" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "zynq" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module hop_rom_blk_mem_gen_v8_4_3
(clka,
rsta,
@@ -916,7 +912,6 @@ module hop_rom_blk_mem_gen_v8_4_3
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *)
module hop_rom_blk_mem_gen_v8_4_3_synth
(douta,
clka,
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hop_rom/hop_rom_sim_netlist.vhdl
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@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:23:06 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top hop_rom -prefix
-- hop_rom_ hop_rom_sim_netlist.vhdl
-- Design : hop_rom
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -20,8 +20,6 @@ entity hop_rom_blk_mem_gen_prim_wrapper_init is
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end hop_rom_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of hop_rom_blk_mem_gen_prim_wrapper_init is
@@ -175,8 +173,6 @@ entity hop_rom_blk_mem_gen_prim_width is
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end hop_rom_blk_mem_gen_prim_width;
architecture STRUCTURE of hop_rom_blk_mem_gen_prim_width is
@@ -198,8 +194,6 @@ entity hop_rom_blk_mem_gen_generic_cstr is
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end hop_rom_blk_mem_gen_generic_cstr;
architecture STRUCTURE of hop_rom_blk_mem_gen_generic_cstr is
@@ -574,8 +568,6 @@ entity hop_rom_blk_mem_gen_top is
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_top : entity is "blk_mem_gen_top";
end hop_rom_blk_mem_gen_top;
architecture STRUCTURE of hop_rom_blk_mem_gen_top is
@@ -597,8 +589,6 @@ entity hop_rom_blk_mem_gen_v8_4_3_synth is
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
end hop_rom_blk_mem_gen_v8_4_3_synth;
architecture STRUCTURE of hop_rom_blk_mem_gen_v8_4_3_synth is
@@ -830,8 +820,6 @@ entity hop_rom_blk_mem_gen_v8_4_3 is
attribute C_WRITE_WIDTH_B of hop_rom_blk_mem_gen_v8_4_3 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of hop_rom_blk_mem_gen_v8_4_3 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hop_rom_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of hop_rom_blk_mem_gen_v8_4_3 : entity is "yes";
end hop_rom_blk_mem_gen_v8_4_3;
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hop_rom/hop_rom_stub.v
+2 -2
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@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:23:06 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top hop_rom -prefix
// hop_rom_ hop_rom_stub.v
// Design : hop_rom
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hop_rom/hop_rom_stub.vhdl
+2 -2
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@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:23:06 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top hop_rom -prefix
-- hop_rom_ hop_rom_stub.vhdl
-- Design : hop_rom
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_sim_netlist.v
+5001 -5007
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_sim_netlist.vhdl
+6833 -6856
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_stub.v
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@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:22:50 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top hrc_64_12_025 -prefix
// hrc_64_12_025_ hrc_64_12_025_stub.v
// Design : hrc_64_12_025
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/hrc_64_12_025/hrc_64_12_025_stub.vhdl
+2 -2
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@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:50 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top hrc_64_12_025 -prefix
-- hrc_64_12_025_ hrc_64_12_025_stub.vhdl
-- Design : hrc_64_12_025
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_ctrl_signal/ila_ctrl_signal_sim_netlist.v
+5 -40
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projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_ctrl_signal/ila_ctrl_signal_sim_netlist.vhdl
+3 -73
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@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:23:33 2023
-- Date : Fri Mar 17 22:23:32 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_ctrl_signal_synth_1/ila_ctrl_signal_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top ila_ctrl_signal -prefix
-- ila_ctrl_signal_ ila_ctrl_signal_sim_netlist.vhdl
-- Design : ila_ctrl_signal
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -25,8 +25,6 @@ entity ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper is
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
DIADI : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper";
end ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper is
@@ -206,8 +204,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_all_typeA_slice is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_all_typeA_slice : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_ctrl_signal_ltlib_v1_0_0_all_typeA_slice;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_all_typeA_slice is
@@ -1822,8 +1818,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_async_edge_xfer is
arm_ctrl : in STD_LOGIC;
last_din : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_async_edge_xfer : entity is "ltlib_v1_0_0_async_edge_xfer";
end ila_ctrl_signal_ltlib_v1_0_0_async_edge_xfer;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_async_edge_xfer is
@@ -2296,8 +2290,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_cfglut4 is
A : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_cfglut4 : entity is "ltlib_v1_0_0_cfglut4";
end ila_ctrl_signal_ltlib_v1_0_0_cfglut4;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_cfglut4 is
@@ -2372,8 +2364,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_cfglut5 is
A : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_cfglut5 : entity is "ltlib_v1_0_0_cfglut5";
end ila_ctrl_signal_ltlib_v1_0_0_cfglut5;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_cfglut5 is
@@ -2484,8 +2474,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_cfglut6 is
s_dclk_o : in STD_LOGIC;
u_wcnt_hcmp_q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_cfglut6 : entity is "ltlib_v1_0_0_cfglut6";
end ila_ctrl_signal_ltlib_v1_0_0_cfglut6;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_cfglut6 is
@@ -2737,8 +2725,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_cfglut7 is
wcnt_hcmp : in STD_LOGIC;
\I_YESLUT6.I_YES_OREG.O_reg_reg_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_cfglut7 : entity is "ltlib_v1_0_0_cfglut7";
end ila_ctrl_signal_ltlib_v1_0_0_cfglut7;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_cfglut7 is
@@ -2983,8 +2969,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_generic_memrd is
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\input_data_reg[6]_1\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_generic_memrd : entity is "ltlib_v1_0_0_generic_memrd";
end ila_ctrl_signal_ltlib_v1_0_0_generic_memrd;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_generic_memrd is
@@ -3668,8 +3652,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_rising_edge_detection is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\dout_pulse_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_rising_edge_detection : entity is "ltlib_v1_0_0_rising_edge_detection";
end ila_ctrl_signal_ltlib_v1_0_0_rising_edge_detection;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_rising_edge_detection is
@@ -3853,8 +3835,6 @@ entity ila_ctrl_signal_xsdbs_v1_0_2_reg_ctl is
s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_xsdbs_v1_0_2_reg_ctl : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_ctrl_signal_xsdbs_v1_0_2_reg_ctl;
architecture STRUCTURE of ila_ctrl_signal_xsdbs_v1_0_2_reg_ctl is
@@ -8870,8 +8850,6 @@ entity ila_ctrl_signal_xsdbs_v1_0_2_reg_p2s is
\shadow_reg[15]_0\ : in STD_LOGIC;
mu_config_cs_serial_input : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_xsdbs_v1_0_2_reg_p2s : entity is "xsdbs_v1_0_2_reg_p2s";
end ila_ctrl_signal_xsdbs_v1_0_2_reg_p2s;
architecture STRUCTURE of ila_ctrl_signal_xsdbs_v1_0_2_reg_p2s is
@@ -16292,8 +16270,6 @@ entity ila_ctrl_signal_xsdbs_v1_0_2_reg_stat is
\xsdb_reg_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_xsdbs_v1_0_2_reg_stat : entity is "xsdbs_v1_0_2_reg_stat";
end ila_ctrl_signal_xsdbs_v1_0_2_reg_stat;
architecture STRUCTURE of ila_ctrl_signal_xsdbs_v1_0_2_reg_stat is
@@ -16910,8 +16886,6 @@ entity ila_ctrl_signal_xsdbs_v1_0_2_xsdbs is
attribute C_XDEVICEFAMILY of ila_ctrl_signal_xsdbs_v1_0_2_xsdbs : entity is "zynq";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of ila_ctrl_signal_xsdbs_v1_0_2_xsdbs : entity is 17;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_xsdbs_v1_0_2_xsdbs : entity is "xsdbs_v1_0_2_xsdbs";
attribute dont_touch : string;
attribute dont_touch of ila_ctrl_signal_xsdbs_v1_0_2_xsdbs : entity is "true";
end ila_ctrl_signal_xsdbs_v1_0_2_xsdbs;
@@ -20450,8 +20424,6 @@ entity ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width is
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
DIADI : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_prim_width";
end ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width;
architecture STRUCTURE of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width is
@@ -20483,8 +20455,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_reset_ctrl is
halt_ctrl : in STD_LOGIC;
arm_ctrl : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_reset_ctrl : entity is "ila_v6_2_9_ila_reset_ctrl";
end ila_ctrl_signal_ila_v6_2_9_ila_reset_ctrl;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_reset_ctrl is
@@ -20670,8 +20640,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_all_typeA is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_all_typeA : entity is "ltlib_v1_0_0_all_typeA";
end ila_ctrl_signal_ltlib_v1_0_0_all_typeA;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_all_typeA is
@@ -22625,8 +22593,6 @@ entity ila_ctrl_signal_xsdbs_v1_0_2_reg_stream is
s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_xsdbs_v1_0_2_reg_stream : entity is "xsdbs_v1_0_2_reg_stream";
end ila_ctrl_signal_xsdbs_v1_0_2_reg_stream;
architecture STRUCTURE of ila_ctrl_signal_xsdbs_v1_0_2_reg_stream is
@@ -22712,8 +22678,6 @@ entity ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr is
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
DIADI : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr";
end ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr;
architecture STRUCTURE of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr is
@@ -22771,8 +22735,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_register is
\xsdb_reg_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\xsdb_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_register : entity is "ila_v6_2_9_ila_register";
end ila_ctrl_signal_ila_v6_2_9_ila_register;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_register is
@@ -27520,8 +27482,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_allx_typeA is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_allx_typeA : entity is "ltlib_v1_0_0_allx_typeA";
end ila_ctrl_signal_ltlib_v1_0_0_allx_typeA;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_allx_typeA is
@@ -27915,8 +27875,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_allx_typeA_nodelay is
SRL_D_I : in STD_LOGIC;
\probeDelay1_reg[0]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_allx_typeA_nodelay : entity is "ltlib_v1_0_0_allx_typeA_nodelay";
end ila_ctrl_signal_ltlib_v1_0_0_allx_typeA_nodelay;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_allx_typeA_nodelay is
@@ -28206,8 +28164,6 @@ entity ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_top is
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
DIADI : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_top : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_top";
end ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_top;
architecture STRUCTURE of ila_ctrl_signal_blk_mem_gen_v8_4_3_blk_mem_gen_top is
@@ -28239,8 +28195,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_match is
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_match : entity is "ltlib_v1_0_0_match";
end ila_ctrl_signal_ltlib_v1_0_0_match;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_match is
@@ -28595,8 +28549,6 @@ entity ila_ctrl_signal_ltlib_v1_0_0_match_nodelay is
PROBES_I : in STD_LOGIC_VECTOR ( 19 downto 0 );
SRL_D_I : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ltlib_v1_0_0_match_nodelay : entity is "ltlib_v1_0_0_match_nodelay";
end ila_ctrl_signal_ltlib_v1_0_0_match_nodelay;
architecture STRUCTURE of ila_ctrl_signal_ltlib_v1_0_0_match_nodelay is
@@ -28690,8 +28642,6 @@ entity ila_ctrl_signal_blk_mem_gen_v8_4_3_synth is
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
DIADI : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
end ila_ctrl_signal_blk_mem_gen_v8_4_3_synth;
architecture STRUCTURE of ila_ctrl_signal_blk_mem_gen_v8_4_3_synth is
@@ -28733,8 +28683,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_cap_sample_counter is
\out\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_cap_sample_counter : entity is "ila_v6_2_9_ila_cap_sample_counter";
end ila_ctrl_signal_ila_v6_2_9_ila_cap_sample_counter;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_cap_sample_counter is
@@ -29146,8 +29094,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_cap_window_counter is
wcnt_hcmp_temp : in STD_LOGIC;
\iwcnt_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_cap_window_counter : entity is "ila_v6_2_9_ila_cap_window_counter";
end ila_ctrl_signal_ila_v6_2_9_ila_cap_window_counter;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_cap_window_counter is
@@ -29490,8 +29436,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_trig_match is
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
probe_data : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_trig_match : entity is "ila_v6_2_9_ila_trig_match";
end ila_ctrl_signal_ila_v6_2_9_ila_trig_match;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_trig_match is
@@ -29578,8 +29522,6 @@ entity ila_ctrl_signal_blk_mem_gen_v8_4_3 is
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
DIADI : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
end ila_ctrl_signal_blk_mem_gen_v8_4_3;
architecture STRUCTURE of ila_ctrl_signal_blk_mem_gen_v8_4_3 is
@@ -29626,8 +29568,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_cap_addrgen is
u_scnt_cmp_q_1 : in STD_LOGIC;
\captured_samples_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_cap_addrgen : entity is "ila_v6_2_9_ila_cap_addrgen";
end ila_ctrl_signal_ila_v6_2_9_ila_cap_addrgen;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_cap_addrgen is
@@ -31024,8 +30964,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_trigger is
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC;
probe_data : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_trigger : entity is "ila_v6_2_9_ila_trigger";
end ila_ctrl_signal_ila_v6_2_9_ila_trigger;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_trigger is
@@ -31091,8 +31029,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_cap_ctrl_legacy is
u_scnt_cmp_q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\captured_samples_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_cap_ctrl_legacy : entity is "ila_v6_2_9_ila_cap_ctrl_legacy";
end ila_ctrl_signal_ila_v6_2_9_ila_cap_ctrl_legacy;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_cap_ctrl_legacy is
@@ -31263,8 +31199,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_trace_memory is
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
DIADI : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_trace_memory : entity is "ila_v6_2_9_ila_trace_memory";
end ila_ctrl_signal_ila_v6_2_9_ila_trace_memory;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_trace_memory is
@@ -31298,8 +31232,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila_core is
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila_core : entity is "ila_v6_2_9_ila_core";
end ila_ctrl_signal_ila_v6_2_9_ila_core;
architecture STRUCTURE of ila_ctrl_signal_ila_v6_2_9_ila_core is
@@ -51744,8 +51676,6 @@ entity ila_ctrl_signal_ila_v6_2_9_ila is
attribute LC_TIME_TAG_WIDTH of ila_ctrl_signal_ila_v6_2_9_ila : entity is 1;
attribute LC_TRIG_WIDTH : integer;
attribute LC_TRIG_WIDTH of ila_ctrl_signal_ila_v6_2_9_ila : entity is 6;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_ctrl_signal_ila_v6_2_9_ila : entity is "ila_v6_2_9_ila";
attribute dont_touch : string;
attribute dont_touch of ila_ctrl_signal_ila_v6_2_9_ila : entity is "true";
end ila_ctrl_signal_ila_v6_2_9_ila;
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_ctrl_signal/ila_ctrl_signal_stub.v
+3 -3
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:23:33 2023
// Date : Fri Mar 17 22:23:32 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_ctrl_signal_synth_1/ila_ctrl_signal_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top ila_ctrl_signal -prefix
// ila_ctrl_signal_ ila_ctrl_signal_stub.v
// Design : ila_ctrl_signal
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_ctrl_signal/ila_ctrl_signal_stub.vhdl
+3 -3
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:23:33 2023
-- Date : Fri Mar 17 22:23:32 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_ctrl_signal_synth_1/ila_ctrl_signal_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top ila_ctrl_signal -prefix
-- ila_ctrl_signal_ ila_ctrl_signal_stub.vhdl
-- Design : ila_ctrl_signal
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_tx_rx/ila_tx_rx_sim_netlist.v
+6 -46
View File
File diff suppressed because one or more lines are too long
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_tx_rx/ila_tx_rx_sim_netlist.vhdl
+3 -83
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:27:11 2023
-- Date : Fri Mar 17 22:27:06 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/ila_tx_rx_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top ila_tx_rx -prefix
-- ila_tx_rx_ ila_tx_rx_sim_netlist.vhdl
-- Design : ila_tx_rx
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -20,8 +20,6 @@ entity ila_tx_rx_blk_mem_gen_v8_4_3_bindec is
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_blk_mem_gen_v8_4_3_bindec : entity is "blk_mem_gen_v8_4_3_bindec";
end ila_tx_rx_blk_mem_gen_v8_4_3_bindec;
architecture STRUCTURE of ila_tx_rx_blk_mem_gen_v8_4_3_bindec is
@@ -16268,8 +16266,6 @@ entity ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper is
DIADI : in STD_LOGIC_VECTOR ( 7 downto 0 );
DIPADIP : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper";
end ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper is
@@ -106383,8 +106379,6 @@ entity ila_tx_rx_ila_v6_2_9_generic_counter is
attribute CNT_MAX of ila_tx_rx_ila_v6_2_9_generic_counter : entity is "17'b10000000000000000";
attribute C_COUNTER_WIDTH : integer;
attribute C_COUNTER_WIDTH of ila_tx_rx_ila_v6_2_9_generic_counter : entity is 17;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_generic_counter : entity is "ila_v6_2_9_generic_counter";
attribute dont_touch : string;
attribute dont_touch of ila_tx_rx_ila_v6_2_9_generic_counter : entity is "true";
end ila_tx_rx_ila_v6_2_9_generic_counter;
@@ -108878,8 +108872,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_adv_trigger_sequencer is
\SEQUENCER_STATE_O_reg[8]_0\ : in STD_LOGIC;
\SEQUENCER_STATE_O_reg[0]_2\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_adv_trigger_sequencer : entity is "ila_v6_2_9_ila_adv_trigger_sequencer";
end ila_tx_rx_ila_v6_2_9_ila_adv_trigger_sequencer;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_adv_trigger_sequencer is
@@ -111622,8 +111614,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_fsm_memory_read is
D : in STD_LOGIC_VECTOR ( 15 downto 0 );
\CFG_DATA_O_reg[7]_0\ : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_fsm_memory_read : entity is "ila_v6_2_9_ila_fsm_memory_read";
end ila_tx_rx_ila_v6_2_9_ila_fsm_memory_read;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_fsm_memory_read is
@@ -112104,8 +112094,6 @@ entity ila_tx_rx_ltlib_v1_0_0_all_typeA_slice is
all_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
CI_I : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_all_typeA_slice : entity is "ltlib_v1_0_0_all_typeA_slice";
end ila_tx_rx_ltlib_v1_0_0_all_typeA_slice;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_all_typeA_slice is
@@ -124823,8 +124811,6 @@ entity ila_tx_rx_ltlib_v1_0_0_async_edge_xfer is
arm_ctrl : in STD_LOGIC;
last_din : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_async_edge_xfer : entity is "ltlib_v1_0_0_async_edge_xfer";
end ila_tx_rx_ltlib_v1_0_0_async_edge_xfer;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_async_edge_xfer is
@@ -125310,8 +125296,6 @@ entity ila_tx_rx_ltlib_v1_0_0_cfglut4 is
A : in STD_LOGIC_VECTOR ( 3 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_cfglut4 : entity is "ltlib_v1_0_0_cfglut4";
end ila_tx_rx_ltlib_v1_0_0_cfglut4;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_cfglut4 is
@@ -125386,8 +125370,6 @@ entity ila_tx_rx_ltlib_v1_0_0_cfglut5 is
A : in STD_LOGIC_VECTOR ( 4 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_cfglut5 : entity is "ltlib_v1_0_0_cfglut5";
end ila_tx_rx_ltlib_v1_0_0_cfglut5;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_cfglut5 is
@@ -125498,8 +125480,6 @@ entity ila_tx_rx_ltlib_v1_0_0_cfglut6 is
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
u_wcnt_hcmp_q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_cfglut6 : entity is "ltlib_v1_0_0_cfglut6";
end ila_tx_rx_ltlib_v1_0_0_cfglut6;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_cfglut6 is
@@ -125729,8 +125709,6 @@ entity ila_tx_rx_ltlib_v1_0_0_cfglut7 is
\cntcmpsel_reg[1]\ : in STD_LOGIC;
trig_out_fsm : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_cfglut7 : entity is "ltlib_v1_0_0_cfglut7";
end ila_tx_rx_ltlib_v1_0_0_cfglut7;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_cfglut7 is
@@ -126129,8 +126107,6 @@ entity ila_tx_rx_ltlib_v1_0_0_generic_memrd is
\input_data_reg[98]_0\ : in STD_LOGIC_VECTOR ( 98 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_generic_memrd : entity is "ltlib_v1_0_0_generic_memrd";
end ila_tx_rx_ltlib_v1_0_0_generic_memrd;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_generic_memrd is
@@ -133453,8 +133429,6 @@ entity ila_tx_rx_ltlib_v1_0_0_rising_edge_detection is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\dout_pulse_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_rising_edge_detection : entity is "ltlib_v1_0_0_rising_edge_detection";
end ila_tx_rx_ltlib_v1_0_0_rising_edge_detection;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_rising_edge_detection is
@@ -133626,8 +133600,6 @@ entity ila_tx_rx_xsdbs_v1_0_2_reg_ctl is
s_di_o : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_xsdbs_v1_0_2_reg_ctl : entity is "xsdbs_v1_0_2_reg_ctl";
end ila_tx_rx_xsdbs_v1_0_2_reg_ctl;
architecture STRUCTURE of ila_tx_rx_xsdbs_v1_0_2_reg_ctl is
@@ -139038,8 +139010,6 @@ entity ila_tx_rx_xsdbs_v1_0_2_reg_p2s is
\current_state_reg[1]_0\ : in STD_LOGIC;
\current_state_reg[1]_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_xsdbs_v1_0_2_reg_p2s : entity is "xsdbs_v1_0_2_reg_p2s";
end ila_tx_rx_xsdbs_v1_0_2_reg_p2s;
architecture STRUCTURE of ila_tx_rx_xsdbs_v1_0_2_reg_p2s is
@@ -188780,8 +188750,6 @@ entity ila_tx_rx_xsdbs_v1_0_2_reg_stat is
\xsdb_reg_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_xsdbs_v1_0_2_reg_stat : entity is "xsdbs_v1_0_2_reg_stat";
end ila_tx_rx_xsdbs_v1_0_2_reg_stat;
architecture STRUCTURE of ila_tx_rx_xsdbs_v1_0_2_reg_stat is
@@ -190496,8 +190464,6 @@ entity ila_tx_rx_xsdbs_v1_0_2_xsdbs is
attribute C_XDEVICEFAMILY of ila_tx_rx_xsdbs_v1_0_2_xsdbs : entity is "zynq";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of ila_tx_rx_xsdbs_v1_0_2_xsdbs : entity is 17;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_xsdbs_v1_0_2_xsdbs : entity is "xsdbs_v1_0_2_xsdbs";
attribute dont_touch : string;
attribute dont_touch of ila_tx_rx_xsdbs_v1_0_2_xsdbs : entity is "true";
end ila_tx_rx_xsdbs_v1_0_2_xsdbs;
@@ -194038,8 +194004,6 @@ entity ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width is
DIADI : in STD_LOGIC_VECTOR ( 7 downto 0 );
DIPADIP : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_prim_width";
end ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width;
architecture STRUCTURE of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_prim_width is
@@ -207832,8 +207796,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_counter is
CFG_CNT_DIN : in STD_LOGIC_VECTOR ( 3 downto 0 );
cnt_config_cs_shift_en : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_counter : entity is "ila_v6_2_9_ila_counter";
end ila_tx_rx_ila_v6_2_9_ila_counter;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_counter is
@@ -207920,8 +207882,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_reset_ctrl is
\SEQUENCER_STATE_O_reg[8]\ : in STD_LOGIC;
\SEQUENCER_STATE_O_reg[8]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_reset_ctrl : entity is "ila_v6_2_9_ila_reset_ctrl";
end ila_tx_rx_ila_v6_2_9_ila_reset_ctrl;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_reset_ctrl is
@@ -208109,8 +208069,6 @@ entity ila_tx_rx_ltlib_v1_0_0_all_typeA is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_all_typeA : entity is "ltlib_v1_0_0_all_typeA";
end ila_tx_rx_ltlib_v1_0_0_all_typeA;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_all_typeA is
@@ -214377,8 +214335,6 @@ entity ila_tx_rx_xsdbs_v1_0_2_reg_stream is
\xsdb_reg_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_dclk_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_xsdbs_v1_0_2_reg_stream : entity is "xsdbs_v1_0_2_reg_stream";
end ila_tx_rx_xsdbs_v1_0_2_reg_stream;
architecture STRUCTURE of ila_tx_rx_xsdbs_v1_0_2_reg_stream is
@@ -214678,8 +214634,6 @@ entity ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr is
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_83\ : in STD_LOGIC;
trace_read_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr";
end ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr;
architecture STRUCTURE of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr is
@@ -220118,8 +220072,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_register is
\current_state_reg[1]_16\ : in STD_LOGIC;
CFG_CNT_DOUT : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_register : entity is "ila_v6_2_9_ila_register";
end ila_tx_rx_ila_v6_2_9_ila_register;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_register is
@@ -226299,8 +226251,6 @@ entity ila_tx_rx_ltlib_v1_0_0_allx_typeA is
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_allx_typeA : entity is "ltlib_v1_0_0_allx_typeA";
end ila_tx_rx_ltlib_v1_0_0_allx_typeA;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_allx_typeA is
@@ -229722,8 +229672,6 @@ entity ila_tx_rx_ltlib_v1_0_0_allx_typeA_nodelay is
SRL_D_I : in STD_LOGIC;
\probeDelay1_reg[0]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_allx_typeA_nodelay : entity is "ltlib_v1_0_0_allx_typeA_nodelay";
end ila_tx_rx_ltlib_v1_0_0_allx_typeA_nodelay;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_allx_typeA_nodelay is
@@ -230239,8 +230187,6 @@ entity ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_top is
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_83\ : in STD_LOGIC;
trace_read_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_top : entity is "blk_mem_gen_v8_4_3_blk_mem_gen_top";
end ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_top;
architecture STRUCTURE of ila_tx_rx_blk_mem_gen_v8_4_3_blk_mem_gen_top is
@@ -230359,8 +230305,6 @@ entity ila_tx_rx_ltlib_v1_0_0_match is
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_match : entity is "ltlib_v1_0_0_match";
end ila_tx_rx_ltlib_v1_0_0_match;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_match is
@@ -232910,8 +232854,6 @@ entity ila_tx_rx_ltlib_v1_0_0_match_nodelay is
PROBES_I : in STD_LOGIC_VECTOR ( 33 downto 0 );
SRL_D_I : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ltlib_v1_0_0_match_nodelay : entity is "ltlib_v1_0_0_match_nodelay";
end ila_tx_rx_ltlib_v1_0_0_match_nodelay;
architecture STRUCTURE of ila_tx_rx_ltlib_v1_0_0_match_nodelay is
@@ -233091,8 +233033,6 @@ entity ila_tx_rx_blk_mem_gen_v8_4_3_synth is
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_83\ : in STD_LOGIC;
trace_read_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
end ila_tx_rx_blk_mem_gen_v8_4_3_synth;
architecture STRUCTURE of ila_tx_rx_blk_mem_gen_v8_4_3_synth is
@@ -233217,8 +233157,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_cap_sample_counter is
\i_intcap.icap_addr_reg[16]\ : in STD_LOGIC_VECTOR ( 16 downto 0 );
\i_intcap.icap_addr_reg[16]_0\ : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_cap_sample_counter : entity is "ila_v6_2_9_ila_cap_sample_counter";
end ila_tx_rx_ila_v6_2_9_ila_cap_sample_counter;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_cap_sample_counter is
@@ -233734,8 +233672,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_cap_window_counter is
wcnt_hcmp_temp : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_cap_window_counter : entity is "ila_v6_2_9_ila_cap_window_counter";
end ila_tx_rx_ila_v6_2_9_ila_cap_window_counter;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_cap_window_counter is
@@ -234143,8 +234079,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_trig_match is
probe4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe5 : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_trig_match : entity is "ila_v6_2_9_ila_trig_match";
end ila_tx_rx_ila_v6_2_9_ila_trig_match;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_trig_match is
@@ -234456,8 +234390,6 @@ entity ila_tx_rx_blk_mem_gen_v8_4_3 is
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_83\ : in STD_LOGIC;
trace_read_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
end ila_tx_rx_blk_mem_gen_v8_4_3;
architecture STRUCTURE of ila_tx_rx_blk_mem_gen_v8_4_3 is
@@ -234589,8 +234521,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_cap_addrgen is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\captured_samples_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_cap_addrgen : entity is "ila_v6_2_9_ila_cap_addrgen";
end ila_tx_rx_ila_v6_2_9_ila_cap_addrgen;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_cap_addrgen is
@@ -236278,8 +236208,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_trigger is
probe4 : in STD_LOGIC_VECTOR ( 15 downto 0 );
probe5 : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_trigger : entity is "ila_v6_2_9_ila_trigger";
end ila_tx_rx_ila_v6_2_9_ila_trigger;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_trigger is
@@ -237707,8 +237635,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_cap_ctrl_legacy is
basic_trigger : in STD_LOGIC;
\captured_samples_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_cap_ctrl_legacy : entity is "ila_v6_2_9_ila_cap_ctrl_legacy";
end ila_tx_rx_ila_v6_2_9_ila_cap_ctrl_legacy;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_cap_ctrl_legacy is
@@ -237999,8 +237925,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_trace_memory is
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_87\ : in STD_LOGIC;
trace_read_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_trace_memory : entity is "ila_v6_2_9_ila_trace_memory";
end ila_tx_rx_ila_v6_2_9_ila_trace_memory;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_trace_memory is
@@ -238136,8 +238060,6 @@ entity ila_tx_rx_ila_v6_2_9_ila_core is
probe0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
DUMMY_I : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila_core : entity is "ila_v6_2_9_ila_core";
end ila_tx_rx_ila_v6_2_9_ila_core;
architecture STRUCTURE of ila_tx_rx_ila_v6_2_9_ila_core is
@@ -262314,8 +262236,6 @@ entity ila_tx_rx_ila_v6_2_9_ila is
attribute LC_TIME_TAG_WIDTH of ila_tx_rx_ila_v6_2_9_ila : entity is 1;
attribute LC_TRIG_WIDTH : integer;
attribute LC_TRIG_WIDTH of ila_tx_rx_ila_v6_2_9_ila : entity is 98;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ila_tx_rx_ila_v6_2_9_ila : entity is "ila_v6_2_9_ila";
attribute dont_touch : string;
attribute dont_touch of ila_tx_rx_ila_v6_2_9_ila : entity is "true";
end ila_tx_rx_ila_v6_2_9_ila;
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_tx_rx/ila_tx_rx_stub.v
+3 -3
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:27:10 2023
// Date : Fri Mar 17 22:27:05 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/ila_tx_rx_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top ila_tx_rx -prefix
// ila_tx_rx_ ila_tx_rx_stub.v
// Design : ila_tx_rx
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/ila_tx_rx/ila_tx_rx_stub.vhdl
+3 -3
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:27:10 2023
-- Date : Fri Mar 17 22:27:05 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/ila_tx_rx_synth_1/ila_tx_rx_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top ila_tx_rx -prefix
-- ila_tx_rx_ ila_tx_rx_stub.vhdl
-- Design : ila_tx_rx
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_sim_netlist.v
+2 -3
View File
@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:22:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top sig_clk_gen -prefix
// sig_clk_gen_ sig_clk_gen_sim_netlist.v
// Design : sig_clk_gen
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -35,7 +35,6 @@ module sig_clk_gen
.reset(reset));
endmodule
(* ORIG_REF_NAME = "sig_clk_gen_clk_wiz" *)
module sig_clk_gen_sig_clk_gen_clk_wiz
(clk_out1,
reset,
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_sim_netlist.vhdl
+2 -4
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top sig_clk_gen -prefix
-- sig_clk_gen_ sig_clk_gen_sim_netlist.vhdl
-- Design : sig_clk_gen
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity sig_clk_gen_sig_clk_gen_clk_wiz is
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sig_clk_gen_sig_clk_gen_clk_wiz : entity is "sig_clk_gen_clk_wiz";
end sig_clk_gen_sig_clk_gen_clk_wiz;
architecture STRUCTURE of sig_clk_gen_sig_clk_gen_clk_wiz is
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.v
+2 -2
View File
@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:22:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top sig_clk_gen -prefix
// sig_clk_gen_ sig_clk_gen_stub.v
// Design : sig_clk_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.vhdl
+2 -2
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/sig_clk_gen_synth_1/sig_clk_gen_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top sig_clk_gen -prefix
-- sig_clk_gen_ sig_clk_gen_stub.vhdl
-- Design : sig_clk_gen
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_manual_ctrl/hdl/vio_v3_0_20_vio_include.v
-283
View File
@@ -1,283 +0,0 @@
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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XWe4lBDDrw==
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
`pragma protect data_block
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`pragma protect end_protected
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v
+4 -9
View File
File diff suppressed because one or more lines are too long
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl
+2 -14
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:39 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top vio_manual_ctrl -prefix
-- vio_manual_ctrl_ vio_manual_ctrl_sim_netlist.vhdl
-- Design : vio_manual_ctrl
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -48,8 +48,6 @@ entity vio_manual_ctrl_vio_v3_0_20_decoder is
\probe_out_modified_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
\xsdb_addr_2_0_p2_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_decoder : entity is "vio_v3_0_20_decoder";
end vio_manual_ctrl_vio_v3_0_20_decoder;
architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_decoder is
@@ -926,8 +924,6 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_out_one is
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_probe_out_one : entity is "vio_v3_0_20_probe_out_one";
end vio_manual_ctrl_vio_v3_0_20_probe_out_one;
architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_one is
@@ -2277,8 +2273,6 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_width is
internal_cnt_rst : in STD_LOGIC;
\out\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_probe_width : entity is "vio_v3_0_20_probe_width";
end vio_manual_ctrl_vio_v3_0_20_probe_width;
architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_width is
@@ -2429,8 +2423,6 @@ entity vio_manual_ctrl_xsdbs_v1_0_2_xsdbs is
attribute C_XDEVICEFAMILY of vio_manual_ctrl_xsdbs_v1_0_2_xsdbs : entity is "zynq";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of vio_manual_ctrl_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_manual_ctrl_xsdbs_v1_0_2_xsdbs : entity is "xsdbs_v1_0_2_xsdbs";
attribute dont_touch : string;
attribute dont_touch of vio_manual_ctrl_xsdbs_v1_0_2_xsdbs : entity is "true";
end vio_manual_ctrl_xsdbs_v1_0_2_xsdbs;
@@ -5415,8 +5407,6 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_out_all is
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
internal_cnt_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_probe_out_all : entity is "vio_v3_0_20_probe_out_all";
end vio_manual_ctrl_vio_v3_0_20_probe_out_all;
architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is
@@ -9204,8 +9194,6 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is
attribute LC_TOTAL_PROBE_IN_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 0;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 41;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_vio : entity is "vio_v3_0_20_vio";
attribute dont_touch : string;
attribute dont_touch of vio_manual_ctrl_vio_v3_0_20_vio : entity is "true";
end vio_manual_ctrl_vio_v3_0_20_vio;
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v
+2 -2
View File
@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:22:39 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top vio_manual_ctrl -prefix
// vio_manual_ctrl_ vio_manual_ctrl_stub.v
// Design : vio_manual_ctrl
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl
+2 -2
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:39 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top vio_manual_ctrl -prefix
-- vio_manual_ctrl_ vio_manual_ctrl_stub.vhdl
-- Design : vio_manual_ctrl
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_rf_control/hdl/vio_v3_0_20_vio_include.v
-283
View File
@@ -1,283 +0,0 @@
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
`pragma protect data_block
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5MGygT2/VAEb4BZAbcRxPGqKcLfYnJZ63t3QEqbgblMA1vFo4VgSV1ajLUyoDGBGLV28ExlwTut1
HzIaED7RvsGxFpR26+1akJ1/8bReaeZFhca9QQVHRvj1X698r4C/XUsrSc+05XtjMx6HM5q1yZwu
pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
hsEprM3gDA7yAWiwAy3nxW57jdofbM5LfU0HVc1mK3FN0pfA/Fg0HWk0RX6K1vbYorZ2YFYwkpIK
Spx8l1Y/4Kpd/0yvO9c4f8OcsEc6LfaQSV83l2H8v6NalHbhaZ2gKxmDZi/k03xDyL8v6GCn18bp
dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
`pragma protect end_protected
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v
+5 -10
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File diff suppressed because one or more lines are too long
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl
+3 -15
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:40 2023
-- Date : Fri Mar 17 22:22:39 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top vio_rf_control -prefix
-- vio_rf_control_ vio_rf_control_sim_netlist.vhdl
-- Design : vio_rf_control
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -46,8 +46,6 @@ entity vio_rf_control_vio_v3_0_20_decoder is
\Bus_data_out_reg[10]_0\ : in STD_LOGIC;
\probe_out_modified_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_rf_control_vio_v3_0_20_decoder : entity is "vio_v3_0_20_decoder";
end vio_rf_control_vio_v3_0_20_decoder;
architecture STRUCTURE of vio_rf_control_vio_v3_0_20_decoder is
@@ -902,8 +900,6 @@ entity vio_rf_control_vio_v3_0_20_probe_out_one is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_rf_control_vio_v3_0_20_probe_out_one : entity is "vio_v3_0_20_probe_out_one";
end vio_rf_control_vio_v3_0_20_probe_out_one;
architecture STRUCTURE of vio_rf_control_vio_v3_0_20_probe_out_one is
@@ -1753,8 +1749,6 @@ entity vio_rf_control_vio_v3_0_20_probe_width is
s_rst_o : in STD_LOGIC;
\out\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_rf_control_vio_v3_0_20_probe_width : entity is "vio_v3_0_20_probe_width";
end vio_rf_control_vio_v3_0_20_probe_width;
architecture STRUCTURE of vio_rf_control_vio_v3_0_20_probe_width is
@@ -1928,8 +1922,6 @@ entity vio_rf_control_xsdbs_v1_0_2_xsdbs is
attribute C_XDEVICEFAMILY of vio_rf_control_xsdbs_v1_0_2_xsdbs : entity is "zynq";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of vio_rf_control_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_rf_control_xsdbs_v1_0_2_xsdbs : entity is "xsdbs_v1_0_2_xsdbs";
attribute dont_touch : string;
attribute dont_touch of vio_rf_control_xsdbs_v1_0_2_xsdbs : entity is "true";
end vio_rf_control_xsdbs_v1_0_2_xsdbs;
@@ -4915,8 +4907,6 @@ entity vio_rf_control_vio_v3_0_20_probe_out_all is
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
xsdb_addr_2_0_p1 : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_rf_control_vio_v3_0_20_probe_out_all : entity is "vio_v3_0_20_probe_out_all";
end vio_rf_control_vio_v3_0_20_probe_out_all;
architecture STRUCTURE of vio_rf_control_vio_v3_0_20_probe_out_all is
@@ -8760,8 +8750,6 @@ entity vio_rf_control_vio_v3_0_20_vio is
attribute LC_TOTAL_PROBE_IN_WIDTH of vio_rf_control_vio_v3_0_20_vio : entity is 0;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_rf_control_vio_v3_0_20_vio : entity is 30;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_rf_control_vio_v3_0_20_vio : entity is "vio_v3_0_20_vio";
attribute dont_touch : string;
attribute dont_touch of vio_rf_control_vio_v3_0_20_vio : entity is "true";
end vio_rf_control_vio_v3_0_20_vio;
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v
+3 -3
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Fri Mar 17 22:22:40 2023
// Date : Fri Mar 17 22:22:39 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top vio_rf_control -prefix
// vio_rf_control_ vio_rf_control_stub.v
// Design : vio_rf_control
// Purpose : Stub declaration of top-level module interface
// Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl
+3 -3
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Fri Mar 17 22:22:40 2023
-- Date : Fri Mar 17 22:22:39 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top vio_rf_control -prefix
-- vio_rf_control_ vio_rf_control_stub.vhdl
-- Design : vio_rf_control
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z100ffg900-2
projects/datalink_814/dl814_dj/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
+671 -671
View File
File diff suppressed because it is too large Load Diff
projects/datalink_814/dl814_dj/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
+531 -531
View File
File diff suppressed because it is too large Load Diff
projects/datalink_814/dl814_dj/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
+671 -671
View File
File diff suppressed because it is too large Load Diff
projects/datalink_814/dl814_dj/ip/ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
+861 -861
View File
File diff suppressed because it is too large Load Diff
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/cmpy_18x8.sh
+4 -6
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -93,11 +93,9 @@ setup()
map_setup_file()
{
file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/compile.do
+3 -3
View File
@@ -20,11 +20,11 @@ vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15
vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17
vlog -work xil_defaultlib -sv2k12 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vcom -work xbip_utils_v3_0_10 -93 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/activehdl/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/cmpy_18x8.sh
+2 -2
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/ies/run.f
+3 -3
View File
@@ -1,9 +1,9 @@
-makelib ies_lib/xil_defaultlib -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib ies_lib/xpm \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib ies_lib/xbip_utils_v3_0_10 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/cmpy_18x8.sh
+3 -3
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -98,7 +98,7 @@ copy_setup_file()
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="C:/Mentor/CompLib/2019.1.3"
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_dj_48m/Mentor/CompLib/2019.1.3"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/compile.do
+39 -1
View File
@@ -2,13 +2,51 @@ vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/xpm
vlib modelsim_lib/msim/xbip_utils_v3_0_10
vlib modelsim_lib/msim/axi_utils_v2_0_6
vlib modelsim_lib/msim/xbip_pipe_v3_0_6
vlib modelsim_lib/msim/xbip_bram18k_v3_0_6
vlib modelsim_lib/msim/mult_gen_v12_0_15
vlib modelsim_lib/msim/cmpy_v6_0_17
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap xpm modelsim_lib/msim/xpm
vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15
vmap cmpy_v6_0_17 modelsim_lib/msim/cmpy_v6_0_17
vlog -work xil_defaultlib -64 -incr -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vcom -work xbip_utils_v3_0_10 -64 -93 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
vcom -work axi_utils_v2_0_6 -64 -93 \
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
vcom -work xbip_pipe_v3_0_6 -64 -93 \
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
vcom -work xbip_bram18k_v3_0_6 -64 -93 \
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
vcom -work mult_gen_v12_0_15 -64 -93 \
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
vcom -work cmpy_v6_0_17 -64 -93 \
"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
vlog -work xil_defaultlib \
"glbl.v"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/file_info.txt
+9
View File
@@ -1,2 +1,11 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/modelsim.ini
-2590
View File
File diff suppressed because it is too large Load Diff
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/modelsim/simulate.do
+1 -1
View File
@@ -1,7 +1,7 @@
onbreak {quit -f}
onerror {quit -f}
vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl
do {wave.do}
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/cmpy_18x8.sh
+4 -5
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -102,11 +102,10 @@ setup()
copy_setup_file()
{
file="modelsim.ini"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_dj/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/compile.do
+3 -3
View File
@@ -20,11 +20,11 @@ vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15
vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17
vlog -work xil_defaultlib -64 -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vcom -work xbip_utils_v3_0_10 -64 -93 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/questa/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/cmpy_18x8.sh
+4 -5
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -93,11 +93,10 @@ setup()
map_setup_file()
{
file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_dj/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/compile.do
+3 -3
View File
@@ -20,11 +20,11 @@ vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15
vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17
vlog -work xil_defaultlib -sv2k12 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vcom -work xbip_utils_v3_0_10 -93 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/riviera/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/cmpy_18x8.sh
+7 -6
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -71,12 +71,12 @@ compile()
{
# Compile design files
vlogan -work xil_defaultlib $vlogan_opts -sverilog \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
2>&1 | tee -a vlogan.log
vhdlan -work xpm $vhdlan_opts \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
@@ -171,9 +171,10 @@ create_lib_mappings()
touch $file
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_dj/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/vcs"
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/vcs/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/cmpy_18x8.sh
+2 -2
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xcelium/run.f
+3 -3
View File
@@ -1,9 +1,9 @@
-makelib xcelium_lib/xil_defaultlib -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib xcelium_lib/xpm \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib xcelium_lib/xbip_utils_v3_0_10 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:02 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:48 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/cmpy_18x8.sh
+4 -4
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:02 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:48 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -22,7 +22,7 @@
#*********************************************************************************************************
# Command line options
xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
xvlog_opts="--relax"
xvhdl_opts="--relax"
@@ -94,7 +94,7 @@ setup()
copy_setup_file()
{
file="xsim.ini"
lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim"
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
fi
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/elab.opt
-1
View File
@@ -1 +0,0 @@
--relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot cmpy_18x8 xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl -log elaborate.log
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/cmpy_18x8/xsim/xsim.ini
-430
View File
@@ -1,430 +0,0 @@
std=$RDI_DATADIR/xsim/vhdl/std
ieee=$RDI_DATADIR/xsim/vhdl/ieee
ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
vl=$RDI_DATADIR/xsim/vhdl/vl
synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
secureip=$RDI_DATADIR/xsim/verilog/secureip
unisim=$RDI_DATADIR/xsim/vhdl/unisim
unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
unifast=$RDI_DATADIR/xsim/vhdl/unifast
unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6
bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8
xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
mipi_dphy_v4_1_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_4
iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4
ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11
common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0
ieee802d3_50g_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_1
convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14
gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14
axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10
pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13
xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
ethernet_1_10_25g_v2_2_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_3
zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0
v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14
v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1
hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14
tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14
blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3
noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0
axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18
axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5
ethernet_1_10_25g_v2_0_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_5
compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5
axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21
qdma_v3_0_2=$RDI_DATADIR/xsim/ip/qdma_v3_0_2
viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11
sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
ba317=$RDI_DATADIR/xsim/ip/ba317
xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4
axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19
cmac_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_v2_5_1
floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8
xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3
common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7
util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1
axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15
tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2
sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2
tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4
tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4
usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5
lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0
ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15
v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0
axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5
cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5
etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2
floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16
axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20
jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5
emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1
axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9
axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21
v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10
jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6
v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13
interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3
uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0
axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3
audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1
lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16
v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5
xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
axi_chip2chip_v5_0_6=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_6
fc32_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_11
v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3
multi_channel_25g_rs_fec_v1_0_5=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_5
in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9
ethernet_1_10_25g_v2_1_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_4
axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18
axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17
axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15
displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1
clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19
vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5
picxo=$RDI_DATADIR/xsim/ip/picxo
usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0
v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13
bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2
axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20
lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14
l_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_2
xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3
axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0
c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13
noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17
c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13
xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14
axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23
noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13
i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3
pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8
mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10
c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14
fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6
microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1
lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12
dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18
me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0
gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6
axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20
nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0
tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3
axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0
axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23
v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1
gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6
lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
ieee802d3_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_5
ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6
high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1
xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1
tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2
hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0
axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20
flexo_100g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_11
v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7
xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15
axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19
noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0
duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15
dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
ieee802d3_200g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_7
sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0
sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11
v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1
axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22
ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7
rama_v1_1_2_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_2_lib
v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13
emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1
hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1
hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1
axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17
proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0
v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16
pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17
axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19
audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13
v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15
axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18
xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18
xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9
pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8
fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12
div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15
mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16
v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11
xxv_ethernet_v2_5_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_3
xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1
axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19
xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6
tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1
util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1
rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7
v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0
dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0
pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2
axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21
high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1
axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3
sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2
gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7
xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1
axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5
axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16
v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13
v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0
axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17
axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21
axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13
advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2
interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
cpri_v8_10_3=$RDI_DATADIR/xsim/ip/cpri_v8_10_3
c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0
stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1
ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22
g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6
blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
tmr_sem_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_9
fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7
axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20
xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20
rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15
axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3
tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15
axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21
noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13
shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18
gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11
amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5
mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21
videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0
cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1
i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3
v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5
remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3
xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2
ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2
xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
cmac_usplus_v2_5_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_3
jesd204c_v4_1_1=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_1
debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3
v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2
v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15
axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19
xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0
axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7
cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17
cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5
ieee802d3_400g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_7
xxv_ethernet_v2_4_5=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_5
axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11
tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18
v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13
dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16
processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7
g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16
c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13
displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11
v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12
sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12
xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6
ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7
oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0
c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13
v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15
zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5
cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14
c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0
pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7
timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16
zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3
v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5
bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15
polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3
rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6
xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15
ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1
high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3
mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11
video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1
axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12
ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16
l_ethernet_v2_4_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_3
dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1
rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0
stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3
pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4
lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9
axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17
cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15
axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19
axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19
axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16
mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15
spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21
v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13
ethernet_1_10_25g_v2_3_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_3
xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18
axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1
axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5
axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
ieee802d3_25g_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_13
aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
xtlm=$RDI_DATADIR/xsim/ip/xtlm
iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4
xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3
perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8
axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20
tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4
v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13
xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9
dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0
lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16
soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0
pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1
sync_ip=$RDI_DATADIR/xsim/ip/sync_ip
v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2
c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
cmac_usplus_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_2
axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5
c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1
lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0
ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0
l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5
microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1
ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3
xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
xpm=$RDI_DATADIR/xsim/ip/xpm
srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6
g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17
noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0
roe_framer_v2_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_1
xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15
can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22
av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0
fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18
lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5
xxv_ethernet_v3_0_3=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_3
axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22
axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1
util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0
v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0
v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13
sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3
xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1
axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0
mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9
axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21
xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:10 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:49 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/compile.do
+3 -3
View File
@@ -26,11 +26,11 @@ vmap xbip_dsp48_multadd_v3_0_6 activehdl/xbip_dsp48_multadd_v3_0_6
vmap dds_compiler_v6_0_18 activehdl/dds_compiler_v6_0_18
vlog -work xil_defaultlib -sv2k12 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vcom -work xbip_utils_v3_0_10 -93 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/dds_32b_8b.sh
+4 -6
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:10 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:49 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -93,11 +93,9 @@ setup()
map_setup_file()
{
file="library.cfg"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/activehdl/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:10 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:49 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/dds_32b_8b.sh
+2 -2
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:10 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:49 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/ies/run.f
+3 -3
View File
@@ -1,9 +1,9 @@
-makelib ies_lib/xil_defaultlib -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib ies_lib/xpm \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib ies_lib/xbip_utils_v3_0_10 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:10 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:49 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/compile.do
+54 -1
View File
@@ -2,13 +2,66 @@ vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/xpm
vlib modelsim_lib/msim/xbip_utils_v3_0_10
vlib modelsim_lib/msim/axi_utils_v2_0_6
vlib modelsim_lib/msim/xbip_pipe_v3_0_6
vlib modelsim_lib/msim/xbip_bram18k_v3_0_6
vlib modelsim_lib/msim/mult_gen_v12_0_15
vlib modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4
vlib modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6
vlib modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6
vlib modelsim_lib/msim/dds_compiler_v6_0_18
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap xpm modelsim_lib/msim/xpm
vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15
vmap xbip_dsp48_wrapper_v3_0_4 modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4
vmap xbip_dsp48_addsub_v3_0_6 modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6
vmap xbip_dsp48_multadd_v3_0_6 modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6
vmap dds_compiler_v6_0_18 modelsim_lib/msim/dds_compiler_v6_0_18
vlog -work xil_defaultlib -64 -incr -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vcom -work xbip_utils_v3_0_10 -64 -93 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
vcom -work axi_utils_v2_0_6 -64 -93 \
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
vcom -work xbip_pipe_v3_0_6 -64 -93 \
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
vcom -work xbip_bram18k_v3_0_6 -64 -93 \
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
vcom -work mult_gen_v12_0_15 -64 -93 \
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
vcom -work xbip_dsp48_wrapper_v3_0_4 -64 -93 \
"../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd" \
vcom -work xbip_dsp48_addsub_v3_0_6 -64 -93 \
"../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd" \
vcom -work xbip_dsp48_multadd_v3_0_6 -64 -93 \
"../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd" \
vcom -work dds_compiler_v6_0_18 -64 -93 \
"../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../ip/dds_32b_8b/sim/dds_32b_8b.vhd" \
vlog -work xil_defaultlib \
"glbl.v"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/dds_32b_8b.sh
+3 -3
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:10 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:49 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -98,7 +98,7 @@ copy_setup_file()
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="C:/Mentor/CompLib/2019.1.3"
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_dj_48m/Mentor/CompLib/2019.1.3"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/file_info.txt
+12
View File
@@ -1,2 +1,14 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
xbip_dsp48_addsub_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_addsub_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd,
xbip_dsp48_multadd_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_multadd_v3_0_6,../../../ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd,
dds_compiler_v6_0_vh_rfs.vhd,vhdl,dds_compiler_v6_0_18,../../../ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd,
dds_32b_8b.vhd,vhdl,xil_defaultlib,../../../ip/dds_32b_8b/sim/dds_32b_8b.vhd,
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/modelsim.ini
-2590
View File
File diff suppressed because it is too large Load Diff
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/modelsim/simulate.do
+1 -1
View File
@@ -1,7 +1,7 @@
onbreak {quit -f}
onerror {quit -f}
vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.dds_32b_8b xil_defaultlib.glbl
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_18 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.dds_32b_8b xil_defaultlib.glbl
do {wave.do}
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:10 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:49 CST 2023
#
################################################################################
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/compile.do
+3 -3
View File
@@ -26,11 +26,11 @@ vmap xbip_dsp48_multadd_v3_0_6 questa_lib/msim/xbip_dsp48_multadd_v3_0_6
vmap dds_compiler_v6_0_18 questa_lib/msim/dds_compiler_v6_0_18
vlog -work xil_defaultlib -64 -sv \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vcom -work xbip_utils_v3_0_10 -64 -93 \
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/dds_32b_8b.sh
+4 -5
View File
@@ -9,8 +9,8 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Fri Mar 17 22:22:10 +0800 2023
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
# Generated by Vivado on Sun Mar 26 12:23:49 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
@@ -102,11 +102,10 @@ setup()
copy_setup_file()
{
file="modelsim.ini"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_dj/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/questa/file_info.txt
+3 -3
View File
@@ -1,6 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
projects/datalink_814/dl814_dj/ip/ip_user_files/sim_scripts/dds_32b_8b/riviera/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Fri Mar 17 22:22:10 +0800 2023
# Generated by export_simulation on Sun Mar 26 12:23:49 CST 2023
#
################################################################################

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