Archived
revise dl814_dj_48m
the data counter of module tx_pn_seq was mod-32, now modified to mod-128 to cover the whole pn cycle
This commit is contained in:
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NumberHits:1
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Timestamp: Sun Mar 26 04:23:47 UTC 2023
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+2
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NumberHits:1
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Timestamp: Sun Mar 26 04:23:47 UTC 2023
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+2
@@ -0,0 +1,2 @@
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NumberHits:1
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Timestamp: Sun Mar 26 04:23:43 UTC 2023
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+2
@@ -0,0 +1,2 @@
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NumberHits:1
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||||
Timestamp: Sun Mar 26 04:23:47 UTC 2023
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+2
@@ -0,0 +1,2 @@
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NumberHits:1
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Timestamp: Sun Mar 26 04:23:45 UTC 2023
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+2
@@ -0,0 +1,2 @@
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NumberHits:1
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||||
Timestamp: Sun Mar 26 04:23:44 UTC 2023
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+2
@@ -0,0 +1,2 @@
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NumberHits:1
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||||
Timestamp: Sun Mar 26 04:23:43 UTC 2023
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||||
+2
@@ -0,0 +1,2 @@
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NumberHits:1
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||||
Timestamp: Sun Mar 26 04:23:47 UTC 2023
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||||
+2
@@ -0,0 +1,2 @@
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||||
NumberHits:1
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||||
Timestamp: Sun Mar 26 04:23:42 UTC 2023
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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+1
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eof:
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||||
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||||
+23
-12
@@ -3,7 +3,7 @@
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||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pa" timeStamp="Fri Mar 17 23:49:11 2023">
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<application name="pa" timeStamp="Sun Mar 26 12:24:14 2023">
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<property name="ProjectIteration" value="1" type="ProjectIteration"/>
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@@ -18,31 +18,42 @@ This means code written to parse this file will need to be revisited each subseq
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</item>
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<item name="Java Command Handlers">
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<property name="AddExistingIPHandler" value="1" type="JavaHandler"/>
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||||
<property name="OpenIPLocationHandler" value="1" type="JavaHandler"/>
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||||
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||||
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||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="24" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="4" type="GuiHandlerData"/>
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||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="31" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="2" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
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||||
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||||
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|
||||
<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
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||||
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||||
<property name="PACommandNames_ADD_EXISTING_IP" value="1" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="4" type="GuiHandlerData"/>
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||||
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||||
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="1" type="GuiHandlerData"/>
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||||
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|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="3" type="GuiHandlerData"/>
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||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="3" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="2" type="GuiHandlerData"/>
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||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="4" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="3" type="GuiHandlerData"/>
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||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="2" type="GuiHandlerData"/>
|
||||
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||||
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|
||||
<property name="GuiMode" value="44" type="GuiMode"/>
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
</application>
|
||||
|
||||
-5
@@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="14168" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
-270
@@ -1,270 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
-155
@@ -1,155 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7z100ffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1 -new_name cmpy_18x8 -ip [get_ips cmpy_18x8]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top cmpy_18x8 -part xc7z100ffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix cmpy_18x8_ cmpy_18x8.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_stub.v
|
||||
lappend ipCachedFiles cmpy_18x8_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_stub.vhdl
|
||||
lappend ipCachedFiles cmpy_18x8_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_sim_netlist.v
|
||||
lappend ipCachedFiles cmpy_18x8_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x8_sim_netlist.vhdl
|
||||
lappend ipCachedFiles cmpy_18x8_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp cmpy_18x8.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips cmpy_18x8]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all cmpy_18x8_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef cmpy_18x8.dcp
|
||||
create_report "cmpy_18x8_synth_1_synth_report_utilization_0" "report_utilization -file cmpy_18x8_utilization_synth.rpt -pb cmpy_18x8_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v -of_objects [get_files D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.v -of_objects [get_files D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.dcp -of_objects [get_files D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_sim_netlist.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/cmpy_18x8
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
-393
@@ -1,393 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Fri Mar 17 22:22:03 2023
|
||||
# Process ID: 2888
|
||||
# Current directory: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1
|
||||
# Command line: vivado.exe -log cmpy_18x8.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl
|
||||
# Log file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.vds
|
||||
# Journal file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source cmpy_18x8.tcl -notrace
|
||||
Command: synth_design -top cmpy_18x8 -part xc7z100ffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 31612
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 920.344 ; gain = 177.000
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'cmpy_18x8' [d:/vivado-git/datalink_814/ip/cmpy_18x8/synth/cmpy_18x8.vhd:71]
|
||||
Parameter C_VERBOSITY bound to: 0 - type: integer
|
||||
Parameter C_XDEVICEFAMILY bound to: zynq - type: string
|
||||
Parameter C_XDEVICE bound to: xc7z100 - type: string
|
||||
Parameter C_A_WIDTH bound to: 18 - type: integer
|
||||
Parameter C_B_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_OUT_WIDTH bound to: 27 - type: integer
|
||||
Parameter C_LATENCY bound to: 4 - type: integer
|
||||
Parameter C_MULT_TYPE bound to: 0 - type: integer
|
||||
Parameter C_OPTIMIZE_GOAL bound to: 0 - type: integer
|
||||
Parameter HAS_NEGATE bound to: 0 - type: integer
|
||||
Parameter SINGLE_OUTPUT bound to: 0 - type: integer
|
||||
Parameter ROUND bound to: 0 - type: integer
|
||||
Parameter USE_DSP_CASCADES bound to: 1 - type: integer
|
||||
Parameter C_THROTTLE_SCHEME bound to: 3 - type: integer
|
||||
Parameter C_HAS_ACLKEN bound to: 0 - type: integer
|
||||
Parameter C_HAS_ARESETN bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_A_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_A_TLAST bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_B_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_B_TLAST bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CTRL_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CTRL_TLAST bound to: 0 - type: integer
|
||||
Parameter C_TLAST_RESOLUTION bound to: 0 - type: integer
|
||||
Parameter C_S_AXIS_A_TDATA_WIDTH bound to: 48 - type: integer
|
||||
Parameter C_S_AXIS_A_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_S_AXIS_B_TDATA_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_S_AXIS_B_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_S_AXIS_CTRL_TDATA_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_S_AXIS_CTRL_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TDATA_WIDTH bound to: 64 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TUSER_WIDTH bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'cmpy_v6_0_17' declared at 'd:/vivado-git/datalink_814/ip/cmpy_18x8/hdl/cmpy_v6_0_vh_rfs.vhd:13922' bound to instance 'U0' of component 'cmpy_v6_0_17' [d:/vivado-git/datalink_814/ip/cmpy_18x8/synth/cmpy_18x8.vhd:155]
|
||||
INFO: [Synth 8-256] done synthesizing module 'cmpy_18x8' (10#1) [d:/vivado-git/datalink_814/ip/cmpy_18x8/synth/cmpy_18x8.vhd:71]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized1 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line__parameterized0 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_R
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port NEGATE_I
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design input_negation has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port ROUND_CY
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_synth has unconnected port SO_START
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_delay_line has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[47]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[46]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[45]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[44]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[43]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[42]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[23]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[22]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[21]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[20]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[19]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[18]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tvalid
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[7]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[6]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[5]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[4]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[3]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[2]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[1]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port m_axis_dout_tready
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 1058.410 ; gain = 315.066
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1058.410 ; gain = 315.066
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1058.410 ; gain = 315.066
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 708 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1126.453 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 232 instances were transformed.
|
||||
MULT_AND => LUT2: 232 instances
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1136.645 ; gain = 10.191
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z100ffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 2020 (col length:140)
|
||||
BRAMs: 1510 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv__parameterized0 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design mult_gen_v12_0_15_viv has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aclken
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port aresetn
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[47]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[46]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[45]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[44]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[43]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[42]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[23]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[22]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[21]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[20]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[19]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_a_tdata[18]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_b_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tvalid
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tlast
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[7]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[6]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[5]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[4]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[3]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[2]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[1]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port s_axis_ctrl_tdata[0]
|
||||
WARNING: [Synth 8-3331] design cmpy_v6_0_17_viv has unconnected port m_axis_dout_tready
|
||||
INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][20]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][19]'
|
||||
INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][21]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][19]'
|
||||
INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][22]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[2][19]'
|
||||
INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[0][21]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[0][22]'
|
||||
INFO: [Synth 8-3886] merging instance 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[1][21]' (FDR) to 'mult_gen_v12_0_15_viv:/gLUT.gLUT_speed.iLUT/NxM_mult.stage_1_add.stage_1_pipeline.s1_add_out_reg[1][22]'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |CARRY4 | 87|
|
||||
|2 |LUT1 | 11|
|
||||
|3 |LUT2 | 297|
|
||||
|4 |LUT3 | 62|
|
||||
|5 |LUT4 | 208|
|
||||
|6 |MULT_AND | 229|
|
||||
|7 |MUXCY | 232|
|
||||
|8 |SRL16E | 1|
|
||||
|9 |XORCY | 244|
|
||||
|10 |FDRE | 430|
|
||||
+------+---------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 34 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:25 . Memory (MB): peak = 1136.645 ; gain = 315.066
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 1136.645 ; gain = 393.301
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 792 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1145.945 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 293 instances were transformed.
|
||||
(MUXCY,XORCY) => CARRY4: 64 instances
|
||||
MULT_AND => LUT2: 229 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 84 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:35 . Memory (MB): peak = 1145.945 ; gain = 761.527
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1145.945 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP cmpy_18x8, cache-ID = fc8a790122720d8a
|
||||
INFO: [Coretcl 2-1174] Renamed 11 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1145.945 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file cmpy_18x8_utilization_synth.rpt -pb cmpy_18x8_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Mar 17 22:22:44 2023...
|
||||
-9282
File diff suppressed because it is too large
Load Diff
-12962
File diff suppressed because it is too large
Load Diff
-27
@@ -1,27 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Fri Mar 17 22:22:44 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
|
||||
// Design : cmpy_18x8
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
|
||||
module cmpy_18x8(aclk, s_axis_a_tvalid, s_axis_a_tdata,
|
||||
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */;
|
||||
input aclk;
|
||||
input s_axis_a_tvalid;
|
||||
input [47:0]s_axis_a_tdata;
|
||||
input s_axis_b_tvalid;
|
||||
input [15:0]s_axis_b_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [63:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
-36
@@ -1,36 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Fri Mar 17 22:22:44 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
|
||||
-- Design : cmpy_18x8
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity cmpy_18x8 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_a_tvalid : in STD_LOGIC;
|
||||
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
s_axis_b_tvalid : in STD_LOGIC;
|
||||
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
|
||||
end cmpy_18x8;
|
||||
|
||||
architecture stub of cmpy_18x8 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
-182
@@ -1,182 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Fri Mar 17 22:22:44 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file cmpy_18x8_utilization_synth.rpt -pb cmpy_18x8_utilization_synth.pb
|
||||
| Design : cmpy_18x8
|
||||
| Device : 7z100ffg900-2
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 565 | 0 | 277400 | 0.20 |
|
||||
| LUT as Logic | 564 | 0 | 277400 | 0.20 |
|
||||
| LUT as Memory | 1 | 0 | 108200 | <0.01 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 1 | 0 | | |
|
||||
| Slice Registers | 430 | 0 | 554800 | 0.08 |
|
||||
| Register as Flip Flop | 430 | 0 | 554800 | 0.08 |
|
||||
| Register as Latch | 0 | 0 | 554800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 138700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 69350 | 0.00 |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 430 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 1510 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 2020 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 362 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 348 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 362 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 362 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT2 | 526 | LUT |
|
||||
| FDRE | 430 | Flop & Latch |
|
||||
| LUT4 | 208 | LUT |
|
||||
| CARRY4 | 151 | CarryLogic |
|
||||
| LUT3 | 62 | LUT |
|
||||
| LUT1 | 11 | LUT |
|
||||
| SRL16E | 1 | Distributed Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci
|
||||
# IP: The module: 'cmpy_18x8' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'cmpy_18x8'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8.xci
|
||||
# IP: The module: 'cmpy_18x8' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/cmpy_18x8/cmpy_18x8_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'cmpy_18x8'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
-64
@@ -1,64 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_18x8_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1679062919">
|
||||
<File Type="PA-TCL" Name="cmpy_18x8.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="cmpy_18x8_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="cmpy_18x8_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_18x8.vds"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_18x8_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_18x8_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_18x8.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="cmpy_18x8_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="cmpy_18x8_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8">
|
||||
<File Path="$PPRDIR/../cmpy_18x8/cmpy_18x8.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../cmpy_18x8.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="cmpy_18x8"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8">
|
||||
<File Path="$PPRDIR/../cmpy_18x8/cmpy_18x8.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../cmpy_18x8.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="cmpy_18x8"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
-9
@@ -1,9 +0,0 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log cmpy_18x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl
|
||||
-40
@@ -1,40 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31387838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f3862:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c686f705f726f6d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6872635f36345f31325f303235:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f6374726c5f7369676e616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f74785f7278:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c7369675f636c6b5f67656e:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:39:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6466383235613631313535333430343961333865326262336238653431393135:506172656e742050412070726f6a656374204944:00
|
||||
eof:1302407817
|
||||
-36
@@ -1,36 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log cmpy_18x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
-10
@@ -1,10 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
-43
@@ -1,43 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log cmpy_18x8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cmpy_18x8.tcl
|
||||
BIN
Binary file not shown.
-5
@@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="18612" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
-270
@@ -1,270 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
-155
@@ -1,155 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7z100ffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1 -new_name dds_32b_8b -ip [get_ips dds_32b_8b]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top dds_32b_8b -part xc7z100ffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix dds_32b_8b_ dds_32b_8b.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_stub.v
|
||||
lappend ipCachedFiles dds_32b_8b_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_stub.vhdl
|
||||
lappend ipCachedFiles dds_32b_8b_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_sim_netlist.v
|
||||
lappend ipCachedFiles dds_32b_8b_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_32b_8b_sim_netlist.vhdl
|
||||
lappend ipCachedFiles dds_32b_8b_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp dds_32b_8b.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips dds_32b_8b]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all dds_32b_8b_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef dds_32b_8b.dcp
|
||||
create_report "dds_32b_8b_synth_1_synth_report_utilization_0" "report_utilization -file dds_32b_8b_utilization_synth.rpt -pb dds_32b_8b_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v -of_objects [get_files D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.v -of_objects [get_files D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.dcp -of_objects [get_files D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_sim_netlist.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/dds_32b_8b
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
-423
@@ -1,423 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Fri Mar 17 22:22:03 2023
|
||||
# Process ID: 17772
|
||||
# Current directory: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1
|
||||
# Command line: vivado.exe -log dds_32b_8b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl
|
||||
# Log file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.vds
|
||||
# Journal file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source dds_32b_8b.tcl -notrace
|
||||
Command: synth_design -top dds_32b_8b -part xc7z100ffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 35924
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 921.586 ; gain = 177.355
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'dds_32b_8b' [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:69]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_pinc_in' is missing in component declaration [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_poff_in' is missing in component declaration [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_resync_in' is missing in component declaration [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_axi_chan_in' is missing in component declaration [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_core_nd' is missing in component declaration [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_phase' is missing in component declaration [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
WARNING: [Synth 8-5640] Port 'debug_phase_nd' is missing in component declaration [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:72]
|
||||
Parameter C_XDEVICEFAMILY bound to: zynq - type: string
|
||||
Parameter C_MODE_OF_OPERATION bound to: 0 - type: integer
|
||||
Parameter C_MODULUS bound to: 9 - type: integer
|
||||
Parameter C_ACCUMULATOR_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_CHANNELS bound to: 1 - type: integer
|
||||
Parameter C_HAS_PHASE_OUT bound to: 0 - type: integer
|
||||
Parameter C_HAS_PHASEGEN bound to: 1 - type: integer
|
||||
Parameter C_HAS_SINCOS bound to: 1 - type: integer
|
||||
Parameter C_LATENCY bound to: 3 - type: integer
|
||||
Parameter C_MEM_TYPE bound to: 1 - type: integer
|
||||
Parameter C_NEGATIVE_COSINE bound to: 0 - type: integer
|
||||
Parameter C_NEGATIVE_SINE bound to: 0 - type: integer
|
||||
Parameter C_NOISE_SHAPING bound to: 0 - type: integer
|
||||
Parameter C_OUTPUTS_REQUIRED bound to: 2 - type: integer
|
||||
Parameter C_OUTPUT_FORM bound to: 0 - type: integer
|
||||
Parameter C_OUTPUT_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_PHASE_ANGLE_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_PHASE_INCREMENT bound to: 1 - type: integer
|
||||
Parameter C_PHASE_INCREMENT_VALUE bound to: 10101010101010101,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - type: string
|
||||
Parameter C_RESYNC bound to: 0 - type: integer
|
||||
Parameter C_PHASE_OFFSET bound to: 0 - type: integer
|
||||
Parameter C_PHASE_OFFSET_VALUE bound to: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - type: string
|
||||
Parameter C_OPTIMISE_GOAL bound to: 0 - type: integer
|
||||
Parameter C_USE_DSP48 bound to: 0 - type: integer
|
||||
Parameter C_POR_MODE bound to: 0 - type: integer
|
||||
Parameter C_AMPLITUDE bound to: 0 - type: integer
|
||||
Parameter C_HAS_ACLKEN bound to: 0 - type: integer
|
||||
Parameter C_HAS_ARESETN bound to: 0 - type: integer
|
||||
Parameter C_HAS_TLAST bound to: 0 - type: integer
|
||||
Parameter C_HAS_TREADY bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_PHASE bound to: 0 - type: integer
|
||||
Parameter C_S_PHASE_TDATA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_S_PHASE_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_S_PHASE_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_CONFIG bound to: 1 - type: integer
|
||||
Parameter C_S_CONFIG_SYNC_MODE bound to: 0 - type: integer
|
||||
Parameter C_S_CONFIG_TDATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_HAS_M_DATA bound to: 1 - type: integer
|
||||
Parameter C_M_DATA_TDATA_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_M_PHASE bound to: 0 - type: integer
|
||||
Parameter C_M_PHASE_TDATA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_M_PHASE_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_M_PHASE_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_DEBUG_INTERFACE bound to: 0 - type: integer
|
||||
Parameter C_CHAN_WIDTH bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'dds_compiler_v6_0_18' declared at 'd:/vivado-git/datalink_814/ip/dds_32b_8b/hdl/dds_compiler_v6_0_vh_rfs.vhd:47308' bound to instance 'U0' of component 'dds_compiler_v6_0_18' [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:174]
|
||||
INFO: [Synth 8-256] done synthesizing module 'dds_32b_8b' (9#1) [d:/vivado-git/datalink_814/ip/dds_32b_8b/synth/dds_32b_8b.vhd:69]
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized9 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized15 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized13 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized11 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design sin_cos has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized7 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized5 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv__parameterized3 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port chan_addr[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port chan_addr_del2[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port chan_addr_del3[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[3]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[2]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[1]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port addr_i[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port phase_inc_we
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port phase_adj_we
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[31]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[30]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[29]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[28]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[27]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[26]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[25]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[24]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[23]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[22]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[21]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[20]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[19]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[18]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[17]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[16]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[15]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[14]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[13]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[12]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[11]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[10]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[9]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[8]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[7]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[6]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[5]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[4]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[3]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[2]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[1]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port poff_in[0]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[31]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[30]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[29]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[28]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[27]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[26]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[25]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[24]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[23]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[22]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[21]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[20]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[19]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[18]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[17]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[16]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[15]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[14]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[13]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[12]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[11]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[10]
|
||||
WARNING: [Synth 8-3331] design accum has unconnected port data_i[9]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1041.414 ; gain = 297.184
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1041.414 ; gain = 297.184
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1041.414 ; gain = 297.184
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1105.250 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1115.781 ; gain = 10.531
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z100ffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-7031] Trying to map ROM "sin_cos_lut" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
INFO: [Synth 8-7031] Trying to map ROM "sin_cos_lut" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 2020 (col length:140)
|
||||
BRAMs: 1510 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance U0/i_synth/i_0/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
INFO: [Synth 8-6837] The timing for the instance U0/i_synth/i_1/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----------+------+
|
||||
| |Cell |Count |
|
||||
+------+-----------+------+
|
||||
|1 |CARRY4 | 9|
|
||||
|2 |LUT2 | 35|
|
||||
|3 |RAMB18E1_2 | 1|
|
||||
|4 |FDRE | 72|
|
||||
+------+-----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 14 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:05 ; elapsed = 00:00:23 . Memory (MB): peak = 1115.781 ; gain = 297.184
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1115.781 ; gain = 371.551
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1141.906 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 107 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 1141.906 ; gain = 754.984
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1141.906 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP dds_32b_8b, cache-ID = 971cef6a07d69819
|
||||
INFO: [Coretcl 2-1174] Renamed 11 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1141.906 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file dds_32b_8b_utilization_synth.rpt -pb dds_32b_8b_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Mar 17 22:22:41 2023...
|
||||
-1481
File diff suppressed because it is too large
Load Diff
-1869
File diff suppressed because it is too large
Load Diff
-25
@@ -1,25 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Fri Mar 17 22:22:40 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
|
||||
// Design : dds_32b_8b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
|
||||
module dds_32b_8b(aclk, s_axis_config_tvalid,
|
||||
s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_config_tvalid;
|
||||
input [31:0]s_axis_config_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
-34
@@ -1,34 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Fri Mar 17 22:22:40 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
|
||||
-- Design : dds_32b_8b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity dds_32b_8b is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_config_tvalid : in STD_LOGIC;
|
||||
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end dds_32b_8b;
|
||||
|
||||
architecture stub of dds_32b_8b is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
-178
@@ -1,178 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Fri Mar 17 22:22:40 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file dds_32b_8b_utilization_synth.rpt -pb dds_32b_8b_utilization_synth.pb
|
||||
| Design : dds_32b_8b
|
||||
| Device : 7z100ffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 34 | 0 | 277400 | 0.01 |
|
||||
| LUT as Logic | 34 | 0 | 277400 | 0.01 |
|
||||
| LUT as Memory | 0 | 0 | 108200 | 0.00 |
|
||||
| Slice Registers | 72 | 0 | 554800 | 0.01 |
|
||||
| Register as Flip Flop | 72 | 0 | 554800 | 0.01 |
|
||||
| Register as Latch | 0 | 0 | 554800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 138700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 69350 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 72 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0.5 | 0 | 755 | 0.07 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB18 | 1 | 0 | 1510 | 0.07 |
|
||||
| RAMB18E1 only | 1 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 2020 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 362 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 348 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 362 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 362 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 72 | Flop & Latch |
|
||||
| LUT2 | 35 | LUT |
|
||||
| CARRY4 | 9 | CarryLogic |
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci
|
||||
# IP: The module: 'dds_32b_8b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'dds_32b_8b'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b.xci
|
||||
# IP: The module: 'dds_32b_8b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/dds_32b_8b/dds_32b_8b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'dds_32b_8b'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
-64
@@ -1,64 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="dds_32b_8b_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1679062920">
|
||||
<File Type="PA-TCL" Name="dds_32b_8b.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="dds_32b_8b_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="dds_32b_8b_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="dds_32b_8b.vds"/>
|
||||
<File Type="RDS-UTIL" Name="dds_32b_8b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="dds_32b_8b_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="dds_32b_8b.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="dds_32b_8b_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="dds_32b_8b_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b">
|
||||
<File Path="$PPRDIR/../dds_32b_8b/dds_32b_8b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../dds_32b_8b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="dds_32b_8b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b">
|
||||
<File Path="$PPRDIR/../dds_32b_8b/dds_32b_8b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../dds_32b_8b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="dds_32b_8b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
-9
@@ -1,9 +0,0 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log dds_32b_8b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl
|
||||
-40
@@ -1,40 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31387838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f3862:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c686f705f726f6d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6872635f36345f31325f303235:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f6374726c5f7369676e616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f74785f7278:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c7369675f636c6b5f67656e:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:39:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6466383235613631313535333430343961333865326262336238653431393135:506172656e742050412070726f6a656374204944:00
|
||||
eof:1302407817
|
||||
-36
@@ -1,36 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log dds_32b_8b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
-10
@@ -1,10 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
-43
@@ -1,43 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log dds_32b_8b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_32b_8b.tcl
|
||||
BIN
Binary file not shown.
-5
@@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="37744" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
-270
@@ -1,270 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci
|
||||
# IP: The module: 'hop_rom' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/hop_rom/hop_rom_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hop_rom'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci
|
||||
# IP: The module: 'hop_rom' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/hop_rom/hop_rom_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hop_rom'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
-64
@@ -1,64 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="hop_rom_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1679062920">
|
||||
<File Type="PA-TCL" Name="hop_rom.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="hop_rom_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="hop_rom_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="hop_rom.vds"/>
|
||||
<File Type="RDS-UTIL" Name="hop_rom_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="hop_rom_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="hop_rom.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="hop_rom_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="hop_rom_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom">
|
||||
<File Path="$PPRDIR/../hop_rom/hop_rom.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../hop_rom.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hop_rom"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom">
|
||||
<File Path="$PPRDIR/../hop_rom/hop_rom.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../hop_rom.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hop_rom"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
BIN
Binary file not shown.
-155
@@ -1,155 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7z100ffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/datalink_814/ip/hop_rom/hop_rom_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1 -new_name hop_rom -ip [get_ips hop_rom]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top hop_rom -part xc7z100ffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix hop_rom_ hop_rom.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_stub.v
|
||||
lappend ipCachedFiles hop_rom_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_stub.vhdl
|
||||
lappend ipCachedFiles hop_rom_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_sim_netlist.v
|
||||
lappend ipCachedFiles hop_rom_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hop_rom_sim_netlist.vhdl
|
||||
lappend ipCachedFiles hop_rom_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp hop_rom.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips hop_rom]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all hop_rom_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef hop_rom.dcp
|
||||
create_report "hop_rom_synth_1_synth_report_utilization_0" "report_utilization -file hop_rom_utilization_synth.rpt -pb hop_rom_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v -of_objects [get_files D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v -of_objects [get_files D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.dcp -of_objects [get_files D:/vivado-git/datalink_814/ip/hop_rom/hop_rom.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_sim_netlist.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/hop_rom
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
-459
@@ -1,459 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Fri Mar 17 22:22:03 2023
|
||||
# Process ID: 13316
|
||||
# Current directory: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1
|
||||
# Command line: vivado.exe -log hop_rom.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl
|
||||
# Log file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.vds
|
||||
# Journal file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source hop_rom.tcl -notrace
|
||||
Command: synth_design -top hop_rom -part xc7z100ffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 2076
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 920.816 ; gain = 176.984
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'hop_rom' [d:/vivado-git/datalink_814/ip/hop_rom/synth/hop_rom.vhd:67]
|
||||
Parameter C_FAMILY bound to: zynq - type: string
|
||||
Parameter C_XDEVICEFAMILY bound to: zynq - type: string
|
||||
Parameter C_ELABORATION_DIR bound to: ./ - type: string
|
||||
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
|
||||
Parameter C_AXI_TYPE bound to: 1 - type: integer
|
||||
Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer
|
||||
Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer
|
||||
Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer
|
||||
Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string
|
||||
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
|
||||
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_MEM_TYPE bound to: 3 - type: integer
|
||||
Parameter C_BYTE_SIZE bound to: 9 - type: integer
|
||||
Parameter C_ALGORITHM bound to: 1 - type: integer
|
||||
Parameter C_PRIM_TYPE bound to: 1 - type: integer
|
||||
Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer
|
||||
Parameter C_INIT_FILE_NAME bound to: hop_rom.mif - type: string
|
||||
Parameter C_INIT_FILE bound to: hop_rom.mem - type: string
|
||||
Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer
|
||||
Parameter C_DEFAULT_DATA bound to: 0 - type: string
|
||||
Parameter C_HAS_RSTA bound to: 0 - type: integer
|
||||
Parameter C_RST_PRIORITY_A bound to: CE - type: string
|
||||
Parameter C_RSTRAM_A bound to: 0 - type: integer
|
||||
Parameter C_INITA_VAL bound to: 0 - type: string
|
||||
Parameter C_HAS_ENA bound to: 0 - type: integer
|
||||
Parameter C_HAS_REGCEA bound to: 0 - type: integer
|
||||
Parameter C_USE_BYTE_WEA bound to: 0 - type: integer
|
||||
Parameter C_WEA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string
|
||||
Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer
|
||||
Parameter C_READ_WIDTH_A bound to: 32 - type: integer
|
||||
Parameter C_WRITE_DEPTH_A bound to: 256 - type: integer
|
||||
Parameter C_READ_DEPTH_A bound to: 256 - type: integer
|
||||
Parameter C_ADDRA_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_HAS_RSTB bound to: 0 - type: integer
|
||||
Parameter C_RST_PRIORITY_B bound to: CE - type: string
|
||||
Parameter C_RSTRAM_B bound to: 0 - type: integer
|
||||
Parameter C_INITB_VAL bound to: 0 - type: string
|
||||
Parameter C_HAS_ENB bound to: 0 - type: integer
|
||||
Parameter C_HAS_REGCEB bound to: 0 - type: integer
|
||||
Parameter C_USE_BYTE_WEB bound to: 0 - type: integer
|
||||
Parameter C_WEB_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string
|
||||
Parameter C_WRITE_WIDTH_B bound to: 32 - type: integer
|
||||
Parameter C_READ_WIDTH_B bound to: 32 - type: integer
|
||||
Parameter C_WRITE_DEPTH_B bound to: 256 - type: integer
|
||||
Parameter C_READ_DEPTH_B bound to: 256 - type: integer
|
||||
Parameter C_ADDRB_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer
|
||||
Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 1 - type: integer
|
||||
Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer
|
||||
Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer
|
||||
Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_USE_SOFTECC bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC bound to: 0 - type: integer
|
||||
Parameter C_EN_ECC_PIPE bound to: 0 - type: integer
|
||||
Parameter C_READ_LATENCY_A bound to: 1 - type: integer
|
||||
Parameter C_READ_LATENCY_B bound to: 1 - type: integer
|
||||
Parameter C_HAS_INJECTERR bound to: 0 - type: integer
|
||||
Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string
|
||||
Parameter C_COMMON_CLK bound to: 0 - type: integer
|
||||
Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer
|
||||
Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer
|
||||
Parameter C_USE_URAM bound to: 0 - type: integer
|
||||
Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer
|
||||
Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer
|
||||
Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer
|
||||
Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer
|
||||
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
|
||||
Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer
|
||||
Parameter C_COUNT_36K_BRAM bound to: 0 - type: string
|
||||
Parameter C_COUNT_18K_BRAM bound to: 1 - type: string
|
||||
Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 3.375199 mW - type: string
|
||||
INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at 'd:/vivado-git/datalink_814/ip/hop_rom/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [d:/vivado-git/datalink_814/ip/hop_rom/synth/hop_rom.vhd:230]
|
||||
INFO: [Synth 8-256] done synthesizing module 'hop_rom' (9#1) [d:/vivado-git/datalink_814/ip/hop_rom/synth/hop_rom.vhd:67]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[35]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[34]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[33]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[32]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[31]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[30]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[29]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[28]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[27]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[26]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[25]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[24]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[23]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[22]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[21]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[20]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[19]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[18]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[17]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[16]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[15]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[14]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[13]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[12]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[11]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[10]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[9]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstram_b
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstreg_b
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port REGCEB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[31]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[30]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[29]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[28]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[27]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[26]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[25]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[24]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[23]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[22]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[21]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[20]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[19]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[18]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[17]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[16]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1196.602 ; gain = 452.770
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1196.602 ; gain = 452.770
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:38 . Memory (MB): peak = 1196.602 ; gain = 452.770
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/datalink_814/ip/hop_rom/hop_rom_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/datalink_814/ip/hop_rom/hop_rom_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1214.109 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1214.625 ; gain = 0.516
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:43 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z100ffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:43 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:43 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:43 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
32 Bit Registers := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module blk_mem_gen_generic_cstr
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
32 Bit Registers := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 2020 (col length:140)
|
||||
BRAMs: 1510 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:44 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:49 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:49 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:49 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:50 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:50 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:50 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:50 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:50 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:50 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |RAMB18E1 | 1|
|
||||
|2 |FDRE | 32|
|
||||
+------+---------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
|1 |top | | 33|
|
||||
|2 | U0 |blk_mem_gen_v8_4_3 | 33|
|
||||
|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 33|
|
||||
|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 33|
|
||||
|5 | \valid.cstr |blk_mem_gen_generic_cstr | 33|
|
||||
|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1|
|
||||
|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1|
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:50 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 227 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:00:48 . Memory (MB): peak = 1214.625 ; gain = 452.770
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:51 . Memory (MB): peak = 1214.625 ; gain = 470.793
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1214.625 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:57 . Memory (MB): peak = 1214.625 ; gain = 828.285
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1214.625 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP hop_rom, cache-ID = b80f8c4f2ecb1180
|
||||
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1214.625 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file hop_rom_utilization_synth.rpt -pb hop_rom_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Mar 17 22:23:06 2023...
|
||||
-1006
File diff suppressed because it is too large
Load Diff
-1222
File diff suppressed because it is too large
Load Diff
-22
@@ -1,22 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Fri Mar 17 22:23:06 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
|
||||
// Design : hop_rom
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module hop_rom(clka, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[7:0],douta[31:0]" */;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
output [31:0]douta;
|
||||
endmodule
|
||||
-32
@@ -1,32 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Fri Mar 17 22:23:06 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
|
||||
-- Design : hop_rom
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity hop_rom is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end hop_rom;
|
||||
|
||||
architecture stub of hop_rom is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[7:0],douta[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
-176
@@ -1,176 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Fri Mar 17 22:23:06 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file hop_rom_utilization_synth.rpt -pb hop_rom_utilization_synth.pb
|
||||
| Design : hop_rom
|
||||
| Device : 7z100ffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 0 | 0 | 277400 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 277400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 108200 | 0.00 |
|
||||
| Slice Registers | 32 | 0 | 554800 | <0.01 |
|
||||
| Register as Flip Flop | 32 | 0 | 554800 | <0.01 |
|
||||
| Register as Latch | 0 | 0 | 554800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 138700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 69350 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 32 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0.5 | 0 | 755 | 0.07 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB18 | 1 | 0 | 1510 | 0.07 |
|
||||
| RAMB18E1 only | 1 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 2020 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 362 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 348 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 362 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 362 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 32 | Flop & Latch |
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
-9
@@ -1,9 +0,0 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log hop_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl
|
||||
-40
@@ -1,40 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31387838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f3862:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c686f705f726f6d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6872635f36345f31325f303235:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f6374726c5f7369676e616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f74785f7278:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c7369675f636c6b5f67656e:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:39:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6466383235613631313535333430343961333865326262336238653431393135:506172656e742050412070726f6a656374204944:00
|
||||
eof:1302407817
|
||||
-36
@@ -1,36 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log hop_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
-10
@@ -1,10 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
-43
@@ -1,43 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log hop_rom.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source hop_rom.tcl
|
||||
BIN
Binary file not shown.
-5
@@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="13584" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
-270
@@ -1,270 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
-24
@@ -1,24 +0,0 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci
|
||||
# IP: The module: 'hrc_64_12_025' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/hrc_64_12_025/constraints/fir_compiler_v7_2.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hrc_64_12_025'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hrc_64_12_025'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci
|
||||
# IP: The module: 'hrc_64_12_025' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/hrc_64_12_025/constraints/fir_compiler_v7_2.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hrc_64_12_025'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'hrc_64_12_025'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
-64
@@ -1,64 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="hrc_64_12_025_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1679062920">
|
||||
<File Type="PA-TCL" Name="hrc_64_12_025.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="hrc_64_12_025_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="hrc_64_12_025_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="hrc_64_12_025.vds"/>
|
||||
<File Type="RDS-UTIL" Name="hrc_64_12_025_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="hrc_64_12_025_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="hrc_64_12_025.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="hrc_64_12_025_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="hrc_64_12_025_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025">
|
||||
<File Path="$PPRDIR/../hrc_64_12_025/hrc_64_12_025.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../hrc_64_12_025.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hrc_64_12_025"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025">
|
||||
<File Path="$PPRDIR/../hrc_64_12_025/hrc_64_12_025.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../hrc_64_12_025.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="hrc_64_12_025"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
BIN
Binary file not shown.
-156
@@ -1,156 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7z100ffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/datalink_814/ip/hrc_64_12_025/constraints/fir_compiler_v7_2.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1 -new_name hrc_64_12_025 -ip [get_ips hrc_64_12_025]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top hrc_64_12_025 -part xc7z100ffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix hrc_64_12_025_ hrc_64_12_025.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hrc_64_12_025_stub.v
|
||||
lappend ipCachedFiles hrc_64_12_025_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hrc_64_12_025_stub.vhdl
|
||||
lappend ipCachedFiles hrc_64_12_025_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hrc_64_12_025_sim_netlist.v
|
||||
lappend ipCachedFiles hrc_64_12_025_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ hrc_64_12_025_sim_netlist.vhdl
|
||||
lappend ipCachedFiles hrc_64_12_025_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp hrc_64_12_025.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips hrc_64_12_025]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all hrc_64_12_025_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef hrc_64_12_025.dcp
|
||||
create_report "hrc_64_12_025_synth_1_synth_report_utilization_0" "report_utilization -file hrc_64_12_025_utilization_synth.rpt -pb hrc_64_12_025_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v -of_objects [get_files D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_sim_netlist.v -of_objects [get_files D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci]
|
||||
|
||||
add_files D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025.dcp -of_objects [get_files D:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_sim_netlist.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_sim_netlist.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl D:/vivado-git/datalink_814/ip/ip_user_files/ip/hrc_64_12_025
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
-479
@@ -1,479 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Fri Mar 17 22:22:04 2023
|
||||
# Process ID: 28972
|
||||
# Current directory: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1
|
||||
# Command line: vivado.exe -log hrc_64_12_025.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source hrc_64_12_025.tcl
|
||||
# Log file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025.vds
|
||||
# Journal file: D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source hrc_64_12_025.tcl -notrace
|
||||
Command: synth_design -top hrc_64_12_025 -part xc7z100ffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 14268
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 920.227 ; gain = 177.418
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'hrc_64_12_025' [d:/vivado-git/datalink_814/ip/hrc_64_12_025/synth/hrc_64_12_025.vhd:70]
|
||||
Parameter C_XDEVICEFAMILY bound to: zynq - type: string
|
||||
Parameter C_ELABORATION_DIR bound to: ./ - type: string
|
||||
Parameter C_COMPONENT_NAME bound to: hrc_64_12_025 - type: string
|
||||
Parameter C_COEF_FILE bound to: hrc_64_12_025.mif - type: string
|
||||
Parameter C_COEF_FILE_LINES bound to: 448 - type: integer
|
||||
Parameter C_FILTER_TYPE bound to: 2 - type: integer
|
||||
Parameter C_INTERP_RATE bound to: 64 - type: integer
|
||||
Parameter C_DECIM_RATE bound to: 1 - type: integer
|
||||
Parameter C_ZERO_PACKING_FACTOR bound to: 1 - type: integer
|
||||
Parameter C_SYMMETRY bound to: 1 - type: integer
|
||||
Parameter C_NUM_FILTS bound to: 1 - type: integer
|
||||
Parameter C_NUM_TAPS bound to: 769 - type: integer
|
||||
Parameter C_NUM_CHANNELS bound to: 1 - type: integer
|
||||
Parameter C_CHANNEL_PATTERN bound to: fixed - type: string
|
||||
Parameter C_ROUND_MODE bound to: 0 - type: integer
|
||||
Parameter C_COEF_RELOAD bound to: 0 - type: integer
|
||||
Parameter C_NUM_RELOAD_SLOTS bound to: 1 - type: integer
|
||||
Parameter C_COL_MODE bound to: 1 - type: integer
|
||||
Parameter C_COL_PIPE_LEN bound to: 4 - type: integer
|
||||
Parameter C_COL_CONFIG bound to: 7 - type: string
|
||||
Parameter C_OPTIMIZATION bound to: 0 - type: integer
|
||||
Parameter C_DATA_PATH_WIDTHS bound to: 2 - type: string
|
||||
Parameter C_DATA_IP_PATH_WIDTHS bound to: 2 - type: string
|
||||
Parameter C_DATA_PX_PATH_WIDTHS bound to: 2 - type: string
|
||||
Parameter C_DATA_WIDTH bound to: 2 - type: integer
|
||||
Parameter C_COEF_PATH_WIDTHS bound to: 17 - type: string
|
||||
Parameter C_COEF_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_DATA_PATH_SRC bound to: 0 - type: string
|
||||
Parameter C_COEF_PATH_SRC bound to: 0 - type: string
|
||||
Parameter C_PX_PATH_SRC bound to: 0 - type: string
|
||||
Parameter C_DATA_PATH_SIGN bound to: 0 - type: string
|
||||
Parameter C_COEF_PATH_SIGN bound to: 0 - type: string
|
||||
Parameter C_ACCUM_PATH_WIDTHS bound to: 19 - type: string
|
||||
Parameter C_OUTPUT_WIDTH bound to: 18 - type: integer
|
||||
Parameter C_OUTPUT_PATH_WIDTHS bound to: 18 - type: string
|
||||
Parameter C_ACCUM_OP_PATH_WIDTHS bound to: 18 - type: string
|
||||
Parameter C_EXT_MULT_CNFG bound to: none - type: string
|
||||
Parameter C_DATA_PATH_PSAMP_SRC bound to: 0 - type: string
|
||||
Parameter C_OP_PATH_PSAMP_SRC bound to: 0 - type: string
|
||||
Parameter C_NUM_MADDS bound to: 7 - type: integer
|
||||
Parameter C_OPT_MADDS bound to: none - type: string
|
||||
Parameter C_OVERSAMPLING_RATE bound to: 1 - type: integer
|
||||
Parameter C_INPUT_RATE bound to: 64 - type: integer
|
||||
Parameter C_OUTPUT_RATE bound to: 1 - type: integer
|
||||
Parameter C_DATA_MEMTYPE bound to: 0 - type: integer
|
||||
Parameter C_COEF_MEMTYPE bound to: 2 - type: integer
|
||||
Parameter C_IPBUFF_MEMTYPE bound to: 0 - type: integer
|
||||
Parameter C_OPBUFF_MEMTYPE bound to: 2 - type: integer
|
||||
Parameter C_DATAPATH_MEMTYPE bound to: 0 - type: integer
|
||||
Parameter C_MEM_ARRANGEMENT bound to: 1 - type: integer
|
||||
Parameter C_DATA_MEM_PACKING bound to: 0 - type: integer
|
||||
Parameter C_COEF_MEM_PACKING bound to: 0 - type: integer
|
||||
Parameter C_FILTS_PACKED bound to: 0 - type: integer
|
||||
Parameter C_LATENCY bound to: 17 - type: integer
|
||||
Parameter C_HAS_ARESETn bound to: 0 - type: integer
|
||||
Parameter C_HAS_ACLKEN bound to: 0 - type: integer
|
||||
Parameter C_DATA_HAS_TLAST bound to: 0 - type: integer
|
||||
Parameter C_S_DATA_HAS_FIFO bound to: 0 - type: integer
|
||||
Parameter C_S_DATA_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_S_DATA_TDATA_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_S_DATA_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_M_DATA_HAS_TREADY bound to: 0 - type: integer
|
||||
Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer
|
||||
Parameter C_M_DATA_TDATA_WIDTH bound to: 24 - type: integer
|
||||
Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_CONFIG_CHANNEL bound to: 0 - type: integer
|
||||
Parameter C_CONFIG_SYNC_MODE bound to: 0 - type: integer
|
||||
Parameter C_CONFIG_PACKET_SIZE bound to: 0 - type: integer
|
||||
Parameter C_CONFIG_TDATA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_RELOAD_TDATA_WIDTH bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'fir_compiler_v7_2_12' declared at 'd:/vivado-git/datalink_814/ip/hrc_64_12_025/hdl/fir_compiler_v7_2_vh_rfs.vhd:61264' bound to instance 'U0' of component 'fir_compiler_v7_2_12' [d:/vivado-git/datalink_814/ip/hrc_64_12_025/synth/hrc_64_12_025.vhd:198]
|
||||
WARNING: [Synth 8-5858] RAM p_casc_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
|
||||
WARNING: [Synth 8-5858] RAM p_path_out_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
|
||||
INFO: [Synth 8-256] done synthesizing module 'hrc_64_12_025' (13#1) [d:/vivado-git/datalink_814/ip/hrc_64_12_025/synth/hrc_64_12_025.vhd:70]
|
||||
WARNING: [Synth 8-3331] design buff__parameterized1 has unconnected port READ_ADDR[0]
|
||||
WARNING: [Synth 8-3331] design buff__parameterized1 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design buff__parameterized0 has unconnected port READ_ADDR[0]
|
||||
WARNING: [Synth 8-3331] design buff__parameterized0 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized5 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design buff has unconnected port RE
|
||||
WARNING: [Synth 8-3331] design buff has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized1 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized10 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized10 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized9 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized9 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized8 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized7 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized7 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized17 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized17 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized17 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized17 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized17 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design delay__parameterized16 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized16 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized16 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized16 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized16 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADDSUB
|
||||
WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port PRE_ADD_BYPASS
|
||||
WARNING: [Synth 8-3331] design calc__parameterized0 has unconnected port CED
|
||||
WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized15 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port SCLR_ALT
|
||||
WARNING: [Synth 8-3331] design delay__parameterized14 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][57]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][56]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][55]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][54]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][53]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][52]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][51]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][50]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][49]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[fab][48]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][62]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][61]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][60]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][59]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][58]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][57]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][56]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][55]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][54]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][53]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][52]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][51]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][50]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][49]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port POUT[casc][48]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][57]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][56]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][55]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][54]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][53]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][52]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][51]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][50]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][49]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][48]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][47]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][46]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][45]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][44]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][43]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][42]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][41]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][40]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][39]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][38]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][37]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][36]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][35]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][34]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][33]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][32]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][31]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][30]
|
||||
WARNING: [Synth 8-3331] design add_accum has unconnected port PIN[fab][29]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/datalink_814/ip/hrc_64_12_025/hrc_64_12_025_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [d:/vivado-git/datalink_814/ip/hrc_64_12_025/constraints/fir_compiler_v7_2.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/datalink_814/ip/hrc_64_12_025/constraints/fir_compiler_v7_2.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1131.160 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1131.160 ; gain = 0.000
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z100ffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "rom". This will be implemented in logic
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 2020 (col length:140)
|
||||
BRAMs: 1510 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
||||
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.i_cntrl_src/gen_dly.gen_regs.delay_bus_reg[0][0]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_cntrl_sym.i_addsup/gen_dly.gen_regs.delay_bus_reg[0][0]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.i_cntrl_src/gen_dly.gen_regs.delay_bus_reg[1][0]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_cntrl_sym.i_addsup/gen_dly.gen_regs.delay_bus_reg[1][0]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_paths[0].g_mem_array[0].i_mem/g_individual.i_mem_a /\gen_dram.gen_rom.d_out_reg[1] )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[5]' (FD) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[9]' (FD) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[0]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[0]' (FD) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[1]' (FD) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[2]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.g_accum_cntrl.accum_opcode_reg[2] )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[17]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[18]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[18]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[19]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[20]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[20]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[21]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[21]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[22]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[22]' (FDRE) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[23]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\g_polyphase_interpolation.i_polyphase_interpolation/g_m_data_chan_no_fifo.m_axis_data_tlast_int_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.start_px_reg' (FD) to 'U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_parallel.base_en_reg'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1131.160 ; gain = 388.352
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:33 . Memory (MB): peak = 1141.285 ; gain = 398.477
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:33 . Memory (MB): peak = 1162.355 ; gain = 419.547
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:33 . Memory (MB): peak = 1163.562 ; gain = 420.754
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+----------+------+
|
||||
| |Cell |Count |
|
||||
+------+----------+------+
|
||||
|1 |CARRY4 | 2|
|
||||
|2 |DSP48E1 | 7|
|
||||
|3 |DSP48E1_1 | 1|
|
||||
|4 |LUT1 | 8|
|
||||
|5 |LUT2 | 9|
|
||||
|6 |LUT3 | 30|
|
||||
|7 |LUT4 | 24|
|
||||
|8 |LUT5 | 14|
|
||||
|9 |LUT6 | 87|
|
||||
|10 |RAM128X1D | 18|
|
||||
|11 |SRL16E | 18|
|
||||
|12 |FDRE | 311|
|
||||
|13 |FDSE | 6|
|
||||
+------+----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 153 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:32 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 1170.309 ; gain = 427.500
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 28 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1192.508 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 18 instances were transformed.
|
||||
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 18 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
47 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:41 . Memory (MB): peak = 1192.508 ; gain = 805.605
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1192.508 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP hrc_64_12_025, cache-ID = b62778e9f879369b
|
||||
INFO: [Coretcl 2-1174] Renamed 70 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1192.508 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file hrc_64_12_025_utilization_synth.rpt -pb hrc_64_12_025_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Mar 17 22:22:51 2023...
|
||||
-5518
File diff suppressed because it is too large
Load Diff
-7480
File diff suppressed because it is too large
Load Diff
-26
@@ -1,26 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Fri Mar 17 22:22:50 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v
|
||||
// Design : hrc_64_12_025
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module hrc_64_12_025(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [7:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [23:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
-35
@@ -1,35 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Fri Mar 17 22:22:50 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/datalink_814/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl
|
||||
-- Design : hrc_64_12_025
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity hrc_64_12_025 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
|
||||
);
|
||||
|
||||
end hrc_64_12_025;
|
||||
|
||||
architecture stub of hrc_64_12_025 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
-189
@@ -1,189 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Fri Mar 17 22:22:50 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file hrc_64_12_025_utilization_synth.rpt -pb hrc_64_12_025_utilization_synth.pb
|
||||
| Design : hrc_64_12_025
|
||||
| Device : 7z100ffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 232 | 0 | 277400 | 0.08 |
|
||||
| LUT as Logic | 142 | 0 | 277400 | 0.05 |
|
||||
| LUT as Memory | 90 | 0 | 108200 | 0.08 |
|
||||
| LUT as Distributed RAM | 72 | 0 | | |
|
||||
| LUT as Shift Register | 18 | 0 | | |
|
||||
| Slice Registers | 317 | 0 | 554800 | 0.06 |
|
||||
| Register as Flip Flop | 317 | 0 | 554800 | 0.06 |
|
||||
| Register as Latch | 0 | 0 | 554800 | 0.00 |
|
||||
| F7 Muxes | 36 | 0 | 138700 | 0.03 |
|
||||
| F8 Muxes | 0 | 0 | 69350 | 0.00 |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 6 | Yes | Set | - |
|
||||
| 311 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 1510 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| DSPs | 8 | 0 | 2020 | 0.40 |
|
||||
| DSP48E1 only | 8 | | | |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 362 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 348 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 362 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 362 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 311 | Flop & Latch |
|
||||
| LUT6 | 87 | LUT |
|
||||
| RAMD64E | 72 | Distributed Memory |
|
||||
| MUXF7 | 36 | MuxFx |
|
||||
| LUT3 | 30 | LUT |
|
||||
| LUT4 | 24 | LUT |
|
||||
| SRL16E | 18 | Distributed Memory |
|
||||
| LUT5 | 14 | LUT |
|
||||
| LUT2 | 9 | LUT |
|
||||
| LUT1 | 8 | LUT |
|
||||
| DSP48E1 | 8 | Block Arithmetic |
|
||||
| FDSE | 6 | Flop & Latch |
|
||||
| CARRY4 | 2 | CarryLogic |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
-9
@@ -1,9 +0,0 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log hrc_64_12_025.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source hrc_64_12_025.tcl
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user