Archived
Update gitignore, add dl814_z7 project
gitignore structure is updated to work with single and multi project situation under a single project directory
This commit is contained in:
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//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
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//Date : Sat Feb 25 17:00:07 2023
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//Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
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//Command : generate_target system_bd_wrapper.bd
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//Design : system_bd_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module system_bd_wrapper
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(DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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c2c_rst_n,
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c2c_rx_clk,
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c2c_tx_clk,
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glink_gpio_i_0,
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glink_gpio_i_1,
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glink_gpio_o_0,
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glink_gpio_o_1,
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glink_ip_clk,
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glink_ip_rst_n,
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m_axis_fifo_c2c_out_tdata,
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m_axis_fifo_c2c_out_tlast,
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m_axis_fifo_c2c_out_tready,
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m_axis_fifo_c2c_out_tvalid,
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m_axis_fifo_glink_out_tdata,
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m_axis_fifo_glink_out_tlast,
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m_axis_fifo_glink_out_tready,
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m_axis_fifo_glink_out_tvalid,
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ps_clk,
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pwdown_gpio_o,
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s_axis_fifo_c2c_in_tdata,
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s_axis_fifo_c2c_in_tlast,
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s_axis_fifo_c2c_in_tready,
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s_axis_fifo_c2c_in_tvalid,
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s_axis_fifo_glink_in_tdata,
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s_axis_fifo_glink_in_tlast,
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s_axis_fifo_glink_in_tready,
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s_axis_fifo_glink_in_tvalid);
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inout [14:0]DDR_addr;
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inout [2:0]DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [3:0]DDR_dm;
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inout [31:0]DDR_dq;
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inout [3:0]DDR_dqs_n;
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inout [3:0]DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0]FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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input c2c_rst_n;
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input c2c_rx_clk;
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input c2c_tx_clk;
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input [31:0]glink_gpio_i_0;
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input [31:0]glink_gpio_i_1;
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output [31:0]glink_gpio_o_0;
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output [31:0]glink_gpio_o_1;
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input glink_ip_clk;
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input glink_ip_rst_n;
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output [31:0]m_axis_fifo_c2c_out_tdata;
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output m_axis_fifo_c2c_out_tlast;
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input m_axis_fifo_c2c_out_tready;
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output m_axis_fifo_c2c_out_tvalid;
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output [15:0]m_axis_fifo_glink_out_tdata;
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output m_axis_fifo_glink_out_tlast;
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input m_axis_fifo_glink_out_tready;
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output m_axis_fifo_glink_out_tvalid;
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output ps_clk;
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output [0:0]pwdown_gpio_o;
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input [31:0]s_axis_fifo_c2c_in_tdata;
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input s_axis_fifo_c2c_in_tlast;
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output s_axis_fifo_c2c_in_tready;
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input s_axis_fifo_c2c_in_tvalid;
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input [15:0]s_axis_fifo_glink_in_tdata;
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input s_axis_fifo_glink_in_tlast;
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output s_axis_fifo_glink_in_tready;
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input s_axis_fifo_glink_in_tvalid;
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wire [14:0]DDR_addr;
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wire [2:0]DDR_ba;
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wire DDR_cas_n;
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wire DDR_ck_n;
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wire DDR_ck_p;
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wire DDR_cke;
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wire DDR_cs_n;
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wire [3:0]DDR_dm;
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wire [31:0]DDR_dq;
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wire [3:0]DDR_dqs_n;
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wire [3:0]DDR_dqs_p;
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wire DDR_odt;
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wire DDR_ras_n;
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wire DDR_reset_n;
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wire DDR_we_n;
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wire FIXED_IO_ddr_vrn;
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wire FIXED_IO_ddr_vrp;
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wire [53:0]FIXED_IO_mio;
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wire FIXED_IO_ps_clk;
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wire FIXED_IO_ps_porb;
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wire FIXED_IO_ps_srstb;
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wire c2c_rst_n;
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wire c2c_rx_clk;
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wire c2c_tx_clk;
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wire [31:0]glink_gpio_i_0;
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wire [31:0]glink_gpio_i_1;
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wire [31:0]glink_gpio_o_0;
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wire [31:0]glink_gpio_o_1;
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wire glink_ip_clk;
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wire glink_ip_rst_n;
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wire [31:0]m_axis_fifo_c2c_out_tdata;
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wire m_axis_fifo_c2c_out_tlast;
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wire m_axis_fifo_c2c_out_tready;
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wire m_axis_fifo_c2c_out_tvalid;
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wire [15:0]m_axis_fifo_glink_out_tdata;
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wire m_axis_fifo_glink_out_tlast;
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wire m_axis_fifo_glink_out_tready;
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wire m_axis_fifo_glink_out_tvalid;
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wire ps_clk;
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wire [0:0]pwdown_gpio_o;
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wire [31:0]s_axis_fifo_c2c_in_tdata;
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wire s_axis_fifo_c2c_in_tlast;
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wire s_axis_fifo_c2c_in_tready;
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wire s_axis_fifo_c2c_in_tvalid;
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wire [15:0]s_axis_fifo_glink_in_tdata;
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wire s_axis_fifo_glink_in_tlast;
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wire s_axis_fifo_glink_in_tready;
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wire s_axis_fifo_glink_in_tvalid;
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system_bd system_bd_i
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(.DDR_addr(DDR_addr),
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.DDR_ba(DDR_ba),
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.DDR_cas_n(DDR_cas_n),
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.DDR_ck_n(DDR_ck_n),
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.DDR_ck_p(DDR_ck_p),
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.DDR_cke(DDR_cke),
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.DDR_cs_n(DDR_cs_n),
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.DDR_dm(DDR_dm),
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.DDR_dq(DDR_dq),
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.DDR_dqs_n(DDR_dqs_n),
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.DDR_dqs_p(DDR_dqs_p),
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.DDR_odt(DDR_odt),
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.DDR_ras_n(DDR_ras_n),
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.DDR_reset_n(DDR_reset_n),
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.DDR_we_n(DDR_we_n),
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.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
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.FIXED_IO_mio(FIXED_IO_mio),
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.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
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.c2c_rst_n(c2c_rst_n),
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.c2c_rx_clk(c2c_rx_clk),
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.c2c_tx_clk(c2c_tx_clk),
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.glink_gpio_i_0(glink_gpio_i_0),
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.glink_gpio_i_1(glink_gpio_i_1),
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.glink_gpio_o_0(glink_gpio_o_0),
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.glink_gpio_o_1(glink_gpio_o_1),
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.glink_ip_clk(glink_ip_clk),
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.glink_ip_rst_n(glink_ip_rst_n),
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.m_axis_fifo_c2c_out_tdata(m_axis_fifo_c2c_out_tdata),
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.m_axis_fifo_c2c_out_tlast(m_axis_fifo_c2c_out_tlast),
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.m_axis_fifo_c2c_out_tready(m_axis_fifo_c2c_out_tready),
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.m_axis_fifo_c2c_out_tvalid(m_axis_fifo_c2c_out_tvalid),
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.m_axis_fifo_glink_out_tdata(m_axis_fifo_glink_out_tdata),
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.m_axis_fifo_glink_out_tlast(m_axis_fifo_glink_out_tlast),
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.m_axis_fifo_glink_out_tready(m_axis_fifo_glink_out_tready),
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.m_axis_fifo_glink_out_tvalid(m_axis_fifo_glink_out_tvalid),
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.ps_clk(ps_clk),
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.pwdown_gpio_o(pwdown_gpio_o),
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.s_axis_fifo_c2c_in_tdata(s_axis_fifo_c2c_in_tdata),
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.s_axis_fifo_c2c_in_tlast(s_axis_fifo_c2c_in_tlast),
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.s_axis_fifo_c2c_in_tready(s_axis_fifo_c2c_in_tready),
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.s_axis_fifo_c2c_in_tvalid(s_axis_fifo_c2c_in_tvalid),
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.s_axis_fifo_glink_in_tdata(s_axis_fifo_glink_in_tdata),
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.s_axis_fifo_glink_in_tlast(s_axis_fifo_glink_in_tlast),
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.s_axis_fifo_glink_in_tready(s_axis_fifo_glink_in_tready),
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.s_axis_fifo_glink_in_tvalid(s_axis_fifo_glink_in_tvalid));
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endmodule
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,664 @@
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################################################################
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# This is a generated script based on design: system_bd
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source system_bd_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z045ffg900-2
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name system_bd
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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||||
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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||||
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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||||
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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return $nRet
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}
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||||
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||||
##################################################################
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# DESIGN PROCs
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||||
##################################################################
|
||||
|
||||
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# Hierarchical cell: glink_dma
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proc create_hier_cell_glink_dma { parentCell nameHier } {
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||||
variable script_folder
|
||||
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if { $parentCell eq "" || $nameHier eq "" } {
|
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catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_glink_dma() - Empty argument(s)!"}
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return
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}
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||||
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||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
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return
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}
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||||
|
||||
# Make sure parentObj is hier blk
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||||
set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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||||
return
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}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
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||||
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||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
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||||
|
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# Create cell and set as current instance
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||||
set hier_obj [create_bd_cell -type hier $nameHier]
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||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI
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||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE
|
||||
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_fifo_out
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_fifo_in
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir I -type rst axi_resetn
|
||||
create_bd_pin -dir I -type clk glink_ip_clk
|
||||
create_bd_pin -dir I -type rst glink_ip_rst_n
|
||||
create_bd_pin -dir I -type clk m_axi_mm2s_aclk
|
||||
create_bd_pin -dir O -type intr mm2s_introut
|
||||
create_bd_pin -dir O -type intr s2mm_introut
|
||||
|
||||
# Create instance: axi_dma_glink, and set properties
|
||||
set axi_dma_glink [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_glink ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.c_include_mm2s_dre {1} \
|
||||
CONFIG.c_include_s2mm_dre {1} \
|
||||
CONFIG.c_include_sg {0} \
|
||||
CONFIG.c_m_axis_mm2s_tdata_width {16} \
|
||||
CONFIG.c_mm2s_burst_size {64} \
|
||||
CONFIG.c_s2mm_burst_size {64} \
|
||||
CONFIG.c_sg_include_stscntrl_strm {0} \
|
||||
] $axi_dma_glink
|
||||
|
||||
# Create instance: axi_smc, and set properties
|
||||
set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_SI {2} \
|
||||
] $axi_smc
|
||||
|
||||
# Create instance: axis_data_fifo_in, and set properties
|
||||
set axis_data_fifo_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_in ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
CONFIG.IS_ACLK_ASYNC {1} \
|
||||
CONFIG.TDATA_NUM_BYTES {2} \
|
||||
] $axis_data_fifo_in
|
||||
|
||||
# Create instance: axis_data_fifo_out, and set properties
|
||||
set axis_data_fifo_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_out ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
CONFIG.IS_ACLK_ASYNC {1} \
|
||||
CONFIG.TDATA_NUM_BYTES {2} \
|
||||
] $axis_data_fifo_out
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S_AXIS_0_1 [get_bd_intf_pins s_axis_fifo_in] [get_bd_intf_pins axis_data_fifo_in/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axi_dma_glink_M_AXIS_MM2S [get_bd_intf_pins axi_dma_glink/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_out/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axi_dma_glink_M_AXI_MM2S [get_bd_intf_pins axi_dma_glink/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_dma_glink_M_AXI_S2MM [get_bd_intf_pins axi_dma_glink/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI]
|
||||
connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins M00_AXI] [get_bd_intf_pins axi_smc/M00_AXI]
|
||||
connect_bd_intf_net -intf_net axis_data_fifo_in_M_AXIS [get_bd_intf_pins axi_dma_glink/S_AXIS_S2MM] [get_bd_intf_pins axis_data_fifo_in/M_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_data_fifo_out_M_AXIS [get_bd_intf_pins m_axis_fifo_out] [get_bd_intf_pins axis_data_fifo_out/M_AXIS]
|
||||
connect_bd_intf_net -intf_net ps7_axi_periph_M01_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_dma_glink/S_AXI_LITE]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_dma_glink_mm2s_introut [get_bd_pins mm2s_introut] [get_bd_pins axi_dma_glink/mm2s_introut]
|
||||
connect_bd_net -net axi_dma_glink_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins axi_dma_glink/s2mm_introut]
|
||||
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins m_axi_mm2s_aclk] [get_bd_pins axi_dma_glink/m_axi_mm2s_aclk] [get_bd_pins axi_dma_glink/m_axi_s2mm_aclk] [get_bd_pins axi_dma_glink/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_data_fifo_in/m_axis_aclk] [get_bd_pins axis_data_fifo_out/s_axis_aclk]
|
||||
connect_bd_net -net rst_ps7_100M_peripheral_aresetn [get_bd_pins axi_resetn] [get_bd_pins axi_dma_glink/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_data_fifo_out/s_axis_aresetn]
|
||||
connect_bd_net -net s_axis_aclk_0_1 [get_bd_pins glink_ip_clk] [get_bd_pins axis_data_fifo_in/s_axis_aclk] [get_bd_pins axis_data_fifo_out/m_axis_aclk]
|
||||
connect_bd_net -net s_axis_aresetn_0_1 [get_bd_pins glink_ip_rst_n] [get_bd_pins axis_data_fifo_in/s_axis_aresetn]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
# Hierarchical cell: c2c_dma
|
||||
proc create_hier_cell_c2c_dma { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_c2c_dma() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI
|
||||
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_0
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_0
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir I -type rst axi_resetn
|
||||
create_bd_pin -dir I -type clk m_axis_aclk
|
||||
create_bd_pin -dir I -type clk m_axis_aclk_0
|
||||
create_bd_pin -dir O -type intr mm2s_introut
|
||||
create_bd_pin -dir O -type intr s2mm_introut
|
||||
create_bd_pin -dir I -type clk s_axis_aclk_0
|
||||
create_bd_pin -dir I -type rst s_axis_aresetn_0
|
||||
|
||||
# Create instance: axi_dma_c2c, and set properties
|
||||
set axi_dma_c2c [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_c2c ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.c_include_mm2s_dre {1} \
|
||||
CONFIG.c_include_s2mm_dre {1} \
|
||||
CONFIG.c_include_sg {0} \
|
||||
CONFIG.c_mm2s_burst_size {64} \
|
||||
CONFIG.c_s2mm_burst_size {64} \
|
||||
CONFIG.c_sg_include_stscntrl_strm {0} \
|
||||
] $axi_dma_c2c
|
||||
|
||||
# Create instance: axi_smc, and set properties
|
||||
set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
|
||||
|
||||
# Create instance: axis_data_fifo_c2c_in, and set properties
|
||||
set axis_data_fifo_c2c_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_c2c_in ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FIFO_DEPTH {1024} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
CONFIG.IS_ACLK_ASYNC {1} \
|
||||
CONFIG.TDATA_NUM_BYTES {4} \
|
||||
] $axis_data_fifo_c2c_in
|
||||
|
||||
# Create instance: axis_data_fifo_c2c_out, and set properties
|
||||
set axis_data_fifo_c2c_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_c2c_out ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FIFO_DEPTH {1024} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
CONFIG.IS_ACLK_ASYNC {1} \
|
||||
CONFIG.TDATA_NUM_BYTES {4} \
|
||||
] $axis_data_fifo_c2c_out
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S_AXIS_0] [get_bd_intf_pins axis_data_fifo_c2c_in/S_AXIS]
|
||||
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_dma_c2c/S_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins M00_AXI] [get_bd_intf_pins axi_smc/M00_AXI]
|
||||
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins M_AXIS_0] [get_bd_intf_pins axis_data_fifo_c2c_out/M_AXIS]
|
||||
connect_bd_intf_net -intf_net axi_dma_c2c_M_AXIS_MM2S [get_bd_intf_pins axi_dma_c2c/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_c2c_out/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axi_dma_c2c_M_AXI_MM2S [get_bd_intf_pins axi_dma_c2c/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_dma_c2c_M_AXI_S2MM [get_bd_intf_pins axi_dma_c2c/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI]
|
||||
connect_bd_intf_net -intf_net axis_data_fifo_c2c_in_M_AXIS [get_bd_intf_pins axi_dma_c2c/S_AXIS_S2MM] [get_bd_intf_pins axis_data_fifo_c2c_in/M_AXIS]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_dma_c2c_mm2s_introut [get_bd_pins mm2s_introut] [get_bd_pins axi_dma_c2c/mm2s_introut]
|
||||
connect_bd_net -net axi_dma_c2c_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins axi_dma_c2c/s2mm_introut]
|
||||
connect_bd_net -net axi_resetn_1 [get_bd_pins axi_resetn] [get_bd_pins axi_dma_c2c/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axis_data_fifo_c2c_out/s_axis_aresetn]
|
||||
connect_bd_net -net m_axis_aclk_0_1 [get_bd_pins m_axis_aclk_0] [get_bd_pins axis_data_fifo_c2c_out/m_axis_aclk]
|
||||
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins axi_dma_c2c/m_axi_mm2s_aclk] [get_bd_pins axi_dma_c2c/m_axi_s2mm_aclk] [get_bd_pins axi_dma_c2c/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axis_data_fifo_c2c_in/m_axis_aclk] [get_bd_pins axis_data_fifo_c2c_out/s_axis_aclk]
|
||||
connect_bd_net -net s_axis_aclk_0_1 [get_bd_pins s_axis_aclk_0] [get_bd_pins axis_data_fifo_c2c_in/s_axis_aclk]
|
||||
connect_bd_net -net s_axis_aresetn_0_1 [get_bd_pins s_axis_aresetn_0] [get_bd_pins axis_data_fifo_c2c_in/s_axis_aresetn]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
|
||||
|
||||
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
|
||||
|
||||
set m_axis_fifo_c2c_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_fifo_c2c_out ]
|
||||
|
||||
set m_axis_fifo_glink_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_fifo_glink_out ]
|
||||
|
||||
set s_axis_fifo_c2c_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_fifo_c2c_in ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {1} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
CONFIG.LAYERED_METADATA {undef} \
|
||||
CONFIG.TDATA_NUM_BYTES {4} \
|
||||
CONFIG.TDEST_WIDTH {0} \
|
||||
CONFIG.TID_WIDTH {0} \
|
||||
CONFIG.TUSER_WIDTH {0} \
|
||||
] $s_axis_fifo_c2c_in
|
||||
|
||||
set s_axis_fifo_glink_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_fifo_glink_in ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {1} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
CONFIG.LAYERED_METADATA {undef} \
|
||||
CONFIG.TDATA_NUM_BYTES {2} \
|
||||
CONFIG.TDEST_WIDTH {0} \
|
||||
CONFIG.TID_WIDTH {0} \
|
||||
CONFIG.TUSER_WIDTH {0} \
|
||||
] $s_axis_fifo_glink_in
|
||||
|
||||
|
||||
# Create ports
|
||||
set c2c_rst_n [ create_bd_port -dir I -type rst c2c_rst_n ]
|
||||
set c2c_rx_clk [ create_bd_port -dir I -type clk c2c_rx_clk ]
|
||||
set c2c_tx_clk [ create_bd_port -dir I -type clk c2c_tx_clk ]
|
||||
set glink_gpio_i_0 [ create_bd_port -dir I -from 31 -to 0 glink_gpio_i_0 ]
|
||||
set glink_gpio_i_1 [ create_bd_port -dir I -from 31 -to 0 glink_gpio_i_1 ]
|
||||
set glink_gpio_o_0 [ create_bd_port -dir O -from 31 -to 0 glink_gpio_o_0 ]
|
||||
set glink_gpio_o_1 [ create_bd_port -dir O -from 31 -to 0 glink_gpio_o_1 ]
|
||||
set glink_ip_clk [ create_bd_port -dir I -type clk glink_ip_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {s_axis_fifo_glink_in:m_axis_fifo_glink_out} \
|
||||
] $glink_ip_clk
|
||||
set glink_ip_rst_n [ create_bd_port -dir I -type rst glink_ip_rst_n ]
|
||||
set ps_clk [ create_bd_port -dir O -type clk ps_clk ]
|
||||
set pwdown_gpio_o [ create_bd_port -dir O -from 0 -to 0 pwdown_gpio_o ]
|
||||
|
||||
# Create instance: c2c_dma
|
||||
create_hier_cell_c2c_dma [current_bd_instance .] c2c_dma
|
||||
|
||||
# Create instance: glink_ctrl, and set properties
|
||||
set glink_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 glink_ctrl ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_IS_DUAL {1} \
|
||||
] $glink_ctrl
|
||||
|
||||
# Create instance: glink_dma
|
||||
create_hier_cell_glink_dma [current_bd_instance .] glink_dma
|
||||
|
||||
# Create instance: processing_system7, and set properties
|
||||
set processing_system7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
|
||||
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
|
||||
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
|
||||
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_CLK0_FREQ {100000000} \
|
||||
CONFIG.PCW_CLK1_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK2_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK3_FREQ {10000000} \
|
||||
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
|
||||
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
|
||||
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
|
||||
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
|
||||
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_EN_QSPI {1} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {3} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
|
||||
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
|
||||
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
|
||||
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
|
||||
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
|
||||
CONFIG.PCW_IOPLL_CTRL_FBDIV {54} \
|
||||
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1800.000} \
|
||||
CONFIG.PCW_IRQ_F2P_INTR {1} \
|
||||
CONFIG.PCW_MIO_1_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_1_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_1_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_2_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_3_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_4_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_5_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_6_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \
|
||||
CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \
|
||||
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
||||
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \
|
||||
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {9} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
|
||||
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
|
||||
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
||||
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
|
||||
CONFIG.PCW_USE_S_AXI_HP0 {1} \
|
||||
CONFIG.PCW_USE_S_AXI_HP1 {1} \
|
||||
] $processing_system7
|
||||
|
||||
# Create instance: ps7_axi_periph, and set properties
|
||||
set ps7_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_axi_periph ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_MI {4} \
|
||||
] $ps7_axi_periph
|
||||
|
||||
# Create instance: pwdown_ctrl, and set properties
|
||||
set pwdown_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 pwdown_ctrl ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_ALL_OUTPUTS {1} \
|
||||
CONFIG.C_GPIO_WIDTH {1} \
|
||||
] $pwdown_ctrl
|
||||
|
||||
# Create instance: rst_ps7_100M, and set properties
|
||||
set rst_ps7_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_100M ]
|
||||
|
||||
# Create instance: xlconcat_intr, and set properties
|
||||
set xlconcat_intr [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_intr ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_PORTS {4} \
|
||||
] $xlconcat_intr
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S_AXIS_0_1 [get_bd_intf_ports s_axis_fifo_glink_in] [get_bd_intf_pins glink_dma/s_axis_fifo_in]
|
||||
connect_bd_intf_net -intf_net S_AXIS_0_2 [get_bd_intf_ports s_axis_fifo_c2c_in] [get_bd_intf_pins c2c_dma/S_AXIS_0]
|
||||
connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins glink_dma/M00_AXI] [get_bd_intf_pins processing_system7/S_AXI_HP0]
|
||||
connect_bd_intf_net -intf_net axis_data_fifo_out_M_AXIS [get_bd_intf_ports m_axis_fifo_glink_out] [get_bd_intf_pins glink_dma/m_axis_fifo_out]
|
||||
connect_bd_intf_net -intf_net c2c_dma_M00_AXI [get_bd_intf_pins c2c_dma/M00_AXI] [get_bd_intf_pins processing_system7/S_AXI_HP1]
|
||||
connect_bd_intf_net -intf_net c2c_dma_M_AXIS_0 [get_bd_intf_ports m_axis_fifo_c2c_out] [get_bd_intf_pins c2c_dma/M_AXIS_0]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7/DDR]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7/FIXED_IO]
|
||||
connect_bd_intf_net -intf_net processing_system7_M_AXI_GP0 [get_bd_intf_pins processing_system7/M_AXI_GP0] [get_bd_intf_pins ps7_axi_periph/S00_AXI]
|
||||
connect_bd_intf_net -intf_net ps7_axi_periph_M00_AXI [get_bd_intf_pins glink_ctrl/S_AXI] [get_bd_intf_pins ps7_axi_periph/M00_AXI]
|
||||
connect_bd_intf_net -intf_net ps7_axi_periph_M01_AXI [get_bd_intf_pins glink_dma/S_AXI_LITE] [get_bd_intf_pins ps7_axi_periph/M01_AXI]
|
||||
connect_bd_intf_net -intf_net ps7_axi_periph_M02_AXI [get_bd_intf_pins c2c_dma/S_AXI_LITE] [get_bd_intf_pins ps7_axi_periph/M02_AXI]
|
||||
connect_bd_intf_net -intf_net ps7_axi_periph_M03_AXI [get_bd_intf_pins ps7_axi_periph/M03_AXI] [get_bd_intf_pins pwdown_ctrl/S_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_dma_glink_mm2s_introut [get_bd_pins glink_dma/mm2s_introut] [get_bd_pins xlconcat_intr/In0]
|
||||
connect_bd_net -net axi_dma_glink_s2mm_introut [get_bd_pins glink_dma/s2mm_introut] [get_bd_pins xlconcat_intr/In1]
|
||||
connect_bd_net -net c2c_dma_mm2s_introut [get_bd_pins c2c_dma/mm2s_introut] [get_bd_pins xlconcat_intr/In2]
|
||||
connect_bd_net -net c2c_dma_s2mm_introut [get_bd_pins c2c_dma/s2mm_introut] [get_bd_pins xlconcat_intr/In3]
|
||||
connect_bd_net -net glink_ctrl_gpio2_io_o [get_bd_ports glink_gpio_o_1] [get_bd_pins glink_ctrl/gpio2_io_o]
|
||||
connect_bd_net -net glink_ctrl_gpio_io_o [get_bd_ports glink_gpio_o_0] [get_bd_pins glink_ctrl/gpio_io_o]
|
||||
connect_bd_net -net gpio2_io_i_0_1 [get_bd_ports glink_gpio_i_1] [get_bd_pins glink_ctrl/gpio2_io_i]
|
||||
connect_bd_net -net gpio_io_i_0_1 [get_bd_ports glink_gpio_i_0] [get_bd_pins glink_ctrl/gpio_io_i]
|
||||
connect_bd_net -net irq_xlconcat_dout [get_bd_pins processing_system7/IRQ_F2P] [get_bd_pins xlconcat_intr/dout]
|
||||
connect_bd_net -net m_axis_aclk_0_1 [get_bd_ports c2c_tx_clk] [get_bd_pins c2c_dma/m_axis_aclk_0]
|
||||
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports ps_clk] [get_bd_pins c2c_dma/m_axis_aclk] [get_bd_pins glink_ctrl/s_axi_aclk] [get_bd_pins glink_dma/m_axi_mm2s_aclk] [get_bd_pins processing_system7/FCLK_CLK0] [get_bd_pins processing_system7/M_AXI_GP0_ACLK] [get_bd_pins processing_system7/S_AXI_HP0_ACLK] [get_bd_pins processing_system7/S_AXI_HP1_ACLK] [get_bd_pins ps7_axi_periph/ACLK] [get_bd_pins ps7_axi_periph/M00_ACLK] [get_bd_pins ps7_axi_periph/M01_ACLK] [get_bd_pins ps7_axi_periph/M02_ACLK] [get_bd_pins ps7_axi_periph/M03_ACLK] [get_bd_pins ps7_axi_periph/S00_ACLK] [get_bd_pins pwdown_ctrl/s_axi_aclk] [get_bd_pins rst_ps7_100M/slowest_sync_clk]
|
||||
connect_bd_net -net processing_system7_FCLK_RESET0_N [get_bd_pins processing_system7/FCLK_RESET0_N] [get_bd_pins rst_ps7_100M/ext_reset_in]
|
||||
connect_bd_net -net pwdown_ctrl_gpio_io_o [get_bd_ports pwdown_gpio_o] [get_bd_pins pwdown_ctrl/gpio_io_o]
|
||||
connect_bd_net -net rst_ps7_100M_peripheral_aresetn [get_bd_pins c2c_dma/axi_resetn] [get_bd_pins glink_ctrl/s_axi_aresetn] [get_bd_pins glink_dma/axi_resetn] [get_bd_pins ps7_axi_periph/ARESETN] [get_bd_pins ps7_axi_periph/M00_ARESETN] [get_bd_pins ps7_axi_periph/M01_ARESETN] [get_bd_pins ps7_axi_periph/M02_ARESETN] [get_bd_pins ps7_axi_periph/M03_ARESETN] [get_bd_pins ps7_axi_periph/S00_ARESETN] [get_bd_pins pwdown_ctrl/s_axi_aresetn] [get_bd_pins rst_ps7_100M/peripheral_aresetn]
|
||||
connect_bd_net -net s_axis_aclk_0_1 [get_bd_ports glink_ip_clk] [get_bd_pins glink_dma/glink_ip_clk]
|
||||
connect_bd_net -net s_axis_aclk_0_2 [get_bd_ports c2c_rx_clk] [get_bd_pins c2c_dma/s_axis_aclk_0]
|
||||
connect_bd_net -net s_axis_aresetn_0_1 [get_bd_ports glink_ip_rst_n] [get_bd_pins glink_dma/glink_ip_rst_n]
|
||||
connect_bd_net -net s_axis_aresetn_0_2 [get_bd_ports c2c_rst_n] [get_bd_pins c2c_dma/s_axis_aresetn_0]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40410000 [get_bd_addr_spaces processing_system7/Data] [get_bd_addr_segs c2c_dma/axi_dma_c2c/S_AXI_LITE/Reg] SEG_axi_dma_c2c_Reg
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces processing_system7/Data] [get_bd_addr_segs glink_dma/axi_dma_glink/S_AXI_LITE/Reg] SEG_axi_dma_glink_Reg
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7/Data] [get_bd_addr_segs glink_ctrl/S_AXI/Reg] SEG_glink_ctrl_Reg
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7/Data] [get_bd_addr_segs pwdown_ctrl/S_AXI/Reg] SEG_pwdown_ctrl_Reg
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces c2c_dma/axi_dma_c2c/Data_MM2S] [get_bd_addr_segs processing_system7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_HP1_DDR_LOWOCM
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces c2c_dma/axi_dma_c2c/Data_S2MM] [get_bd_addr_segs processing_system7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_HP1_DDR_LOWOCM
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces glink_dma/axi_dma_glink/Data_MM2S] [get_bd_addr_segs processing_system7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_HP0_DDR_LOWOCM
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces glink_dma/axi_dma_glink/Data_S2MM] [get_bd_addr_segs processing_system7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_HP0_DDR_LOWOCM
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
+354
@@ -0,0 +1,354 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 19
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, \
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4\
|
||||
, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_19_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+356
@@ -0,0 +1,356 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 19
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_bd_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=19,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSE\
|
||||
R_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, \
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4\
|
||||
, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_19_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+213
@@ -0,0 +1,213 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_auto_pc_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_protocol_converter" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_READ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_USER_SIGNALS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_WRITE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IGNORE_ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_PROTOCOL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_PROTOCOL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRANSLATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_auto_pc_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_PROTOCOL">AXI3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRANSLATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+4325
File diff suppressed because it is too large
Load Diff
+50
@@ -0,0 +1,50 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
create_clock -period 100.0 -name aclk [get_ports aclk]
|
||||
|
||||
+12764
File diff suppressed because it is too large
Load Diff
+14973
File diff suppressed because it is too large
Load Diff
+87
@@ -0,0 +1,87 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
// Date : Sat Feb 25 17:02:06 2023
|
||||
// Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// e:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_05/datalink814_z045_smart_c2c_05.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0_stub.v
|
||||
// Design : system_bd_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z045ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1" *)
|
||||
module system_bd_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+88
@@ -0,0 +1,88 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
-- Date : Sat Feb 25 17:02:06 2023
|
||||
-- Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- e:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_05/datalink814_z045_smart_c2c_05.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0_stub.vhdl
|
||||
-- Design : system_bd_auto_pc_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z045ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_auto_pc_0 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_awvalid : out STD_LOGIC;
|
||||
m_axi_awready : in STD_LOGIC;
|
||||
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_wvalid : out STD_LOGIC;
|
||||
m_axi_wready : in STD_LOGIC;
|
||||
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_bvalid : in STD_LOGIC;
|
||||
m_axi_bready : out STD_LOGIC;
|
||||
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_arvalid : out STD_LOGIC;
|
||||
m_axi_arready : in STD_LOGIC;
|
||||
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_rvalid : in STD_LOGIC;
|
||||
m_axi_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_auto_pc_0;
|
||||
|
||||
architecture stub of system_bd_auto_pc_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1";
|
||||
begin
|
||||
end;
|
||||
+486
@@ -0,0 +1,486 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 20
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_20;
|
||||
USE axi_dma_v7_1_20.axi_dma;
|
||||
|
||||
ENTITY system_bd_axi_dma_0_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_dma_0_0;
|
||||
|
||||
ARCHITECTURE system_bd_axi_dma_0_0_arch OF system_bd_axi_dma_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_introut: SIGNAL IS "XIL_INTERFACENAME MM2S_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_mm2s_tdata: SIGNAL IS "XIL_INTERFACENAME M_AXIS_MM2S, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0, HAS_BURST 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME MM2S_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_araddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE" &
|
||||
"ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S_CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL, ASSOCIATED_RESET mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 0,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 14,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 32,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 1,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 64,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 32,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 16,
|
||||
C_INCLUDE_MM2S_DRE => 1,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 64,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 32,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 16,
|
||||
C_INCLUDE_S2MM_DRE => 1,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
|
||||
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
|
||||
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
|
||||
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
|
||||
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
|
||||
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
|
||||
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
|
||||
m_axi_mm2s_arready => m_axi_mm2s_arready,
|
||||
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
|
||||
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
|
||||
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
|
||||
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
|
||||
m_axi_mm2s_rready => m_axi_mm2s_rready,
|
||||
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
|
||||
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
|
||||
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
|
||||
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
|
||||
m_axis_mm2s_tready => m_axis_mm2s_tready,
|
||||
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
mm2s_introut => mm2s_introut,
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_bd_axi_dma_0_0_arch;
|
||||
+493
@@ -0,0 +1,493 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 20
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_20;
|
||||
USE axi_dma_v7_1_20.axi_dma;
|
||||
|
||||
ENTITY system_bd_axi_dma_0_0 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_dma_0_0;
|
||||
|
||||
ARCHITECTURE system_bd_axi_dma_0_0_arch OF system_bd_axi_dma_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2019.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_axi_dma_0_0_arch : ARCHITECTURE IS "system_bd_axi_dma_0_0,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_axi_dma_0_0_arch: ARCHITECTURE IS "system_bd_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=20,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32" &
|
||||
",C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=64,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=16,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=64,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=16,C_INCLUDE_S2MM_DRE=1,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_introut: SIGNAL IS "XIL_INTERFACENAME MM2S_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_mm2s_tdata: SIGNAL IS "XIL_INTERFACENAME M_AXIS_MM2S, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0, HAS_BURST 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME MM2S_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_araddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE" &
|
||||
"ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S_CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL, ASSOCIATED_RESET mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 0,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 14,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 32,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 1,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 64,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 32,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 16,
|
||||
C_INCLUDE_MM2S_DRE => 1,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 64,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 32,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 16,
|
||||
C_INCLUDE_S2MM_DRE => 1,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
|
||||
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
|
||||
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
|
||||
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
|
||||
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
|
||||
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
|
||||
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
|
||||
m_axi_mm2s_arready => m_axi_mm2s_arready,
|
||||
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
|
||||
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
|
||||
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
|
||||
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
|
||||
m_axi_mm2s_rready => m_axi_mm2s_rready,
|
||||
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
|
||||
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
|
||||
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
|
||||
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
|
||||
m_axis_mm2s_tready => m_axis_mm2s_tready,
|
||||
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
mm2s_introut => mm2s_introut,
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_bd_axi_dma_0_0_arch;
|
||||
BIN
Binary file not shown.
+484
@@ -0,0 +1,484 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_dma_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_dma" spirit:version="7.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MM2S_CNTRL_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MM2S_INTROUT.PortWidth">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MM2S_PRMRY_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
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|
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|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.FREQ_HZ">100000000</spirit:configurableElementValue>
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.MAX_BURST_LENGTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.MAX_BURST_LENGTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.READ_WRITE_MODE">WRITE_ONLY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_SG_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2MM_INTROUT.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2MM_PRMRY_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S2MM_STS_RESET_OUT_N.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDATA_NUM_BYTES">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TKEEP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TLAST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DLYTMR_RESOLUTION">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_MULTI_CHANNEL">0</spirit:configurableElementValue>
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ARUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.AWUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_CACHE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_RRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_WSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PROTOCOL" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2MM_INTROUT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TKEEP" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TLAST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TREADY" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.LAYERED_METADATA" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDEST_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TUSER_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TKEEP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TLAST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TREADY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_mm2s_dre" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_s2mm_dre" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_sg" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axi_s2mm_data_width" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axis_mm2s_tdata_width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_mm2s_burst_size" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_prmry_is_aclk_async" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s2mm_burst_size" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s_axis_s2mm_tdata_width" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_include_stscntrl_strm" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
# file: system_bd_axi_dma_0_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
## INFO: Level CDC Crossing in AXI DMA
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
# Specific to MultiChannel mode
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. In multi channel mode, it is safe to ignore this." \
|
||||
-from [get_pins -hier -quiet -filter {NAME =~*MM2S_SPLIT.I_COMMAND_MM2S_SPLITTER/vsize_data_int_reg[*]/C}]
|
||||
|
||||
|
||||
+8860
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
# file: system_bd_axi_dma_0_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
+52887
File diff suppressed because it is too large
Load Diff
+62680
File diff suppressed because it is too large
Load Diff
+98
@@ -0,0 +1,98 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
// Date : Sat Feb 25 17:03:16 2023
|
||||
// Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_05/datalink814_z045_smart_c2c_05.srcs/sources_1/bd/system_bd/ip/system_bd_axi_dma_0_0/system_bd_axi_dma_0_0_stub.v
|
||||
// Design : system_bd_axi_dma_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z045ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_dma,Vivado 2019.1" *)
|
||||
module system_bd_axi_dma_0_0(s_axi_lite_aclk, m_axi_mm2s_aclk,
|
||||
m_axi_s2mm_aclk, axi_resetn, s_axi_lite_awvalid, s_axi_lite_awready, s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid, s_axi_lite_wready, s_axi_lite_wdata, s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid, s_axi_lite_bready, s_axi_lite_arvalid, s_axi_lite_arready,
|
||||
s_axi_lite_araddr, s_axi_lite_rvalid, s_axi_lite_rready, s_axi_lite_rdata,
|
||||
s_axi_lite_rresp, m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize,
|
||||
m_axi_mm2s_arburst, m_axi_mm2s_arprot, m_axi_mm2s_arcache, m_axi_mm2s_arvalid,
|
||||
m_axi_mm2s_arready, m_axi_mm2s_rdata, m_axi_mm2s_rresp, m_axi_mm2s_rlast,
|
||||
m_axi_mm2s_rvalid, m_axi_mm2s_rready, mm2s_prmry_reset_out_n, m_axis_mm2s_tdata,
|
||||
m_axis_mm2s_tkeep, m_axis_mm2s_tvalid, m_axis_mm2s_tready, m_axis_mm2s_tlast,
|
||||
m_axi_s2mm_awaddr, m_axi_s2mm_awlen, m_axi_s2mm_awsize, m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot, m_axi_s2mm_awcache, m_axi_s2mm_awvalid, m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata, m_axi_s2mm_wstrb, m_axi_s2mm_wlast, m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready, m_axi_s2mm_bresp, m_axi_s2mm_bvalid, m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n, s_axis_s2mm_tdata, s_axis_s2mm_tkeep, s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready, s_axis_s2mm_tlast, mm2s_introut, s2mm_introut, axi_dma_tstvec)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_lite_aclk,m_axi_mm2s_aclk,m_axi_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[15:0],m_axis_mm2s_tkeep[1:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[15:0],s_axis_s2mm_tkeep[1:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut,axi_dma_tstvec[31:0]" */;
|
||||
input s_axi_lite_aclk;
|
||||
input m_axi_mm2s_aclk;
|
||||
input m_axi_s2mm_aclk;
|
||||
input axi_resetn;
|
||||
input s_axi_lite_awvalid;
|
||||
output s_axi_lite_awready;
|
||||
input [9:0]s_axi_lite_awaddr;
|
||||
input s_axi_lite_wvalid;
|
||||
output s_axi_lite_wready;
|
||||
input [31:0]s_axi_lite_wdata;
|
||||
output [1:0]s_axi_lite_bresp;
|
||||
output s_axi_lite_bvalid;
|
||||
input s_axi_lite_bready;
|
||||
input s_axi_lite_arvalid;
|
||||
output s_axi_lite_arready;
|
||||
input [9:0]s_axi_lite_araddr;
|
||||
output s_axi_lite_rvalid;
|
||||
input s_axi_lite_rready;
|
||||
output [31:0]s_axi_lite_rdata;
|
||||
output [1:0]s_axi_lite_rresp;
|
||||
output [31:0]m_axi_mm2s_araddr;
|
||||
output [7:0]m_axi_mm2s_arlen;
|
||||
output [2:0]m_axi_mm2s_arsize;
|
||||
output [1:0]m_axi_mm2s_arburst;
|
||||
output [2:0]m_axi_mm2s_arprot;
|
||||
output [3:0]m_axi_mm2s_arcache;
|
||||
output m_axi_mm2s_arvalid;
|
||||
input m_axi_mm2s_arready;
|
||||
input [31:0]m_axi_mm2s_rdata;
|
||||
input [1:0]m_axi_mm2s_rresp;
|
||||
input m_axi_mm2s_rlast;
|
||||
input m_axi_mm2s_rvalid;
|
||||
output m_axi_mm2s_rready;
|
||||
output mm2s_prmry_reset_out_n;
|
||||
output [15:0]m_axis_mm2s_tdata;
|
||||
output [1:0]m_axis_mm2s_tkeep;
|
||||
output m_axis_mm2s_tvalid;
|
||||
input m_axis_mm2s_tready;
|
||||
output m_axis_mm2s_tlast;
|
||||
output [31:0]m_axi_s2mm_awaddr;
|
||||
output [7:0]m_axi_s2mm_awlen;
|
||||
output [2:0]m_axi_s2mm_awsize;
|
||||
output [1:0]m_axi_s2mm_awburst;
|
||||
output [2:0]m_axi_s2mm_awprot;
|
||||
output [3:0]m_axi_s2mm_awcache;
|
||||
output m_axi_s2mm_awvalid;
|
||||
input m_axi_s2mm_awready;
|
||||
output [31:0]m_axi_s2mm_wdata;
|
||||
output [3:0]m_axi_s2mm_wstrb;
|
||||
output m_axi_s2mm_wlast;
|
||||
output m_axi_s2mm_wvalid;
|
||||
input m_axi_s2mm_wready;
|
||||
input [1:0]m_axi_s2mm_bresp;
|
||||
input m_axi_s2mm_bvalid;
|
||||
output m_axi_s2mm_bready;
|
||||
output s2mm_prmry_reset_out_n;
|
||||
input [15:0]s_axis_s2mm_tdata;
|
||||
input [1:0]s_axis_s2mm_tkeep;
|
||||
input s_axis_s2mm_tvalid;
|
||||
output s_axis_s2mm_tready;
|
||||
input s_axis_s2mm_tlast;
|
||||
output mm2s_introut;
|
||||
output s2mm_introut;
|
||||
output [31:0]axi_dma_tstvec;
|
||||
endmodule
|
||||
+93
@@ -0,0 +1,93 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
-- Date : Sat Feb 25 17:03:16 2023
|
||||
-- Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_05/datalink814_z045_smart_c2c_05.srcs/sources_1/bd/system_bd/ip/system_bd_axi_dma_0_0/system_bd_axi_dma_0_0_stub.vhdl
|
||||
-- Design : system_bd_axi_dma_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z045ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_dma_0_0 is
|
||||
Port (
|
||||
s_axi_lite_aclk : in STD_LOGIC;
|
||||
m_axi_mm2s_aclk : in STD_LOGIC;
|
||||
m_axi_s2mm_aclk : in STD_LOGIC;
|
||||
axi_resetn : in STD_LOGIC;
|
||||
s_axi_lite_awvalid : in STD_LOGIC;
|
||||
s_axi_lite_awready : out STD_LOGIC;
|
||||
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_wvalid : in STD_LOGIC;
|
||||
s_axi_lite_wready : out STD_LOGIC;
|
||||
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_lite_bvalid : out STD_LOGIC;
|
||||
s_axi_lite_bready : in STD_LOGIC;
|
||||
s_axi_lite_arvalid : in STD_LOGIC;
|
||||
s_axi_lite_arready : out STD_LOGIC;
|
||||
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_rvalid : out STD_LOGIC;
|
||||
s_axi_lite_rready : in STD_LOGIC;
|
||||
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_mm2s_arvalid : out STD_LOGIC;
|
||||
m_axi_mm2s_arready : in STD_LOGIC;
|
||||
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_rlast : in STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : in STD_LOGIC;
|
||||
m_axi_mm2s_rready : out STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : out STD_LOGIC;
|
||||
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axis_mm2s_tvalid : out STD_LOGIC;
|
||||
m_axis_mm2s_tready : in STD_LOGIC;
|
||||
m_axis_mm2s_tlast : out STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_s2mm_awvalid : out STD_LOGIC;
|
||||
m_axi_s2mm_awready : in STD_LOGIC;
|
||||
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_s2mm_wlast : out STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : out STD_LOGIC;
|
||||
m_axi_s2mm_wready : in STD_LOGIC;
|
||||
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_s2mm_bvalid : in STD_LOGIC;
|
||||
m_axi_s2mm_bready : out STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : out STD_LOGIC;
|
||||
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axis_s2mm_tvalid : in STD_LOGIC;
|
||||
s_axis_s2mm_tready : out STD_LOGIC;
|
||||
s_axis_s2mm_tlast : in STD_LOGIC;
|
||||
mm2s_introut : out STD_LOGIC;
|
||||
s2mm_introut : out STD_LOGIC;
|
||||
axi_dma_tstvec : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_dma_0_0;
|
||||
|
||||
architecture stub of system_bd_axi_dma_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_mm2s_aclk,m_axi_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[15:0],m_axis_mm2s_tkeep[1:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[15:0],s_axis_s2mm_tkeep[1:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut,axi_dma_tstvec[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_dma,Vivado 2019.1";
|
||||
begin
|
||||
end;
|
||||
+486
@@ -0,0 +1,486 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 20
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_20;
|
||||
USE axi_dma_v7_1_20.axi_dma;
|
||||
|
||||
ENTITY system_bd_axi_dma_0_1 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_dma_0_1;
|
||||
|
||||
ARCHITECTURE system_bd_axi_dma_0_1_arch OF system_bd_axi_dma_0_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_dma_0_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_introut: SIGNAL IS "XIL_INTERFACENAME MM2S_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_mm2s_tdata: SIGNAL IS "XIL_INTERFACENAME M_AXIS_MM2S, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0, HAS_BURST 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME MM2S_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_araddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE" &
|
||||
"ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S_CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL, ASSOCIATED_RESET mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 0,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 14,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 32,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 1,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 64,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 32,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 1,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 64,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 32,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_S2MM_DRE => 1,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
|
||||
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
|
||||
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
|
||||
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
|
||||
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
|
||||
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
|
||||
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
|
||||
m_axi_mm2s_arready => m_axi_mm2s_arready,
|
||||
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
|
||||
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
|
||||
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
|
||||
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
|
||||
m_axi_mm2s_rready => m_axi_mm2s_rready,
|
||||
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
|
||||
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
|
||||
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
|
||||
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
|
||||
m_axis_mm2s_tready => m_axis_mm2s_tready,
|
||||
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
mm2s_introut => mm2s_introut,
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_bd_axi_dma_0_1_arch;
|
||||
+493
@@ -0,0 +1,493 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
|
||||
-- IP Revision: 20
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_dma_v7_1_20;
|
||||
USE axi_dma_v7_1_20.axi_dma;
|
||||
|
||||
ENTITY system_bd_axi_dma_0_1 IS
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_dma_0_1;
|
||||
|
||||
ARCHITECTURE system_bd_axi_dma_0_1_arch OF system_bd_axi_dma_0_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_dma_0_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_dma IS
|
||||
GENERIC (
|
||||
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
|
||||
C_DLYTMR_RESOLUTION : INTEGER;
|
||||
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
|
||||
C_ENABLE_MULTI_CHANNEL : INTEGER;
|
||||
C_NUM_MM2S_CHANNELS : INTEGER;
|
||||
C_NUM_S2MM_CHANNELS : INTEGER;
|
||||
C_INCLUDE_SG : INTEGER;
|
||||
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
|
||||
C_SG_USE_STSAPP_LENGTH : INTEGER;
|
||||
C_SG_LENGTH_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_SG_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
|
||||
C_MICRO_DMA : INTEGER;
|
||||
C_INCLUDE_MM2S : INTEGER;
|
||||
C_INCLUDE_MM2S_SF : INTEGER;
|
||||
C_MM2S_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_MM2S_DRE : INTEGER;
|
||||
C_INCLUDE_S2MM : INTEGER;
|
||||
C_INCLUDE_S2MM_SF : INTEGER;
|
||||
C_S2MM_BURST_SIZE : INTEGER;
|
||||
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
|
||||
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
|
||||
C_INCLUDE_S2MM_DRE : INTEGER;
|
||||
C_INCREASE_THROUGHPUT : INTEGER;
|
||||
C_FAMILY : STRING
|
||||
);
|
||||
PORT (
|
||||
s_axi_lite_aclk : IN STD_LOGIC;
|
||||
m_axi_sg_aclk : IN STD_LOGIC;
|
||||
m_axi_mm2s_aclk : IN STD_LOGIC;
|
||||
m_axi_s2mm_aclk : IN STD_LOGIC;
|
||||
axi_resetn : IN STD_LOGIC;
|
||||
s_axi_lite_awvalid : IN STD_LOGIC;
|
||||
s_axi_lite_awready : OUT STD_LOGIC;
|
||||
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_wvalid : IN STD_LOGIC;
|
||||
s_axi_lite_wready : OUT STD_LOGIC;
|
||||
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_lite_bvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_bready : IN STD_LOGIC;
|
||||
s_axi_lite_arvalid : IN STD_LOGIC;
|
||||
s_axi_lite_arready : OUT STD_LOGIC;
|
||||
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
s_axi_lite_rvalid : OUT STD_LOGIC;
|
||||
s_axi_lite_rready : IN STD_LOGIC;
|
||||
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_awvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_awready : IN STD_LOGIC;
|
||||
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_wlast : OUT STD_LOGIC;
|
||||
m_axi_sg_wvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_wready : IN STD_LOGIC;
|
||||
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_bvalid : IN STD_LOGIC;
|
||||
m_axi_sg_bready : OUT STD_LOGIC;
|
||||
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_sg_arvalid : OUT STD_LOGIC;
|
||||
m_axi_sg_arready : IN STD_LOGIC;
|
||||
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_sg_rlast : IN STD_LOGIC;
|
||||
m_axi_sg_rvalid : IN STD_LOGIC;
|
||||
m_axi_sg_rready : OUT STD_LOGIC;
|
||||
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_mm2s_arvalid : OUT STD_LOGIC;
|
||||
m_axi_mm2s_arready : IN STD_LOGIC;
|
||||
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_mm2s_rlast : IN STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : IN STD_LOGIC;
|
||||
m_axi_mm2s_rready : OUT STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_tlast : OUT STD_LOGIC;
|
||||
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
|
||||
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_awvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_awready : IN STD_LOGIC;
|
||||
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
m_axi_s2mm_wlast : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : OUT STD_LOGIC;
|
||||
m_axi_s2mm_wready : IN STD_LOGIC;
|
||||
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
m_axi_s2mm_bvalid : IN STD_LOGIC;
|
||||
m_axi_s2mm_bready : OUT STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_tlast : IN STD_LOGIC;
|
||||
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
s2mm_sts_reset_out_n : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
|
||||
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
|
||||
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
|
||||
mm2s_introut : OUT STD_LOGIC;
|
||||
s2mm_introut : OUT STD_LOGIC;
|
||||
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_axi_dma_0_1_arch: ARCHITECTURE IS "axi_dma,Vivado 2019.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_axi_dma_0_1_arch : ARCHITECTURE IS "system_bd_axi_dma_0_1,axi_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_axi_dma_0_1_arch: ARCHITECTURE IS "system_bd_axi_dma_0_1,axi_dma,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=20,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32" &
|
||||
",C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=64,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=64,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=1,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynq}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_introut: SIGNAL IS "XIL_INTERFACENAME MM2S_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_s2mm_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_S2MM, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME S2MM_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_mm2s_tdata: SIGNAL IS "XIL_INTERFACENAME M_AXIS_MM2S, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0, HAS_BURST 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mm2s_prmry_reset_out_n: SIGNAL IS "XIL_INTERFACENAME MM2S_PRMRY_RESET_OUT_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_araddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awvalid: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 10, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THRE" &
|
||||
"ADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axi_resetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM_CLK, ASSOCIATED_BUSIF M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS, ASSOCIATED_RESET s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_mm2s_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_MM2S_CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL, ASSOCIATED_RESET mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE:M_AXI, ASSOCIATED_RESET axi_resetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_dma
|
||||
GENERIC MAP (
|
||||
C_S_AXI_LITE_ADDR_WIDTH => 10,
|
||||
C_S_AXI_LITE_DATA_WIDTH => 32,
|
||||
C_DLYTMR_RESOLUTION => 125,
|
||||
C_PRMRY_IS_ACLK_ASYNC => 0,
|
||||
C_ENABLE_MULTI_CHANNEL => 0,
|
||||
C_NUM_MM2S_CHANNELS => 1,
|
||||
C_NUM_S2MM_CHANNELS => 1,
|
||||
C_INCLUDE_SG => 0,
|
||||
C_SG_INCLUDE_STSCNTRL_STRM => 0,
|
||||
C_SG_USE_STSAPP_LENGTH => 0,
|
||||
C_SG_LENGTH_WIDTH => 14,
|
||||
C_M_AXI_SG_ADDR_WIDTH => 32,
|
||||
C_M_AXI_SG_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
|
||||
C_MICRO_DMA => 0,
|
||||
C_INCLUDE_MM2S => 1,
|
||||
C_INCLUDE_MM2S_SF => 1,
|
||||
C_MM2S_BURST_SIZE => 64,
|
||||
C_M_AXI_MM2S_ADDR_WIDTH => 32,
|
||||
C_M_AXI_MM2S_DATA_WIDTH => 32,
|
||||
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_MM2S_DRE => 1,
|
||||
C_INCLUDE_S2MM => 1,
|
||||
C_INCLUDE_S2MM_SF => 1,
|
||||
C_S2MM_BURST_SIZE => 64,
|
||||
C_M_AXI_S2MM_ADDR_WIDTH => 32,
|
||||
C_M_AXI_S2MM_DATA_WIDTH => 32,
|
||||
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
|
||||
C_INCLUDE_S2MM_DRE => 1,
|
||||
C_INCREASE_THROUGHPUT => 0,
|
||||
C_FAMILY => "zynq"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_lite_aclk => s_axi_lite_aclk,
|
||||
m_axi_sg_aclk => '0',
|
||||
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
|
||||
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
|
||||
axi_resetn => axi_resetn,
|
||||
s_axi_lite_awvalid => s_axi_lite_awvalid,
|
||||
s_axi_lite_awready => s_axi_lite_awready,
|
||||
s_axi_lite_awaddr => s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid => s_axi_lite_wvalid,
|
||||
s_axi_lite_wready => s_axi_lite_wready,
|
||||
s_axi_lite_wdata => s_axi_lite_wdata,
|
||||
s_axi_lite_bresp => s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid => s_axi_lite_bvalid,
|
||||
s_axi_lite_bready => s_axi_lite_bready,
|
||||
s_axi_lite_arvalid => s_axi_lite_arvalid,
|
||||
s_axi_lite_arready => s_axi_lite_arready,
|
||||
s_axi_lite_araddr => s_axi_lite_araddr,
|
||||
s_axi_lite_rvalid => s_axi_lite_rvalid,
|
||||
s_axi_lite_rready => s_axi_lite_rready,
|
||||
s_axi_lite_rdata => s_axi_lite_rdata,
|
||||
s_axi_lite_rresp => s_axi_lite_rresp,
|
||||
m_axi_sg_awready => '0',
|
||||
m_axi_sg_wready => '0',
|
||||
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_bvalid => '0',
|
||||
m_axi_sg_arready => '0',
|
||||
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
m_axi_sg_rlast => '0',
|
||||
m_axi_sg_rvalid => '0',
|
||||
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
|
||||
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
|
||||
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
|
||||
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
|
||||
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
|
||||
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
|
||||
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
|
||||
m_axi_mm2s_arready => m_axi_mm2s_arready,
|
||||
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
|
||||
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
|
||||
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
|
||||
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
|
||||
m_axi_mm2s_rready => m_axi_mm2s_rready,
|
||||
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
|
||||
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
|
||||
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
|
||||
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
|
||||
m_axis_mm2s_tready => m_axis_mm2s_tready,
|
||||
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
|
||||
m_axis_mm2s_cntrl_tready => '0',
|
||||
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
|
||||
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
|
||||
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
|
||||
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
|
||||
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
|
||||
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
|
||||
m_axi_s2mm_awready => m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
|
||||
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
|
||||
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
|
||||
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready => m_axi_s2mm_wready,
|
||||
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
|
||||
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
|
||||
m_axi_s2mm_bready => m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
|
||||
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
|
||||
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
|
||||
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready => s_axis_s2mm_tready,
|
||||
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
|
||||
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
|
||||
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axis_s2mm_sts_tkeep => X"F",
|
||||
s_axis_s2mm_sts_tvalid => '0',
|
||||
s_axis_s2mm_sts_tlast => '0',
|
||||
mm2s_introut => mm2s_introut,
|
||||
s2mm_introut => s2mm_introut,
|
||||
axi_dma_tstvec => axi_dma_tstvec
|
||||
);
|
||||
END system_bd_axi_dma_0_1_arch;
|
||||
BIN
Binary file not shown.
+483
@@ -0,0 +1,483 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
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||||
<spirit:vendor>xilinx.com</spirit:vendor>
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||||
<spirit:library>xci</spirit:library>
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||||
<spirit:name>unknown</spirit:name>
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<spirit:version>1.0</spirit:version>
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||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
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<spirit:instanceName>system_bd_axi_dma_0_1</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_dma" spirit:version="7.1"/>
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<spirit:configurableElementValues>
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|
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|
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CNTRL.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_BURST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TKEEP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TREADY" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TDEST_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_MM2S.TUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ARUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_CACHE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_RRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.MAX_BURST_LENGTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_OUTSTANDING" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.PROTOCOL" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_MM2S_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.AWUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_CACHE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.HAS_WSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.MAX_BURST_LENGTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_OUTSTANDING" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.PROTOCOL" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_S2MM_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ARUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.AWUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_CACHE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_RRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.HAS_WSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.PROTOCOL" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_SG.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S2MM_INTROUT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TKEEP" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TLAST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TREADY" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.LAYERED_METADATA" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDEST_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TUSER_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TKEEP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TLAST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TREADY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_mm2s_dre" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_s2mm_dre" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_sg" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axi_s2mm_data_width" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_mm2s_burst_size" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_prmry_is_aclk_async" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s2mm_burst_size" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s_axis_s2mm_tdata_width" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_include_stscntrl_strm" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
# file: system_bd_axi_dma_0_1.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
## INFO: Level CDC Crossing in AXI DMA
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. The Address and Data value does not change until AXI transaction is complete." \
|
||||
-to [get_pins -hier -quiet -filter {NAME =~*I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[*].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to/D}]
|
||||
|
||||
# Specific to MultiChannel mode
|
||||
create_waiver -internal -scope -type CDC -id {CDC-1} -user "axi_dma" -tags "9601"\
|
||||
-desc "The CDC-1 warning is waived as it is safe in the context of AXI DMA. In multi channel mode, it is safe to ignore this." \
|
||||
-from [get_pins -hier -quiet -filter {NAME =~*MM2S_SPLIT.I_COMMAND_MM2S_SPLITTER/vsize_data_int_reg[*]/C}]
|
||||
|
||||
|
||||
+8848
File diff suppressed because it is too large
Load Diff
+46
@@ -0,0 +1,46 @@
|
||||
# file: system_bd_axi_dma_0_1.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
+54839
File diff suppressed because it is too large
Load Diff
+65341
File diff suppressed because it is too large
Load Diff
+98
@@ -0,0 +1,98 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
// Date : Sat Feb 25 17:03:17 2023
|
||||
// Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_05/datalink814_z045_smart_c2c_05.srcs/sources_1/bd/system_bd/ip/system_bd_axi_dma_0_1/system_bd_axi_dma_0_1_stub.v
|
||||
// Design : system_bd_axi_dma_0_1
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z045ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_dma,Vivado 2019.1" *)
|
||||
module system_bd_axi_dma_0_1(s_axi_lite_aclk, m_axi_mm2s_aclk,
|
||||
m_axi_s2mm_aclk, axi_resetn, s_axi_lite_awvalid, s_axi_lite_awready, s_axi_lite_awaddr,
|
||||
s_axi_lite_wvalid, s_axi_lite_wready, s_axi_lite_wdata, s_axi_lite_bresp,
|
||||
s_axi_lite_bvalid, s_axi_lite_bready, s_axi_lite_arvalid, s_axi_lite_arready,
|
||||
s_axi_lite_araddr, s_axi_lite_rvalid, s_axi_lite_rready, s_axi_lite_rdata,
|
||||
s_axi_lite_rresp, m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize,
|
||||
m_axi_mm2s_arburst, m_axi_mm2s_arprot, m_axi_mm2s_arcache, m_axi_mm2s_arvalid,
|
||||
m_axi_mm2s_arready, m_axi_mm2s_rdata, m_axi_mm2s_rresp, m_axi_mm2s_rlast,
|
||||
m_axi_mm2s_rvalid, m_axi_mm2s_rready, mm2s_prmry_reset_out_n, m_axis_mm2s_tdata,
|
||||
m_axis_mm2s_tkeep, m_axis_mm2s_tvalid, m_axis_mm2s_tready, m_axis_mm2s_tlast,
|
||||
m_axi_s2mm_awaddr, m_axi_s2mm_awlen, m_axi_s2mm_awsize, m_axi_s2mm_awburst,
|
||||
m_axi_s2mm_awprot, m_axi_s2mm_awcache, m_axi_s2mm_awvalid, m_axi_s2mm_awready,
|
||||
m_axi_s2mm_wdata, m_axi_s2mm_wstrb, m_axi_s2mm_wlast, m_axi_s2mm_wvalid,
|
||||
m_axi_s2mm_wready, m_axi_s2mm_bresp, m_axi_s2mm_bvalid, m_axi_s2mm_bready,
|
||||
s2mm_prmry_reset_out_n, s_axis_s2mm_tdata, s_axis_s2mm_tkeep, s_axis_s2mm_tvalid,
|
||||
s_axis_s2mm_tready, s_axis_s2mm_tlast, mm2s_introut, s2mm_introut, axi_dma_tstvec)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_lite_aclk,m_axi_mm2s_aclk,m_axi_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut,axi_dma_tstvec[31:0]" */;
|
||||
input s_axi_lite_aclk;
|
||||
input m_axi_mm2s_aclk;
|
||||
input m_axi_s2mm_aclk;
|
||||
input axi_resetn;
|
||||
input s_axi_lite_awvalid;
|
||||
output s_axi_lite_awready;
|
||||
input [9:0]s_axi_lite_awaddr;
|
||||
input s_axi_lite_wvalid;
|
||||
output s_axi_lite_wready;
|
||||
input [31:0]s_axi_lite_wdata;
|
||||
output [1:0]s_axi_lite_bresp;
|
||||
output s_axi_lite_bvalid;
|
||||
input s_axi_lite_bready;
|
||||
input s_axi_lite_arvalid;
|
||||
output s_axi_lite_arready;
|
||||
input [9:0]s_axi_lite_araddr;
|
||||
output s_axi_lite_rvalid;
|
||||
input s_axi_lite_rready;
|
||||
output [31:0]s_axi_lite_rdata;
|
||||
output [1:0]s_axi_lite_rresp;
|
||||
output [31:0]m_axi_mm2s_araddr;
|
||||
output [7:0]m_axi_mm2s_arlen;
|
||||
output [2:0]m_axi_mm2s_arsize;
|
||||
output [1:0]m_axi_mm2s_arburst;
|
||||
output [2:0]m_axi_mm2s_arprot;
|
||||
output [3:0]m_axi_mm2s_arcache;
|
||||
output m_axi_mm2s_arvalid;
|
||||
input m_axi_mm2s_arready;
|
||||
input [31:0]m_axi_mm2s_rdata;
|
||||
input [1:0]m_axi_mm2s_rresp;
|
||||
input m_axi_mm2s_rlast;
|
||||
input m_axi_mm2s_rvalid;
|
||||
output m_axi_mm2s_rready;
|
||||
output mm2s_prmry_reset_out_n;
|
||||
output [31:0]m_axis_mm2s_tdata;
|
||||
output [3:0]m_axis_mm2s_tkeep;
|
||||
output m_axis_mm2s_tvalid;
|
||||
input m_axis_mm2s_tready;
|
||||
output m_axis_mm2s_tlast;
|
||||
output [31:0]m_axi_s2mm_awaddr;
|
||||
output [7:0]m_axi_s2mm_awlen;
|
||||
output [2:0]m_axi_s2mm_awsize;
|
||||
output [1:0]m_axi_s2mm_awburst;
|
||||
output [2:0]m_axi_s2mm_awprot;
|
||||
output [3:0]m_axi_s2mm_awcache;
|
||||
output m_axi_s2mm_awvalid;
|
||||
input m_axi_s2mm_awready;
|
||||
output [31:0]m_axi_s2mm_wdata;
|
||||
output [3:0]m_axi_s2mm_wstrb;
|
||||
output m_axi_s2mm_wlast;
|
||||
output m_axi_s2mm_wvalid;
|
||||
input m_axi_s2mm_wready;
|
||||
input [1:0]m_axi_s2mm_bresp;
|
||||
input m_axi_s2mm_bvalid;
|
||||
output m_axi_s2mm_bready;
|
||||
output s2mm_prmry_reset_out_n;
|
||||
input [31:0]s_axis_s2mm_tdata;
|
||||
input [3:0]s_axis_s2mm_tkeep;
|
||||
input s_axis_s2mm_tvalid;
|
||||
output s_axis_s2mm_tready;
|
||||
input s_axis_s2mm_tlast;
|
||||
output mm2s_introut;
|
||||
output s2mm_introut;
|
||||
output [31:0]axi_dma_tstvec;
|
||||
endmodule
|
||||
+93
@@ -0,0 +1,93 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
-- Date : Sat Feb 25 17:03:17 2023
|
||||
-- Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_05/datalink814_z045_smart_c2c_05.srcs/sources_1/bd/system_bd/ip/system_bd_axi_dma_0_1/system_bd_axi_dma_0_1_stub.vhdl
|
||||
-- Design : system_bd_axi_dma_0_1
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z045ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_dma_0_1 is
|
||||
Port (
|
||||
s_axi_lite_aclk : in STD_LOGIC;
|
||||
m_axi_mm2s_aclk : in STD_LOGIC;
|
||||
m_axi_s2mm_aclk : in STD_LOGIC;
|
||||
axi_resetn : in STD_LOGIC;
|
||||
s_axi_lite_awvalid : in STD_LOGIC;
|
||||
s_axi_lite_awready : out STD_LOGIC;
|
||||
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_wvalid : in STD_LOGIC;
|
||||
s_axi_lite_wready : out STD_LOGIC;
|
||||
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_lite_bvalid : out STD_LOGIC;
|
||||
s_axi_lite_bready : in STD_LOGIC;
|
||||
s_axi_lite_arvalid : in STD_LOGIC;
|
||||
s_axi_lite_arready : out STD_LOGIC;
|
||||
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
s_axi_lite_rvalid : out STD_LOGIC;
|
||||
s_axi_lite_rready : in STD_LOGIC;
|
||||
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_mm2s_arvalid : out STD_LOGIC;
|
||||
m_axi_mm2s_arready : in STD_LOGIC;
|
||||
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mm2s_rlast : in STD_LOGIC;
|
||||
m_axi_mm2s_rvalid : in STD_LOGIC;
|
||||
m_axi_mm2s_rready : out STD_LOGIC;
|
||||
mm2s_prmry_reset_out_n : out STD_LOGIC;
|
||||
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axis_mm2s_tvalid : out STD_LOGIC;
|
||||
m_axis_mm2s_tready : in STD_LOGIC;
|
||||
m_axis_mm2s_tlast : out STD_LOGIC;
|
||||
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_s2mm_awvalid : out STD_LOGIC;
|
||||
m_axi_s2mm_awready : in STD_LOGIC;
|
||||
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_s2mm_wlast : out STD_LOGIC;
|
||||
m_axi_s2mm_wvalid : out STD_LOGIC;
|
||||
m_axi_s2mm_wready : in STD_LOGIC;
|
||||
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_s2mm_bvalid : in STD_LOGIC;
|
||||
m_axi_s2mm_bready : out STD_LOGIC;
|
||||
s2mm_prmry_reset_out_n : out STD_LOGIC;
|
||||
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axis_s2mm_tvalid : in STD_LOGIC;
|
||||
s_axis_s2mm_tready : out STD_LOGIC;
|
||||
s_axis_s2mm_tlast : in STD_LOGIC;
|
||||
mm2s_introut : out STD_LOGIC;
|
||||
s2mm_introut : out STD_LOGIC;
|
||||
axi_dma_tstvec : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_dma_0_1;
|
||||
|
||||
architecture stub of system_bd_axi_dma_0_1 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_mm2s_aclk,m_axi_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut,axi_dma_tstvec[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_dma,Vivado 2019.1";
|
||||
begin
|
||||
end;
|
||||
+218
@@ -0,0 +1,218 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 21
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_21;
|
||||
USE axi_gpio_v2_0_21.axi_gpio;
|
||||
|
||||
ENTITY system_bd_axi_gpio_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_gpio_0_0;
|
||||
|
||||
ARCHITECTURE system_bd_axi_gpio_0_0_arch OF system_bd_axi_gpio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 32,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 1,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => gpio2_io_i,
|
||||
gpio2_io_o => gpio2_io_o,
|
||||
gpio2_io_t => gpio2_io_t
|
||||
);
|
||||
END system_bd_axi_gpio_0_0_arch;
|
||||
+224
@@ -0,0 +1,224 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 21
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_21;
|
||||
USE axi_gpio_v2_0_21.axi_gpio;
|
||||
|
||||
ENTITY system_bd_axi_gpio_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_gpio_0_0;
|
||||
|
||||
ARCHITECTURE system_bd_axi_gpio_0_0_arch OF system_bd_axi_gpio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2019.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_axi_gpio_0_0_arch : ARCHITECTURE IS "system_bd_axi_gpio_0_0,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_axi_gpio_0_0_arch: ARCHITECTURE IS "system_bd_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=32,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 32,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 0,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 1,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => gpio_io_i,
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio_io_t => gpio_io_t,
|
||||
gpio2_io_i => gpio2_io_i,
|
||||
gpio2_io_o => gpio2_io_o,
|
||||
gpio2_io_t => gpio2_io_t
|
||||
);
|
||||
END system_bd_axi_gpio_0_0_arch;
|
||||
BIN
Binary file not shown.
+136
@@ -0,0 +1,136 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_gpio_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IP2INTC_IRQ.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_gpio_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">21</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IS_DUAL" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
||||
+2079
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+9770
File diff suppressed because it is too large
Load Diff
+11876
File diff suppressed because it is too large
Load Diff
+48
@@ -0,0 +1,48 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
// Date : Fri Feb 24 19:11:41 2023
|
||||
// Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_01/datalink814_gch_z045_smart_pwrst_001.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0_stub.v
|
||||
// Design : system_bd_axi_gpio_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z045ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2019.1" *)
|
||||
module system_bd_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t,
|
||||
gpio2_io_i, gpio2_io_o, gpio2_io_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[31:0],gpio_io_o[31:0],gpio_io_t[31:0],gpio2_io_i[31:0],gpio2_io_o[31:0],gpio2_io_t[31:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input [31:0]gpio_io_i;
|
||||
output [31:0]gpio_io_o;
|
||||
output [31:0]gpio_io_t;
|
||||
input [31:0]gpio2_io_i;
|
||||
output [31:0]gpio2_io_o;
|
||||
output [31:0]gpio2_io_t;
|
||||
endmodule
|
||||
+54
@@ -0,0 +1,54 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
-- Date : Fri Feb 24 19:11:41 2023
|
||||
-- Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_01/datalink814_gch_z045_smart_pwrst_001.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0_stub.vhdl
|
||||
-- Design : system_bd_axi_gpio_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z045ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_gpio_0_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_gpio_0_0;
|
||||
|
||||
architecture stub of system_bd_axi_gpio_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[31:0],gpio_io_o[31:0],gpio_io_t[31:0],gpio2_io_i[31:0],gpio2_io_o[31:0],gpio2_io_t[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2019.1";
|
||||
begin
|
||||
end;
|
||||
+204
@@ -0,0 +1,204 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 21
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_21;
|
||||
USE axi_gpio_v2_0_21.axi_gpio;
|
||||
|
||||
ENTITY system_bd_axi_gpio_0_2 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_gpio_0_2;
|
||||
|
||||
ARCHITECTURE system_bd_axi_gpio_0_2_arch OF system_bd_axi_gpio_0_2 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_2_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_bd_axi_gpio_0_2_arch;
|
||||
+210
@@ -0,0 +1,210 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 21
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_21;
|
||||
USE axi_gpio_v2_0_21.axi_gpio;
|
||||
|
||||
ENTITY system_bd_axi_gpio_0_2 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_bd_axi_gpio_0_2;
|
||||
|
||||
ARCHITECTURE system_bd_axi_gpio_0_2_arch OF system_bd_axi_gpio_0_2 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_2_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_axi_gpio_0_2_arch: ARCHITECTURE IS "axi_gpio,Vivado 2019.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_axi_gpio_0_2_arch : ARCHITECTURE IS "system_bd_axi_gpio_0_2,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_axi_gpio_0_2_arch: ARCHITECTURE IS "system_bd_axi_gpio_0_2,axi_gpio,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD" &
|
||||
"S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 1,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_bd_axi_gpio_0_2_arch;
|
||||
BIN
Binary file not shown.
+137
@@ -0,0 +1,137 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_gpio_0_2</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IP2INTC_IRQ.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_DUAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_gpio_0_2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">21</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_OUTPUTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GPIO_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
+2080
File diff suppressed because it is too large
Load Diff
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
+1521
File diff suppressed because it is too large
Load Diff
+1585
File diff suppressed because it is too large
Load Diff
+42
@@ -0,0 +1,42 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
// Date : Fri Feb 24 19:11:40 2023
|
||||
// Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_01/datalink814_gch_z045_smart_pwrst_001.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_2/system_bd_axi_gpio_0_2_stub.v
|
||||
// Design : system_bd_axi_gpio_0_2
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z045ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2019.1" *)
|
||||
module system_bd_axi_gpio_0_2(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[0:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [0:0]gpio_io_o;
|
||||
endmodule
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
|
||||
-- Date : Fri Feb 24 19:11:40 2023
|
||||
-- Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- E:/814/Glink/beamcontrol/datalink814_z045_smart_c2c_01/datalink814_gch_z045_smart_pwrst_001.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_2/system_bd_axi_gpio_0_2_stub.vhdl
|
||||
-- Design : system_bd_axi_gpio_0_2
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z045ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_gpio_0_2 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_gpio_0_2;
|
||||
|
||||
architecture stub of system_bd_axi_gpio_0_2 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2019.1";
|
||||
begin
|
||||
end;
|
||||
+3856
File diff suppressed because it is too large
Load Diff
+259
@@ -0,0 +1,259 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="37">
|
||||
<CompositeFile CompositeFileTopName="bd_3c1f" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1677315623"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1677315623"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1677315623"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1677315623"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth/bd_3c1f.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
</File>
|
||||
<File Name="sim/bd_3c1f.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="sim/bd_3c1f.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_0/bd_3c1f_one_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="clk_map/one"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_1/bd_3c1f_psr_aclk_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="clk_map/psr_aclk"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_2/bd_3c1f_arsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/ar_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_3/bd_3c1f_rsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/r_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_4/bd_3c1f_awsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/aw_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_5/bd_3c1f_wsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/w_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_6/bd_3c1f_bsw_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="switchboards/b_switchboard"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_7/bd_3c1f_s00mmu_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_entry_pipeline/s00_mmu"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_8/bd_3c1f_s00tr_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_entry_pipeline/s00_transaction_regulator"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_9/bd_3c1f_s00sic_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_entry_pipeline/s00_si_converter"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_10/bd_3c1f_s00a2s_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_axi2sc"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_11/bd_3c1f_sarn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_nodes/s00_ar_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_12/bd_3c1f_srn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s00_nodes/s00_r_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_13/bd_3c1f_s01mmu_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_entry_pipeline/s01_mmu"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_14/bd_3c1f_s01tr_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_entry_pipeline/s01_transaction_regulator"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_15/bd_3c1f_s01sic_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_entry_pipeline/s01_si_converter"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_16/bd_3c1f_s01a2s_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_axi2sc"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_17/bd_3c1f_sawn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_nodes/s01_aw_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_18/bd_3c1f_swn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_nodes/s01_w_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_19/bd_3c1f_sbn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="s01_nodes/s01_b_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_20/bd_3c1f_m00s2a_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_sc2axi"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_21/bd_3c1f_m00arn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_ar_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_22/bd_3c1f_m00rn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_r_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_23/bd_3c1f_m00awn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_aw_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_24/bd_3c1f_m00wn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_w_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_25/bd_3c1f_m00bn_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_nodes/m00_b_node"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="ip/ip_26/bd_3c1f_m00e_0.xci" Type="IP">
|
||||
<Instance HierarchyPath="m00_exit_pipeline/m00_exit"/>
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
</File>
|
||||
<File Name="hw_handoff/system_bd_axi_smc_0.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
</File>
|
||||
<File Name="hw_handoff/system_bd_axi_smc_0_bd.tcl">
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
</File>
|
||||
<File Name="synth/system_bd_axi_smc_0.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+285
@@ -0,0 +1,285 @@
|
||||
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3c1f_wrapper.bd
|
||||
//Design : bd_3c1f_wrapper
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module bd_3c1f_wrapper
|
||||
(M00_AXI_araddr,
|
||||
M00_AXI_arburst,
|
||||
M00_AXI_arcache,
|
||||
M00_AXI_arlen,
|
||||
M00_AXI_arlock,
|
||||
M00_AXI_arprot,
|
||||
M00_AXI_arqos,
|
||||
M00_AXI_arready,
|
||||
M00_AXI_arsize,
|
||||
M00_AXI_arvalid,
|
||||
M00_AXI_awaddr,
|
||||
M00_AXI_awburst,
|
||||
M00_AXI_awcache,
|
||||
M00_AXI_awlen,
|
||||
M00_AXI_awlock,
|
||||
M00_AXI_awprot,
|
||||
M00_AXI_awqos,
|
||||
M00_AXI_awready,
|
||||
M00_AXI_awsize,
|
||||
M00_AXI_awvalid,
|
||||
M00_AXI_bready,
|
||||
M00_AXI_bresp,
|
||||
M00_AXI_bvalid,
|
||||
M00_AXI_rdata,
|
||||
M00_AXI_rlast,
|
||||
M00_AXI_rready,
|
||||
M00_AXI_rresp,
|
||||
M00_AXI_rvalid,
|
||||
M00_AXI_wdata,
|
||||
M00_AXI_wlast,
|
||||
M00_AXI_wready,
|
||||
M00_AXI_wstrb,
|
||||
M00_AXI_wvalid,
|
||||
S00_AXI_araddr,
|
||||
S00_AXI_arburst,
|
||||
S00_AXI_arcache,
|
||||
S00_AXI_arlen,
|
||||
S00_AXI_arlock,
|
||||
S00_AXI_arprot,
|
||||
S00_AXI_arqos,
|
||||
S00_AXI_arready,
|
||||
S00_AXI_arsize,
|
||||
S00_AXI_arvalid,
|
||||
S00_AXI_rdata,
|
||||
S00_AXI_rlast,
|
||||
S00_AXI_rready,
|
||||
S00_AXI_rresp,
|
||||
S00_AXI_rvalid,
|
||||
S01_AXI_awaddr,
|
||||
S01_AXI_awburst,
|
||||
S01_AXI_awcache,
|
||||
S01_AXI_awlen,
|
||||
S01_AXI_awlock,
|
||||
S01_AXI_awprot,
|
||||
S01_AXI_awqos,
|
||||
S01_AXI_awready,
|
||||
S01_AXI_awsize,
|
||||
S01_AXI_awvalid,
|
||||
S01_AXI_bready,
|
||||
S01_AXI_bresp,
|
||||
S01_AXI_bvalid,
|
||||
S01_AXI_wdata,
|
||||
S01_AXI_wlast,
|
||||
S01_AXI_wready,
|
||||
S01_AXI_wstrb,
|
||||
S01_AXI_wvalid,
|
||||
aclk,
|
||||
aresetn);
|
||||
output [31:0]M00_AXI_araddr;
|
||||
output [1:0]M00_AXI_arburst;
|
||||
output [3:0]M00_AXI_arcache;
|
||||
output [3:0]M00_AXI_arlen;
|
||||
output [1:0]M00_AXI_arlock;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
output [3:0]M00_AXI_arqos;
|
||||
input M00_AXI_arready;
|
||||
output [2:0]M00_AXI_arsize;
|
||||
output M00_AXI_arvalid;
|
||||
output [31:0]M00_AXI_awaddr;
|
||||
output [1:0]M00_AXI_awburst;
|
||||
output [3:0]M00_AXI_awcache;
|
||||
output [3:0]M00_AXI_awlen;
|
||||
output [1:0]M00_AXI_awlock;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
output [3:0]M00_AXI_awqos;
|
||||
input M00_AXI_awready;
|
||||
output [2:0]M00_AXI_awsize;
|
||||
output M00_AXI_awvalid;
|
||||
output M00_AXI_bready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
input [63:0]M00_AXI_rdata;
|
||||
input M00_AXI_rlast;
|
||||
output M00_AXI_rready;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rvalid;
|
||||
output [63:0]M00_AXI_wdata;
|
||||
output M00_AXI_wlast;
|
||||
input M00_AXI_wready;
|
||||
output [7:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wvalid;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [7:0]S00_AXI_arlen;
|
||||
input [0:0]S00_AXI_arlock;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
output S00_AXI_arready;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input S00_AXI_arvalid;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output S00_AXI_rlast;
|
||||
input S00_AXI_rready;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rvalid;
|
||||
input [31:0]S01_AXI_awaddr;
|
||||
input [1:0]S01_AXI_awburst;
|
||||
input [3:0]S01_AXI_awcache;
|
||||
input [7:0]S01_AXI_awlen;
|
||||
input [0:0]S01_AXI_awlock;
|
||||
input [2:0]S01_AXI_awprot;
|
||||
input [3:0]S01_AXI_awqos;
|
||||
output S01_AXI_awready;
|
||||
input [2:0]S01_AXI_awsize;
|
||||
input S01_AXI_awvalid;
|
||||
input S01_AXI_bready;
|
||||
output [1:0]S01_AXI_bresp;
|
||||
output S01_AXI_bvalid;
|
||||
input [31:0]S01_AXI_wdata;
|
||||
input S01_AXI_wlast;
|
||||
output S01_AXI_wready;
|
||||
input [3:0]S01_AXI_wstrb;
|
||||
input S01_AXI_wvalid;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
|
||||
wire [31:0]M00_AXI_araddr;
|
||||
wire [1:0]M00_AXI_arburst;
|
||||
wire [3:0]M00_AXI_arcache;
|
||||
wire [3:0]M00_AXI_arlen;
|
||||
wire [1:0]M00_AXI_arlock;
|
||||
wire [2:0]M00_AXI_arprot;
|
||||
wire [3:0]M00_AXI_arqos;
|
||||
wire M00_AXI_arready;
|
||||
wire [2:0]M00_AXI_arsize;
|
||||
wire M00_AXI_arvalid;
|
||||
wire [31:0]M00_AXI_awaddr;
|
||||
wire [1:0]M00_AXI_awburst;
|
||||
wire [3:0]M00_AXI_awcache;
|
||||
wire [3:0]M00_AXI_awlen;
|
||||
wire [1:0]M00_AXI_awlock;
|
||||
wire [2:0]M00_AXI_awprot;
|
||||
wire [3:0]M00_AXI_awqos;
|
||||
wire M00_AXI_awready;
|
||||
wire [2:0]M00_AXI_awsize;
|
||||
wire M00_AXI_awvalid;
|
||||
wire M00_AXI_bready;
|
||||
wire [1:0]M00_AXI_bresp;
|
||||
wire M00_AXI_bvalid;
|
||||
wire [63:0]M00_AXI_rdata;
|
||||
wire M00_AXI_rlast;
|
||||
wire M00_AXI_rready;
|
||||
wire [1:0]M00_AXI_rresp;
|
||||
wire M00_AXI_rvalid;
|
||||
wire [63:0]M00_AXI_wdata;
|
||||
wire M00_AXI_wlast;
|
||||
wire M00_AXI_wready;
|
||||
wire [7:0]M00_AXI_wstrb;
|
||||
wire M00_AXI_wvalid;
|
||||
wire [31:0]S00_AXI_araddr;
|
||||
wire [1:0]S00_AXI_arburst;
|
||||
wire [3:0]S00_AXI_arcache;
|
||||
wire [7:0]S00_AXI_arlen;
|
||||
wire [0:0]S00_AXI_arlock;
|
||||
wire [2:0]S00_AXI_arprot;
|
||||
wire [3:0]S00_AXI_arqos;
|
||||
wire S00_AXI_arready;
|
||||
wire [2:0]S00_AXI_arsize;
|
||||
wire S00_AXI_arvalid;
|
||||
wire [31:0]S00_AXI_rdata;
|
||||
wire S00_AXI_rlast;
|
||||
wire S00_AXI_rready;
|
||||
wire [1:0]S00_AXI_rresp;
|
||||
wire S00_AXI_rvalid;
|
||||
wire [31:0]S01_AXI_awaddr;
|
||||
wire [1:0]S01_AXI_awburst;
|
||||
wire [3:0]S01_AXI_awcache;
|
||||
wire [7:0]S01_AXI_awlen;
|
||||
wire [0:0]S01_AXI_awlock;
|
||||
wire [2:0]S01_AXI_awprot;
|
||||
wire [3:0]S01_AXI_awqos;
|
||||
wire S01_AXI_awready;
|
||||
wire [2:0]S01_AXI_awsize;
|
||||
wire S01_AXI_awvalid;
|
||||
wire S01_AXI_bready;
|
||||
wire [1:0]S01_AXI_bresp;
|
||||
wire S01_AXI_bvalid;
|
||||
wire [31:0]S01_AXI_wdata;
|
||||
wire S01_AXI_wlast;
|
||||
wire S01_AXI_wready;
|
||||
wire [3:0]S01_AXI_wstrb;
|
||||
wire S01_AXI_wvalid;
|
||||
wire aclk;
|
||||
wire aresetn;
|
||||
|
||||
bd_3c1f bd_3c1f_i
|
||||
(.M00_AXI_araddr(M00_AXI_araddr),
|
||||
.M00_AXI_arburst(M00_AXI_arburst),
|
||||
.M00_AXI_arcache(M00_AXI_arcache),
|
||||
.M00_AXI_arlen(M00_AXI_arlen),
|
||||
.M00_AXI_arlock(M00_AXI_arlock),
|
||||
.M00_AXI_arprot(M00_AXI_arprot),
|
||||
.M00_AXI_arqos(M00_AXI_arqos),
|
||||
.M00_AXI_arready(M00_AXI_arready),
|
||||
.M00_AXI_arsize(M00_AXI_arsize),
|
||||
.M00_AXI_arvalid(M00_AXI_arvalid),
|
||||
.M00_AXI_awaddr(M00_AXI_awaddr),
|
||||
.M00_AXI_awburst(M00_AXI_awburst),
|
||||
.M00_AXI_awcache(M00_AXI_awcache),
|
||||
.M00_AXI_awlen(M00_AXI_awlen),
|
||||
.M00_AXI_awlock(M00_AXI_awlock),
|
||||
.M00_AXI_awprot(M00_AXI_awprot),
|
||||
.M00_AXI_awqos(M00_AXI_awqos),
|
||||
.M00_AXI_awready(M00_AXI_awready),
|
||||
.M00_AXI_awsize(M00_AXI_awsize),
|
||||
.M00_AXI_awvalid(M00_AXI_awvalid),
|
||||
.M00_AXI_bready(M00_AXI_bready),
|
||||
.M00_AXI_bresp(M00_AXI_bresp),
|
||||
.M00_AXI_bvalid(M00_AXI_bvalid),
|
||||
.M00_AXI_rdata(M00_AXI_rdata),
|
||||
.M00_AXI_rlast(M00_AXI_rlast),
|
||||
.M00_AXI_rready(M00_AXI_rready),
|
||||
.M00_AXI_rresp(M00_AXI_rresp),
|
||||
.M00_AXI_rvalid(M00_AXI_rvalid),
|
||||
.M00_AXI_wdata(M00_AXI_wdata),
|
||||
.M00_AXI_wlast(M00_AXI_wlast),
|
||||
.M00_AXI_wready(M00_AXI_wready),
|
||||
.M00_AXI_wstrb(M00_AXI_wstrb),
|
||||
.M00_AXI_wvalid(M00_AXI_wvalid),
|
||||
.S00_AXI_araddr(S00_AXI_araddr),
|
||||
.S00_AXI_arburst(S00_AXI_arburst),
|
||||
.S00_AXI_arcache(S00_AXI_arcache),
|
||||
.S00_AXI_arlen(S00_AXI_arlen),
|
||||
.S00_AXI_arlock(S00_AXI_arlock),
|
||||
.S00_AXI_arprot(S00_AXI_arprot),
|
||||
.S00_AXI_arqos(S00_AXI_arqos),
|
||||
.S00_AXI_arready(S00_AXI_arready),
|
||||
.S00_AXI_arsize(S00_AXI_arsize),
|
||||
.S00_AXI_arvalid(S00_AXI_arvalid),
|
||||
.S00_AXI_rdata(S00_AXI_rdata),
|
||||
.S00_AXI_rlast(S00_AXI_rlast),
|
||||
.S00_AXI_rready(S00_AXI_rready),
|
||||
.S00_AXI_rresp(S00_AXI_rresp),
|
||||
.S00_AXI_rvalid(S00_AXI_rvalid),
|
||||
.S01_AXI_awaddr(S01_AXI_awaddr),
|
||||
.S01_AXI_awburst(S01_AXI_awburst),
|
||||
.S01_AXI_awcache(S01_AXI_awcache),
|
||||
.S01_AXI_awlen(S01_AXI_awlen),
|
||||
.S01_AXI_awlock(S01_AXI_awlock),
|
||||
.S01_AXI_awprot(S01_AXI_awprot),
|
||||
.S01_AXI_awqos(S01_AXI_awqos),
|
||||
.S01_AXI_awready(S01_AXI_awready),
|
||||
.S01_AXI_awsize(S01_AXI_awsize),
|
||||
.S01_AXI_awvalid(S01_AXI_awvalid),
|
||||
.S01_AXI_bready(S01_AXI_bready),
|
||||
.S01_AXI_bresp(S01_AXI_bresp),
|
||||
.S01_AXI_bvalid(S01_AXI_bvalid),
|
||||
.S01_AXI_wdata(S01_AXI_wdata),
|
||||
.S01_AXI_wlast(S01_AXI_wlast),
|
||||
.S01_AXI_wready(S01_AXI_wready),
|
||||
.S01_AXI_wstrb(S01_AXI_wstrb),
|
||||
.S01_AXI_wvalid(S01_AXI_wvalid),
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn));
|
||||
endmodule
|
||||
+14083
File diff suppressed because it is too large
Load Diff
+1653
File diff suppressed because it is too large
Load Diff
+41
@@ -0,0 +1,41 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_3c1f_one_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_3c1f_one_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+262
@@ -0,0 +1,262 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>bd_3c1f_one_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>xlconstant_v1_1_6_xlconstant</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 25 09:00:21 UTC 2023</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6939c268</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6939c268</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>bd_3c1f_one_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 25 09:00:21 UTC 2023</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6939c268</spirit:value>
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+67
@@ -0,0 +1,67 @@
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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _bd_3c1f_one_0_H_
|
||||
#define _bd_3c1f_one_0_H_
|
||||
|
||||
#include "xlconstant_v1_1_6.h"
|
||||
#include "systemc.h"
|
||||
class bd_3c1f_one_0 : public sc_module {
|
||||
public:
|
||||
xlconstant_v1_1_6<1,1> mod;
|
||||
sc_out< sc_bv<1> > dout;
|
||||
bd_3c1f_one_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
|
||||
mod.dout(dout);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 6
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_one_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_6_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL('H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _xlconstant_v1_1_6_H_
|
||||
#define _xlconstant_v1_1_6_H_
|
||||
|
||||
#include "systemc.h"
|
||||
template<int CONST_WIDTH,int CONST_VAL>
|
||||
SC_MODULE(xlconstant_v1_1_6) {
|
||||
public:
|
||||
sc_out< sc_bv<CONST_WIDTH> > dout;
|
||||
void init() {
|
||||
dout.write(CONST_VAL);
|
||||
}
|
||||
SC_CTOR(xlconstant_v1_1_6) {
|
||||
SC_METHOD(init);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 6
|
||||
|
||||
(* X_CORE_INFO = "xlconstant_v1_1_6_xlconstant,Vivado 2019.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_3c1f_one_0,xlconstant_v1_1_6_xlconstant,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_3c1f_one_0,xlconstant_v1_1_6_xlconstant,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_one_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_6_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL('H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+83
@@ -0,0 +1,83 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_3c1f_psr_aclk_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_3c1f_psr_aclk_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
|
||||
# file: bd_3c1f_psr_aclk_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
+872
@@ -0,0 +1,872 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>bd_3c1f_psr_aclk_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clock</spirit:name>
|
||||
<spirit:displayName>Clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">1e+08</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ext_reset</spirit:name>
|
||||
<spirit:displayName>Ext_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:presence>required</xilinx:presence>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
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</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dcm_locked</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_BUS_RST')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>peripheral_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_RST')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>peripheral_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
|
||||
<spirit:name>C_FAMILY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_ac75ef1e</spirit:name>
|
||||
<spirit:enumeration>Custom</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_3c1f_psr_aclk_0.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/bd_3c1f_psr_aclk_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/bd_3c1f_psr_aclk_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_3c1f_psr_aclk_0_board.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Processor Reset System</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_3c1f_psr_aclk_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
||||
<xilinx:coreRevision>13</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY bd_3c1f_psr_aclk_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_3c1f_psr_aclk_0;
|
||||
|
||||
ARCHITECTURE bd_3c1f_psr_aclk_0_arch OF bd_3c1f_psr_aclk_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_3c1f_psr_aclk_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 1,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END bd_3c1f_psr_aclk_0_arch;
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY bd_3c1f_psr_aclk_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_3c1f_psr_aclk_0;
|
||||
|
||||
ARCHITECTURE bd_3c1f_psr_aclk_0_arch OF bd_3c1f_psr_aclk_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_3c1f_psr_aclk_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF bd_3c1f_psr_aclk_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2019.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_3c1f_psr_aclk_0_arch : ARCHITECTURE IS "bd_3c1f_psr_aclk_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_3c1f_psr_aclk_0_arch: ARCHITECTURE IS "bd_3c1f_psr_aclk_0,proc_sys_reset,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=1,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 1,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END bd_3c1f_psr_aclk_0_arch;
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_3c1f_s00a2s_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="sc_axi2sc" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_RDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_WDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_RDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_WDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_3c1f_s00a2s_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_RDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_WDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SSC_ROUTE_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXI_ADDR_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXI_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXI_RDATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXI_WDATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MSC_ROUTE_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_ADDR_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_ARUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_AWUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_BUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_RDATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_RUSER_BITS_PER_BYTE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_WDATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_WUSER_BITS_PER_BYTE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SSC_ROUTE_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+2914
File diff suppressed because it is too large
Load Diff
+51
@@ -0,0 +1,51 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2015 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
#
|
||||
# Port aclk is never used.
|
||||
#
|
||||
+234
@@ -0,0 +1,234 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_axi2sc:1.0
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_s00a2s_0 (
|
||||
aclk,
|
||||
s_sc_r_req,
|
||||
s_sc_r_info,
|
||||
s_sc_r_send,
|
||||
s_sc_r_recv,
|
||||
s_sc_r_payld,
|
||||
m_sc_ar_req,
|
||||
m_sc_ar_info,
|
||||
m_sc_ar_send,
|
||||
m_sc_ar_recv,
|
||||
m_sc_ar_payld,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R REQ" *)
|
||||
input wire s_sc_r_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R INFO" *)
|
||||
input wire [0 : 0] s_sc_r_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R SEND" *)
|
||||
input wire s_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R RECV" *)
|
||||
output wire s_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R PAYLD" *)
|
||||
input wire [83 : 0] s_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR REQ" *)
|
||||
output wire m_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR INFO" *)
|
||||
output wire [0 : 0] m_sc_ar_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR SEND" *)
|
||||
output wire m_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR RECV" *)
|
||||
input wire m_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR PAYLD" *)
|
||||
output wire [137 : 0] m_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [0 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
sc_axi2sc_v1_0_7_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(1),
|
||||
.C_SC_RDATA_WIDTH(64),
|
||||
.C_SC_WDATA_WIDTH(64),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(2),
|
||||
.C_AWPAYLD_WIDTH(138),
|
||||
.C_ARPAYLD_WIDTH(138),
|
||||
.C_WPAYLD_WIDTH(88),
|
||||
.C_RPAYLD_WIDTH(84),
|
||||
.C_BPAYLD_WIDTH(6)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(s_sc_r_req),
|
||||
.s_sc_r_info(s_sc_r_info),
|
||||
.s_sc_r_send(s_sc_r_send),
|
||||
.s_sc_r_recv(s_sc_r_recv),
|
||||
.s_sc_r_payld(s_sc_r_payld),
|
||||
.s_sc_b_req(1'D0),
|
||||
.s_sc_b_info(1'D0),
|
||||
.s_sc_b_send(1'D0),
|
||||
.s_sc_b_recv(),
|
||||
.s_sc_b_payld(6'D0),
|
||||
.m_sc_ar_req(m_sc_ar_req),
|
||||
.m_sc_ar_info(m_sc_ar_info),
|
||||
.m_sc_ar_send(m_sc_ar_send),
|
||||
.m_sc_ar_recv(m_sc_ar_recv),
|
||||
.m_sc_ar_payld(m_sc_ar_payld),
|
||||
.m_sc_aw_req(),
|
||||
.m_sc_aw_info(),
|
||||
.m_sc_aw_send(),
|
||||
.m_sc_aw_recv(1'D0),
|
||||
.m_sc_aw_payld(),
|
||||
.m_sc_w_req(),
|
||||
.m_sc_w_info(),
|
||||
.m_sc_w_send(),
|
||||
.m_sc_w_recv(1'D0),
|
||||
.m_sc_w_payld(),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H0),
|
||||
.s_axi_awlock(1'H0),
|
||||
.s_axi_awcache(4'H0),
|
||||
.s_axi_awprot(3'H0),
|
||||
.s_axi_awqos(4'H0),
|
||||
.s_axi_awuser(1024'H0),
|
||||
.s_axi_awvalid(1'H0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(32'H00000000),
|
||||
.s_axi_wstrb(4'HF),
|
||||
.s_axi_wlast(1'H1),
|
||||
.s_axi_wuser(1024'H0),
|
||||
.s_axi_wvalid(1'H0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'H0),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+236
@@ -0,0 +1,236 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_axi2sc:1.0
|
||||
// IP Revision: 7
|
||||
|
||||
(* X_CORE_INFO = "sc_axi2sc_v1_0_7_top,Vivado 2019.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_3c1f_s00a2s_0,sc_axi2sc_v1_0_7_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_3c1f_s00a2s_0,sc_axi2sc_v1_0_7_top,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_axi2sc,x_ipVersion=1.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_AXI_ADDR_WIDTH=32,C_AXI_ID_WIDTH=1,C_AXI_RDATA_WIDTH=32,C_AXI_WDATA_WIDTH=32,C_SC_ADDR_WIDTH=32,C_SC_ID_WIDTH=1,C_SC_RDATA_WIDTH=64,C_SC_WDATA_WIDTH=64,C_SC_RUSER_BITS_PER_BYTE=0,C_SC_WUSER_BITS_PER_BYTE=0,C_SC_ARUSER_WIDTH=0,C_SC_AWUSER_WIDTH=0,C_SC_BUSER_WIDTH=0,C_MSC_ROUTE_WIDTH=1,C_SSC_ROUTE_WI\
|
||||
DTH=2,C_AWPAYLD_WIDTH=138,C_ARPAYLD_WIDTH=138,C_WPAYLD_WIDTH=88,C_RPAYLD_WIDTH=84,C_BPAYLD_WIDTH=6}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_s00a2s_0 (
|
||||
aclk,
|
||||
s_sc_r_req,
|
||||
s_sc_r_info,
|
||||
s_sc_r_send,
|
||||
s_sc_r_recv,
|
||||
s_sc_r_payld,
|
||||
m_sc_ar_req,
|
||||
m_sc_ar_info,
|
||||
m_sc_ar_send,
|
||||
m_sc_ar_recv,
|
||||
m_sc_ar_payld,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_aruser,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_ruser,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:M_AR_SC:M_AW_SC:M_W_SC:S_R_SC:S_B_SC, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R REQ" *)
|
||||
input wire s_sc_r_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R INFO" *)
|
||||
input wire [0 : 0] s_sc_r_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R SEND" *)
|
||||
input wire s_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R RECV" *)
|
||||
output wire s_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_R PAYLD" *)
|
||||
input wire [83 : 0] s_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR REQ" *)
|
||||
output wire m_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR INFO" *)
|
||||
output wire [0 : 0] m_sc_ar_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR SEND" *)
|
||||
output wire m_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR RECV" *)
|
||||
input wire m_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_AR PAYLD" *)
|
||||
output wire [137 : 0] m_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [0 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [7 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [0 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
|
||||
input wire [1023 : 0] s_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RUSER" *)
|
||||
output wire [1023 : 0] s_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 1024, WUSER_WIDTH 0, RUSER_WIDTH 1024, BUSER_WIDTH 0, READ_WRITE_MODE READ_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 0, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
|
||||
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
sc_axi2sc_v1_0_7_top #(
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(32),
|
||||
.C_SC_ID_WIDTH(1),
|
||||
.C_SC_RDATA_WIDTH(64),
|
||||
.C_SC_WDATA_WIDTH(64),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(2),
|
||||
.C_AWPAYLD_WIDTH(138),
|
||||
.C_ARPAYLD_WIDTH(138),
|
||||
.C_WPAYLD_WIDTH(88),
|
||||
.C_RPAYLD_WIDTH(84),
|
||||
.C_BPAYLD_WIDTH(6)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.s_sc_r_req(s_sc_r_req),
|
||||
.s_sc_r_info(s_sc_r_info),
|
||||
.s_sc_r_send(s_sc_r_send),
|
||||
.s_sc_r_recv(s_sc_r_recv),
|
||||
.s_sc_r_payld(s_sc_r_payld),
|
||||
.s_sc_b_req(1'D0),
|
||||
.s_sc_b_info(1'D0),
|
||||
.s_sc_b_send(1'D0),
|
||||
.s_sc_b_recv(),
|
||||
.s_sc_b_payld(6'D0),
|
||||
.m_sc_ar_req(m_sc_ar_req),
|
||||
.m_sc_ar_info(m_sc_ar_info),
|
||||
.m_sc_ar_send(m_sc_ar_send),
|
||||
.m_sc_ar_recv(m_sc_ar_recv),
|
||||
.m_sc_ar_payld(m_sc_ar_payld),
|
||||
.m_sc_aw_req(),
|
||||
.m_sc_aw_info(),
|
||||
.m_sc_aw_send(),
|
||||
.m_sc_aw_recv(1'D0),
|
||||
.m_sc_aw_payld(),
|
||||
.m_sc_w_req(),
|
||||
.m_sc_w_info(),
|
||||
.m_sc_w_send(),
|
||||
.m_sc_w_recv(1'D0),
|
||||
.m_sc_w_payld(),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(32'H00000000),
|
||||
.s_axi_awlen(8'H0),
|
||||
.s_axi_awlock(1'H0),
|
||||
.s_axi_awcache(4'H0),
|
||||
.s_axi_awprot(3'H0),
|
||||
.s_axi_awqos(4'H0),
|
||||
.s_axi_awuser(1024'H0),
|
||||
.s_axi_awvalid(1'H0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(32'H00000000),
|
||||
.s_axi_wstrb(4'HF),
|
||||
.s_axi_wlast(1'H1),
|
||||
.s_axi_wuser(1024'H0),
|
||||
.s_axi_wvalid(1'H0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'H0),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(s_axi_aruser),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(s_axi_ruser),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+215
@@ -0,0 +1,215 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_3c1f_sarn_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="sc_node" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLKEN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_SC_ACLKEN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLKEN_CONVERSION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLK_RELATIONSHIP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARBITER_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINING">0x01</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_OUTPUT_REG">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_SIZE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MAX_PAYLD_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_NUM_BYTES_ARRAY">0x00000008</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_PIPELINE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_SEND_PIPELINE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUTSTANDING">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_SI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PAYLD_WIDTH">138</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_LATENCY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_NUM_BYTES_ARRAY">0x00000004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_PIPELINE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONVERSION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLK_RELATIONSHIP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARBITER_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_3c1f_sarn_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PIPELINING">0x01</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_OUTPUT_REG">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_SIZE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M00_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M01_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M02_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M04_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M05_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M06_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M07_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M08_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M09_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M10_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M11_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M12_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M13_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M14_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M15_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MAX_PAYLD_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_PIPELINE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_SEND_PIPELINE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUTSTANDING">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_SI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PAYLD_WIDTH">138</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S00_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S01_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S02_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S03_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S04_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S05_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S06_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S07_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S08_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S09_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S10_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S11_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S12_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S13_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S14_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S15_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_LATENCY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_PIPELINE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLKEN_CONVERSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RELATIONSHIP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CHANNEL" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M00_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M01_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M02_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M05_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M06_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M07_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M08_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M09_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M10_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M11_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M12_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M13_NUM_BYTES" xilinx:valueSource="user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M14_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M15_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MAX_PAYLD_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_PIPELINE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_MI" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUTSTANDING" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_SI" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PAYLD_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S00_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S01_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S02_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S03_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S04_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S05_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S06_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S07_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S08_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S09_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S10_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S11_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S12_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S13_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S14_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S15_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_ROUTE_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USER_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+1838
File diff suppressed because it is too large
Load Diff
+52
@@ -0,0 +1,52 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
create_clock -period 100.0 -name s_sc_aclk [get_ports s_sc_aclk]
|
||||
|
||||
|
||||
+159
@@ -0,0 +1,159 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 10
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_sarn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [137 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [137 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_10_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(138),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000008),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(8),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
+161
@@ -0,0 +1,161 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 10
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_10_top,Vivado 2019.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_3c1f_sarn_0,sc_node_v1_0_10_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_3c1f_sarn_0,sc_node_v1_0_10_top,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=2,C_PAYLD_WIDTH=138,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000008,C_USER_BITS_PER_BYTE=0,C_ARBITER_MODE=1,C_SC_ROUTE\
|
||||
_WIDTH=1,C_ID_WIDTH=1,C_ADDR_WIDTH=32,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=8,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=1,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_sarn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [137 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [137 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_10_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(2),
|
||||
.C_PAYLD_WIDTH(138),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000008),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(8),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(1),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
+216
@@ -0,0 +1,216 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_3c1f_srn_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="sc_node" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLKEN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_SC_ACLKEN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLKEN_CONVERSION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLK_RELATIONSHIP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARBITER_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINING">0x01</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_OUTPUT_REG">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_SIZE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MAX_PAYLD_BYTES">8</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M04_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M05_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M07_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M08_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M09_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M10_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M11_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M12_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M13_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M14_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M15_NUM_BYTES">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MAX_PAYLD_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_PIPELINE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_SEND_PIPELINE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUTSTANDING">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_SI">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PAYLD_WIDTH">84</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S00_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S01_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S02_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S03_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S04_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S05_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S06_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S07_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S08_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S09_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S10_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S11_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S12_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S13_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S14_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S15_NUM_BYTES">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ROUTE_WIDTH">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_WIDTH">512</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../../ipshared</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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</spirit:configurableElementValues>
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<spirit:vendorExtensions>
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<xilinx:componentInstanceExtensions>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MAX_PAYLD_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_SEND_PIPELINE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_MI" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUTSTANDING" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_SI" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PAYLD_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S00_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S01_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S10_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S11_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S12_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S13_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S14_NUM_BYTES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SC_ROUTE_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_LATENCY" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USER_BITS_PER_BYTE" xilinx:valueSource="user"/>
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</xilinx:configElementInfos>
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</xilinx:componentInstanceExtensions>
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</spirit:vendorExtensions>
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</spirit:componentInstance>
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</spirit:componentInstances>
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</spirit:design>
|
||||
+1839
File diff suppressed because it is too large
Load Diff
+52
@@ -0,0 +1,52 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
create_clock -period 100.0 -name s_sc_aclk [get_ports s_sc_aclk]
|
||||
|
||||
|
||||
+159
@@ -0,0 +1,159 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 10
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_srn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [83 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [83 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_10_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(84),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000008),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(2),
|
||||
.C_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(8),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
+161
@@ -0,0 +1,161 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 10
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_10_top,Vivado 2019.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_3c1f_srn_0,sc_node_v1_0_10_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_3c1f_srn_0,sc_node_v1_0_10_top,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=0,C_PAYLD_WIDTH=84,C_S_NUM_BYTES_ARRAY=0x00000008,C_M_NUM_BYTES_ARRAY=0x0000000400000004,C_USER_BITS_PER_BYTE=0,C_ARBITER_MODE=1,C_SC\
|
||||
_ROUTE_WIDTH=2,C_ID_WIDTH=1,C_ADDR_WIDTH=32,C_USER_WIDTH=512,C_MAX_PAYLD_BYTES=8,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=0,C_S_LATENCY=1,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_srn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [83 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [83 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_10_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(0),
|
||||
.C_PAYLD_WIDTH(84),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000008),
|
||||
.C_M_NUM_BYTES_ARRAY(64'H0000000400000004),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(2),
|
||||
.C_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_USER_WIDTH(512),
|
||||
.C_MAX_PAYLD_BYTES(8),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(1),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
+2117
File diff suppressed because it is too large
Load Diff
+13451
File diff suppressed because it is too large
Load Diff
+313
@@ -0,0 +1,313 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_mmu:1.0
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_s01mmu_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, \
|
||||
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
|
||||
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_mmu_v1_0_7_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEG_BASE_ADDR_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SIZE_ARRAY(32'H0000001d),
|
||||
.C_SEG_SEP_ROUTE_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SUPPORTS_READ_ARRAY(1'H1),
|
||||
.C_SEG_SUPPORTS_WRITE_ARRAY(1'H1),
|
||||
.C_SEG_SECURE_READ_ARRAY(1'B0),
|
||||
.C_SEG_SECURE_WRITE_ARRAY(1'B0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_MSC_ROUTE_ARRAY(1'B1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(0),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_AWUSER_WIDTH(0),
|
||||
.C_S_ARUSER_WIDTH(0),
|
||||
.C_S_RUSER_WIDTH(0),
|
||||
.C_S_WUSER_WIDTH(0),
|
||||
.C_S_BUSER_WIDTH(0),
|
||||
.C_S_PROTOCOL(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_SUPPORTS_WRAP(1),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_SUPPORTS_READ_DECERR(1),
|
||||
.C_SUPPORTS_WRITE_DECERR(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'B1),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H00),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+315
@@ -0,0 +1,315 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_mmu:1.0
|
||||
// IP Revision: 7
|
||||
|
||||
(* X_CORE_INFO = "sc_mmu_v1_0_7_top,Vivado 2019.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_3c1f_s01mmu_0,sc_mmu_v1_0_7_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_3c1f_s01mmu_0,sc_mmu_v1_0_7_top,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_mmu,x_ipVersion=1.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_IS_CASCADED=0,C_ENABLE_PIPELINING=0x1,C_NUM_SEG=1,C_SEG_BASE_ADDR_ARRAY=0x0000000000000000,C_SEG_SIZE_ARRAY=0x0000001d,C_SEG_SEP_ROUTE_ARRAY=0x0000000000000000,C_SEG_SUPPORTS_READ_ARRAY=0x1,C_SEG_SUPPORTS_WRITE_ARRAY=0x1,C_SEG_SECURE_READ_ARRAY=0b0,C_SEG_SECURE_WRITE_ARRAY=0b0,C_NUM_MSC=1,C\
|
||||
_MSC_ROUTE_WIDTH=1,C_MSC_ROUTE_ARRAY=0b1,C_ADDR_WIDTH=32,C_ID_WIDTH=0,C_RDATA_WIDTH=32,C_WDATA_WIDTH=32,C_S_AWUSER_WIDTH=0,C_S_ARUSER_WIDTH=0,C_S_RUSER_WIDTH=0,C_S_WUSER_WIDTH=0,C_S_BUSER_WIDTH=0,C_S_PROTOCOL=0,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_SINGLE_ISSUING=0,C_SUPPORTS_WRAP=1,C_SUPPORTS_NARROW=0,C_SUPPORTS_READ_DECERR=1,C_SUPPORTS_WRITE_DECERR=1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_s01mmu_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 64, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, \
|
||||
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
|
||||
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_mmu_v1_0_7_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING(1'H1),
|
||||
.C_NUM_SEG(1),
|
||||
.C_SEG_BASE_ADDR_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SIZE_ARRAY(32'H0000001d),
|
||||
.C_SEG_SEP_ROUTE_ARRAY(64'H0000000000000000),
|
||||
.C_SEG_SUPPORTS_READ_ARRAY(1'H1),
|
||||
.C_SEG_SUPPORTS_WRITE_ARRAY(1'H1),
|
||||
.C_SEG_SECURE_READ_ARRAY(1'B0),
|
||||
.C_SEG_SECURE_WRITE_ARRAY(1'B0),
|
||||
.C_NUM_MSC(1),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_MSC_ROUTE_ARRAY(1'B1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_ID_WIDTH(0),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_AWUSER_WIDTH(0),
|
||||
.C_S_ARUSER_WIDTH(0),
|
||||
.C_S_RUSER_WIDTH(0),
|
||||
.C_S_WUSER_WIDTH(0),
|
||||
.C_S_BUSER_WIDTH(0),
|
||||
.C_S_PROTOCOL(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0),
|
||||
.C_SUPPORTS_WRAP(1),
|
||||
.C_SUPPORTS_NARROW(0),
|
||||
.C_SUPPORTS_READ_DECERR(1),
|
||||
.C_SUPPORTS_WRITE_DECERR(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'B1),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(1'H0),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H00),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(1'H0),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+224
@@ -0,0 +1,224 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_3c1f_s01tr_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="sc_transaction_regulator" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">aresetn</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">WRITE_ONLY</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">1024</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDR_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINING">0x1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_CASCADED">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEP_IDENTIFIER">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEP_IDENTIFIER_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_ID_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_READ_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_WRITE_OUTSTANDING">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_ACCEPTANCE">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEP_ROUTE_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SINGLE_ISSUING">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_ACCEPTANCE">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_3c1f_s01tr_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_CASCADED">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_ACCEPTANCE">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">WRITE_ONLY</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLE_ISSUING">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACCEPTANCE">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../../ipshared</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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<spirit:vendorExtensions>
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<xilinx:componentInstanceExtensions>
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<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IS_CASCADED" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEP_IDENTIFIER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEP_IDENTIFIER_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_READ_OUTSTANDING" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_WRITE_OUTSTANDING" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RDATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SEP_ROUTE_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SUPPORTS_READ_DEADLOCK" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SUPPORTS_WRITE_DEADLOCK" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WDATA_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+4020
File diff suppressed because it is too large
Load Diff
+315
@@ -0,0 +1,315 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_transaction_regulator:1.0
|
||||
// IP Revision: 8
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_s01tr_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CL\
|
||||
K0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [0 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [0 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
|
||||
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_transaction_regulator_v1_0_8_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING('H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(1),
|
||||
.C_MEP_IDENTIFIER(1),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(1'H1),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+317
@@ -0,0 +1,317 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_transaction_regulator:1.0
|
||||
// IP Revision: 8
|
||||
|
||||
(* X_CORE_INFO = "sc_transaction_regulator_v1_0_8_top,Vivado 2019.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_3c1f_s01tr_0,sc_transaction_regulator_v1_0_8_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_3c1f_s01tr_0,sc_transaction_regulator_v1_0_8_top,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_transaction_regulator,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_IS_CASCADED=0,C_ENABLE_PIPELINING=0x1,C_NUM_READ_THREADS=1,C_NUM_WRITE_THREADS=1,C_MEP_IDENTIFIER_WIDTH=1,C_MEP_IDENTIFIER=1,C_SEP_ROUTE_WIDTH=1,C_RDATA_WIDTH=32,C_WDATA_WIDTH=32,C_S_ID_WIDTH=0,C_M_ID_WIDTH=1,C_ADDR_WIDTH=32,C_SUPPORTS_READ_DEADLOCK=0,C_SU\
|
||||
PPORTS_WRITE_DEADLOCK=0,C_READ_ACCEPTANCE=32,C_WRITE_ACCEPTANCE=32,C_NUM_READ_OUTSTANDING=2,C_NUM_WRITE_OUTSTANDING=16,C_SINGLE_ISSUING=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_3c1f_s01tr_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awuser,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wuser,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_buser,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET aresetn, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [7 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [0 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
|
||||
input wire [1023 : 0] s_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WUSER" *)
|
||||
input wire [1023 : 0] s_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BUSER" *)
|
||||
output wire [1023 : 0] s_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, BRIDGES M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CL\
|
||||
K0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [0 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [0 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 1024, ARUSER_WIDTH 0, WUSER_WIDTH 1024, RUSER_WIDTH 0, BUSER_WIDTH 1024, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
|
||||
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
|
||||
sc_transaction_regulator_v1_0_8_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_IS_CASCADED(0),
|
||||
.C_ENABLE_PIPELINING('H1),
|
||||
.C_NUM_READ_THREADS(1),
|
||||
.C_NUM_WRITE_THREADS(1),
|
||||
.C_MEP_IDENTIFIER_WIDTH(1),
|
||||
.C_MEP_IDENTIFIER(1),
|
||||
.C_SEP_ROUTE_WIDTH(1),
|
||||
.C_RDATA_WIDTH(32),
|
||||
.C_WDATA_WIDTH(32),
|
||||
.C_S_ID_WIDTH(0),
|
||||
.C_M_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(32),
|
||||
.C_SUPPORTS_READ_DEADLOCK(0),
|
||||
.C_SUPPORTS_WRITE_DEADLOCK(0),
|
||||
.C_READ_ACCEPTANCE(32),
|
||||
.C_WRITE_ACCEPTANCE(32),
|
||||
.C_NUM_READ_OUTSTANDING(2),
|
||||
.C_NUM_WRITE_OUTSTANDING(16),
|
||||
.C_SINGLE_ISSUING(0)
|
||||
) inst (
|
||||
.mep_identifier(1'H1),
|
||||
.aclk(aclk),
|
||||
.aclken(1'D1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(1'H0),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(s_axi_awuser),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(s_axi_wuser),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(s_axi_buser),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(1'H0),
|
||||
.s_axi_araddr(32'H00000000),
|
||||
.s_axi_arlen(8'H0),
|
||||
.s_axi_arsize(3'H0),
|
||||
.s_axi_arburst(2'H1),
|
||||
.s_axi_arlock(1'H0),
|
||||
.s_axi_arcache(4'H0),
|
||||
.s_axi_arprot(3'H0),
|
||||
.s_axi_arqos(4'H0),
|
||||
.s_axi_aruser(1024'H0),
|
||||
.s_axi_arvalid(1'H0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'H0),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'H0),
|
||||
.m_axi_rid(1'H0),
|
||||
.m_axi_rdata(32'H00000000),
|
||||
.m_axi_rresp(2'H0),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1024'H0),
|
||||
.m_axi_rvalid(1'H0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+1152
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user