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Update gitignore, add dl814_z7 project

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gitignore structure is updated to work with single and multi project situation under a single project directory
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josh
2023-03-29 10:42:01 +08:00
parent b000e2702e
commit cd256a8cd6
2246 changed files with 7838223 additions and 86 deletions
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projects/datalink_814/dl814_z7/ipi-bds/system_bd/hdl/system_bd_wrapper.v
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//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date : Sat Feb 25 17:00:07 2023
//Host : DESKTOP-5MH4P9D running 64-bit major release (build 9200)
//Command : generate_target system_bd_wrapper.bd
//Design : system_bd_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_bd_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
c2c_rst_n,
c2c_rx_clk,
c2c_tx_clk,
glink_gpio_i_0,
glink_gpio_i_1,
glink_gpio_o_0,
glink_gpio_o_1,
glink_ip_clk,
glink_ip_rst_n,
m_axis_fifo_c2c_out_tdata,
m_axis_fifo_c2c_out_tlast,
m_axis_fifo_c2c_out_tready,
m_axis_fifo_c2c_out_tvalid,
m_axis_fifo_glink_out_tdata,
m_axis_fifo_glink_out_tlast,
m_axis_fifo_glink_out_tready,
m_axis_fifo_glink_out_tvalid,
ps_clk,
pwdown_gpio_o,
s_axis_fifo_c2c_in_tdata,
s_axis_fifo_c2c_in_tlast,
s_axis_fifo_c2c_in_tready,
s_axis_fifo_c2c_in_tvalid,
s_axis_fifo_glink_in_tdata,
s_axis_fifo_glink_in_tlast,
s_axis_fifo_glink_in_tready,
s_axis_fifo_glink_in_tvalid);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input c2c_rst_n;
input c2c_rx_clk;
input c2c_tx_clk;
input [31:0]glink_gpio_i_0;
input [31:0]glink_gpio_i_1;
output [31:0]glink_gpio_o_0;
output [31:0]glink_gpio_o_1;
input glink_ip_clk;
input glink_ip_rst_n;
output [31:0]m_axis_fifo_c2c_out_tdata;
output m_axis_fifo_c2c_out_tlast;
input m_axis_fifo_c2c_out_tready;
output m_axis_fifo_c2c_out_tvalid;
output [15:0]m_axis_fifo_glink_out_tdata;
output m_axis_fifo_glink_out_tlast;
input m_axis_fifo_glink_out_tready;
output m_axis_fifo_glink_out_tvalid;
output ps_clk;
output [0:0]pwdown_gpio_o;
input [31:0]s_axis_fifo_c2c_in_tdata;
input s_axis_fifo_c2c_in_tlast;
output s_axis_fifo_c2c_in_tready;
input s_axis_fifo_c2c_in_tvalid;
input [15:0]s_axis_fifo_glink_in_tdata;
input s_axis_fifo_glink_in_tlast;
output s_axis_fifo_glink_in_tready;
input s_axis_fifo_glink_in_tvalid;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire c2c_rst_n;
wire c2c_rx_clk;
wire c2c_tx_clk;
wire [31:0]glink_gpio_i_0;
wire [31:0]glink_gpio_i_1;
wire [31:0]glink_gpio_o_0;
wire [31:0]glink_gpio_o_1;
wire glink_ip_clk;
wire glink_ip_rst_n;
wire [31:0]m_axis_fifo_c2c_out_tdata;
wire m_axis_fifo_c2c_out_tlast;
wire m_axis_fifo_c2c_out_tready;
wire m_axis_fifo_c2c_out_tvalid;
wire [15:0]m_axis_fifo_glink_out_tdata;
wire m_axis_fifo_glink_out_tlast;
wire m_axis_fifo_glink_out_tready;
wire m_axis_fifo_glink_out_tvalid;
wire ps_clk;
wire [0:0]pwdown_gpio_o;
wire [31:0]s_axis_fifo_c2c_in_tdata;
wire s_axis_fifo_c2c_in_tlast;
wire s_axis_fifo_c2c_in_tready;
wire s_axis_fifo_c2c_in_tvalid;
wire [15:0]s_axis_fifo_glink_in_tdata;
wire s_axis_fifo_glink_in_tlast;
wire s_axis_fifo_glink_in_tready;
wire s_axis_fifo_glink_in_tvalid;
system_bd system_bd_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.c2c_rst_n(c2c_rst_n),
.c2c_rx_clk(c2c_rx_clk),
.c2c_tx_clk(c2c_tx_clk),
.glink_gpio_i_0(glink_gpio_i_0),
.glink_gpio_i_1(glink_gpio_i_1),
.glink_gpio_o_0(glink_gpio_o_0),
.glink_gpio_o_1(glink_gpio_o_1),
.glink_ip_clk(glink_ip_clk),
.glink_ip_rst_n(glink_ip_rst_n),
.m_axis_fifo_c2c_out_tdata(m_axis_fifo_c2c_out_tdata),
.m_axis_fifo_c2c_out_tlast(m_axis_fifo_c2c_out_tlast),
.m_axis_fifo_c2c_out_tready(m_axis_fifo_c2c_out_tready),
.m_axis_fifo_c2c_out_tvalid(m_axis_fifo_c2c_out_tvalid),
.m_axis_fifo_glink_out_tdata(m_axis_fifo_glink_out_tdata),
.m_axis_fifo_glink_out_tlast(m_axis_fifo_glink_out_tlast),
.m_axis_fifo_glink_out_tready(m_axis_fifo_glink_out_tready),
.m_axis_fifo_glink_out_tvalid(m_axis_fifo_glink_out_tvalid),
.ps_clk(ps_clk),
.pwdown_gpio_o(pwdown_gpio_o),
.s_axis_fifo_c2c_in_tdata(s_axis_fifo_c2c_in_tdata),
.s_axis_fifo_c2c_in_tlast(s_axis_fifo_c2c_in_tlast),
.s_axis_fifo_c2c_in_tready(s_axis_fifo_c2c_in_tready),
.s_axis_fifo_c2c_in_tvalid(s_axis_fifo_c2c_in_tvalid),
.s_axis_fifo_glink_in_tdata(s_axis_fifo_glink_in_tdata),
.s_axis_fifo_glink_in_tlast(s_axis_fifo_glink_in_tlast),
.s_axis_fifo_glink_in_tready(s_axis_fifo_glink_in_tready),
.s_axis_fifo_glink_in_tvalid(s_axis_fifo_glink_in_tvalid));
endmodule