Update gitignore, add dl814_z7 project

gitignore structure is updated to work with single and multi project situation under a single project directory

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/0513/hdl/lib_pkg_v1_0_rfs.vhd

@@ -0,0 +1,413 @@
+-- Processor Common Library Package
+-------------------------------------------------------------------------------
+--
+-- *************************************************************************
+-- **                                                                     **
+-- ** DISCLAIMER OF LIABILITY                                             **
+-- **                                                                     **
+-- ** This text/file contains proprietary, confidential                   **
+-- ** information of Xilinx, Inc., is distributed under                   **
+-- ** license from Xilinx, Inc., and may be used, copied                  **
+-- ** and/or disclosed only pursuant to the terms of a valid              **
+-- ** license agreement with Xilinx, Inc. Xilinx hereby                   **
+-- ** grants you a license to use this text/file solely for               **
+-- ** design, simulation, implementation and creation of                  **
+-- ** design files limited to Xilinx devices or technologies.             **
+-- ** Use with non-Xilinx devices or technologies is expressly            **
+-- ** prohibited and immediately terminates your license unless           **
+-- ** covered by a separate agreement.                                    **
+-- **                                                                     **
+-- ** Xilinx is providing this design, code, or information               **
+-- ** "as-is" solely for use in developing programs and                   **
+-- ** solutions for Xilinx devices, with no obligation on the             **
+-- ** part of Xilinx to provide support. By providing this design,        **
+-- ** code, or information as one possible implementation of              **
+-- ** this feature, application or standard, Xilinx is making no          **
+-- ** representation that this implementation is free from any            **
+-- ** claims of infringement. You are responsible for obtaining           **
+-- ** any rights you may require for your implementation.                 **
+-- ** Xilinx expressly disclaims any warranty whatsoever with             **
+-- ** respect to the adequacy of the implementation, including            **
+-- ** but not limited to any warranties or representations that this      **
+-- ** implementation is free from claims of infringement, implied         **
+-- ** warranties of merchantability or fitness for a particular           **
+-- ** purpose.                                                            **
+-- **                                                                     **
+-- ** Xilinx products are not intended for use in life support            **
+-- ** appliances, devices, or systems. Use in such applications is        **
+-- ** expressly prohibited.                                               **
+-- **                                                                     **
+-- ** Any modifications that are made to the Source Code are              **
+-- ** done at the user’s sole risk and will be unsupported.               **
+-- ** The Xilinx Support Hotline does not have access to source           **
+-- ** code and therefore cannot answer specific questions related         **
+-- ** to source HDL. The Xilinx Hotline support of original source        **
+-- ** code IP shall only address issues and questions related             **
+-- ** to the standard Netlist version of the core (and thus               **
+-- ** indirectly, the original core source).                              **
+-- **                                                                     **
+-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved.           **
+-- **                                                                     **
+-- ** This copyright and support notice must be retained as part          **
+-- ** of this text at all times.                                          **
+-- **                                                                     **
+-- *************************************************************************
+--
+
+-------------------------------------------------------------------------------
+-- Filename:        lib_pkg.vhd
+--
+-------------------------------------------------------------------------------
+-- Naming Conventions:
+--      active low signals:                     "*_n"
+--      clock signals:                          "clk", "clk_div#", "clk_#x" 
+--      reset signals:                          "rst", "rst_n" 
+--      generics:                               "C_*" 
+--      user defined types:                     "*_TYPE" 
+--      state machine next state:               "*_ns" 
+--      state machine current state:            "*_cs" 
+--      combinatorial signals:                  "*_com" 
+--      pipelined or register delay signals:    "*_d#" 
+--      counter signals:                        "*cnt*"
+--      clock enable signals:                   "*_ce" 
+--      internal version of output port         "*_i"
+--      device pins:                            "*_pin" 
+--      ports:                                  - Names begin with Uppercase 
+--      processes:                              "*_PROCESS" 
+--      component instantiations:               "<ENTITY_>I_<#|FUNC>
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+-- need conversion function to convert reals/integers to std logic vectors
+use ieee.std_logic_arith.conv_std_logic_vector;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+package lib_pkg is
+
+-------------------------------------------------------------------------------
+-- Type Declarations
+-------------------------------------------------------------------------------
+type CHAR_TO_INT_TYPE is array (character) of integer;
+-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
+-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
+
+-------------------------------------------------------------------------------
+-- Function and Procedure Declarations
+-------------------------------------------------------------------------------
+function max2 (num1, num2 : integer) return integer;
+function min2 (num1, num2 : integer) return integer;
+function Addr_Bits(x,y : std_logic_vector) return integer;
+function clog2(x : positive) return natural;
+function pad_power2 ( in_num : integer )  return integer;
+function pad_4 ( in_num : integer )  return integer;
+function log2(x : natural) return integer;
+function pwr(x: integer; y: integer) return integer;
+function String_To_Int(S : string) return integer;
+function itoa (int : integer) return string;
+-------------------------------------------------------------------------------
+-- Constant Declarations
+-------------------------------------------------------------------------------
+-- the RESET_ACTIVE constant should denote the logic level of an active reset
+constant RESET_ACTIVE       : std_logic         := '1'; 
+
+-- table containing strings representing hex characters for conversion to
+-- integers
+constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
+    ('0'     => 0,
+     '1'     => 1,
+     '2'     => 2,
+     '3'     => 3,
+     '4'     => 4,
+     '5'     => 5,
+     '6'     => 6,
+     '7'     => 7,
+     '8'     => 8,
+     '9'     => 9,
+     'A'|'a' => 10,
+     'B'|'b' => 11,
+     'C'|'c' => 12,
+     'D'|'d' => 13,
+     'E'|'e' => 14,
+     'F'|'f' => 15,
+     others  => -1);
+
+ 
+end lib_pkg;
+
+package body lib_pkg is
+-------------------------------------------------------------------------------
+-- Function Definitions
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Function max2
+--
+-- This function returns the greater of two numbers.
+-------------------------------------------------------------------------------
+function max2 (num1, num2 : integer) return integer is
+begin
+    if num1 >= num2 then
+        return num1;
+    else
+        return num2;
+    end if;
+end function max2;
+
+
+-------------------------------------------------------------------------------
+-- Function min2
+--
+-- This function returns the lesser of two numbers.
+-------------------------------------------------------------------------------
+function min2 (num1, num2 : integer) return integer is
+begin
+    if num1 <= num2 then
+        return num1;
+    else
+        return num2;
+    end if;
+end function min2;
+
+
+-------------------------------------------------------------------------------
+-- Function Addr_bits
+--
+-- function to convert an address range (base address and an upper address)
+-- into the number of upper address bits needed for decoding a device
+-- select signal.  will handle slices and big or little endian
+-------------------------------------------------------------------------------
+function Addr_Bits(x,y : std_logic_vector) return integer is
+  variable addr_xor : std_logic_vector(x'range);
+  variable count    : integer := 0;
+begin
+  assert x'length = y'length and (x'ascending xnor y'ascending)
+    report "Addr_Bits: arguments are not the same type"
+    severity ERROR;
+  addr_xor := x xor y;
+  for i in x'range
+  loop
+    if addr_xor(i) = '1' then return count;
+    end if;
+    count := count + 1;
+  end loop;
+  return x'length;
+end Addr_Bits;
+
+
+--------------------------------------------------------------------------------
+-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
+--                  i.e., the least integer greater than or equal to log2(x).
+--------------------------------------------------------------------------------
+function clog2(x : positive) return natural is
+  variable r  : natural := 0;
+  variable rp : natural := 1; -- rp tracks the value 2**r
+begin 
+  while rp < x loop -- Termination condition T: x <= 2**r
+    -- Loop invariant L: 2**(r-1) < x
+    r := r + 1;
+    if rp > integer'high - rp then exit; end if;  -- If doubling rp overflows
+      -- the integer range, the doubled value would exceed x, so safe to exit.
+    rp := rp + rp;
+  end loop;
+  -- L and T  <->  2**(r-1) < x <= 2**r  <->  (r-1) < log2(x) <= r
+  return r; --
+end clog2;
+
+-------------------------------------------------------------------------------
+-- Function pad_power2
+--
+-- This function returns the next power of 2 from the input number. If the 
+-- input number is a power of 2, this function returns the input number.
+--
+-- This function is used to round up the number of masters to the next power
+-- of 2 if the number of masters is not already a power of 2.
+--
+-- Input argument 0, which is not a power of two, is accepted and returns 0.
+-- Input arguments less than 0 are not allowed.
+-------------------------------------------------------------------------------
+-- 
+function pad_power2 (in_num : integer  ) return integer is
+begin         
+    if in_num = 0 then
+        return 0;
+    else
+        return 2**(clog2(in_num));
+    end if;
+end pad_power2;
+
+
+
+
+-------------------------------------------------------------------------------
+-- Function pad_4
+--
+-- This function returns the next multiple of 4 from the input number. If the 
+-- input number is a multiple of 4, this function returns the input number.
+--
+-------------------------------------------------------------------------------
+-- 
+function pad_4 (in_num : integer  ) return integer is
+
+variable out_num     : integer;
+
+begin
+    out_num := (((in_num-1)/4) + 1)*4;
+    return out_num;
+    
+end pad_4;
+
+-------------------------------------------------------------------------------
+-- Function log2 -- returns number of bits needed to encode x choices
+--   x = 0  returns 0
+--   x = 1  returns 0
+--   x = 2  returns 1
+--   x = 4  returns 2, etc.
+-------------------------------------------------------------------------------
+--
+function log2(x : natural) return integer is
+  variable i  : integer := 0; 
+  variable val: integer := 1;
+begin 
+  if x = 0 then return 0;
+  else
+    for j in 0 to 29 loop -- for loop for XST 
+      if val >= x then null; 
+      else
+        i := i+1;
+        val := val*2;
+      end if;
+    end loop;
+  -- Fix per CR520627  XST was ignoring this anyway and printing a  
+  -- Warning in SRP file. This will get rid of the warning and not
+  -- impact simulation.  
+  -- synthesis translate_off
+    assert val >= x
+      report "Function log2 received argument larger" &
+             " than its capability of 2^30. "
+      severity failure;
+  -- synthesis translate_on
+    return i;
+  end if;  
+end function log2; 
+
+
+-------------------------------------------------------------------------------
+-- Function pwr -- x**y
+-- negative numbers not allowed for y
+-------------------------------------------------------------------------------
+
+function pwr(x: integer; y: integer) return integer is
+  variable z : integer := 1;
+begin
+  if y = 0 then return 1; 
+  else
+    for i in 1 to y loop
+      z := z * x;
+    end loop;
+    return z;
+  end if;
+end function pwr;
+
+-------------------------------------------------------------------------------
+-- Function itoa
+-- 
+-- The itoa function converts an integer to a text string.
+-- This function is required since `image doesn't work in Synplicity
+-- Valid input range is -9999 to 9999
+-------------------------------------------------------------------------------
+--  
+  function itoa (int : integer) return string is
+    type table is array (0 to 9) of string (1 to 1);
+    constant LUT     : table :=
+      ("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
+    variable str1            : string(1 to 1);
+    variable str2            : string(1 to 2);
+    variable str3            : string(1 to 3);
+    variable str4            : string(1 to 4);
+    variable str5            : string(1 to 5);
+    variable abs_int         : natural;
+    
+    variable thousands_place : natural;
+    variable hundreds_place  : natural;
+    variable tens_place      : natural;
+    variable ones_place      : natural;
+    variable sign            : integer;
+    
+  begin
+    abs_int := abs(int);
+    if abs_int > int then sign := -1;
+    else sign := 1;
+    end if;
+    thousands_place :=  abs_int/1000;
+    hundreds_place :=  (abs_int-thousands_place*1000)/100;
+    tens_place :=      (abs_int-thousands_place*1000-hundreds_place*100)/10;
+    ones_place :=      
+      (abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
+    
+    if sign>0 then
+      if thousands_place>0 then
+        str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
+                LUT(ones_place);
+        return str4;
+      elsif hundreds_place>0 then 
+        str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
+        return str3;
+      elsif tens_place>0 then
+        str2 := LUT(tens_place) & LUT(ones_place);
+        return str2;
+      else
+        str1 := LUT(ones_place);
+        return str1;
+      end if;
+    else
+      if thousands_place>0 then
+        str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) & 
+          LUT(tens_place) & LUT(ones_place);
+        return str5;
+      elsif hundreds_place>0 then 
+        str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
+        return str4;
+      elsif tens_place>0 then
+        str3 := "-" & LUT(tens_place) & LUT(ones_place);
+        return str3;
+      else
+        str2 := "-" & LUT(ones_place);
+        return str2;
+      end if;
+    end if;  
+  end itoa; 
+  
+  
+
+-----------------------------------------------------------------------------
+-- Function String_To_Int
+--
+-- Converts a string of hex character to an integer
+-- accept negative numbers
+-----------------------------------------------------------------------------
+  function String_To_Int(S : String) return Integer is
+    variable Result : integer := 0;
+    variable Temp   : integer := S'Left;
+    variable Negative : integer := 1;
+  begin
+    for I in S'Left to S'Right loop
+      if (S(I) = '-') then
+        Temp     := 0;
+        Negative := -1;
+      else
+        Temp := STRHEX_TO_INT_TABLE(S(I));
+        if (Temp = -1) then
+          assert false
+            report "Wrong value in String_To_Int conversion " & S(I)
+            severity error;
+        end if;
+      end if;
+      Result := Result * 16 + Temp;
+    end loop;
+    return (Negative * Result);
+  end String_To_Int;
+
+end package body lib_pkg;
+
+

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/1ddd/hdl/verilog/sc_util_v1_0_4_constants.vh

@@ -0,0 +1,123 @@
+`ifndef sc_util_v1_0_4_constants_GLOBAL_CONSTANTS
+`define sc_util_v1_0_4_constants_GLOBAL_CONSTANTS
+parameter integer K_MAX_NUM_BYTES =         128;
+parameter integer K_MAX_BYTE_SIZE =           7;
+parameter integer K_MAX_DATA_WIDTH =        1024;
+parameter integer K_MAX_DATA_SIZE =          10;
+parameter integer K_MIN_NUM_BYTES =           4;
+parameter integer K_MIN_BYTE_SIZE =           2;
+parameter integer K_MIN_DATA_WIDTH =          32;
+parameter integer K_MIN_DATA_SIZE =           5;
+parameter integer K_MAX_NUM_AXI4LITE_BYTES =           8;
+parameter integer K_MAX_AXI4LITE_BYTE_SIZE =           3;
+parameter integer K_MAX_AXI4LITE_DATA_WIDTH =          64;
+parameter integer K_MAX_AXI4LITE_DATA_SIZE =           6;
+parameter integer K_DATA_BITS_PER_BYTE =           9;
+parameter integer K_MAX_BYTE_FACTOR =          16;
+parameter integer K_MAX_BYTE_MAGNITUDE =           5;
+parameter integer K_MAX_ADDR_WIDTH =          64;
+parameter integer K_MAX_ID_WIDTH =          32;
+parameter integer K_MAX_MEP_IDENTIFIER_WIDTH =           8;
+parameter integer K_MAX_USER_WIDTH =        1024;
+parameter integer K_MAX_USER_PAYLD =         512;
+parameter integer K_MAX_NUM_SSC =          16;
+parameter integer K_MAX_SSC_SIZE =           4;
+parameter integer K_MAX_NUM_MSC =          64;
+parameter integer K_MAX_MSC_SIZE =           6;
+parameter integer K_MAX_SWBD_PORTS =          16;
+parameter integer K_MAX_SWBD_SIZE =           4;
+parameter integer K_MAX_CASCADES =          16;
+parameter integer K_MAX_TIERS =           4;
+parameter integer K_MAX_THREADS =          16;
+parameter integer K_MAX_THREAD_SIZE =           4;
+parameter integer K_MAX_NUM_SEG =         256;
+parameter integer K_MAX_SEG_WIDTH =           8;
+parameter integer K_MAX_EP_ROUTE_WIDTH =          64;
+parameter integer K_MAX_SC_ROUTE_WIDTH =          64;
+parameter integer K_MAX_CMD_PTR =           5;
+parameter integer K_MAX_LUTRAM_PTR =           8;
+parameter integer K_MAX_BRAM_PTR =          12;
+parameter integer K_MIN_BRAM_PTR =           9;
+parameter integer K_MAX_SYNC_RATIO =           8;
+parameter integer K_MAX_PIPELINES =           8;
+parameter integer K_LOG_MAX_PIPELINES =           3;
+parameter integer K_MAX_LATENCY =          15;
+parameter integer K_LOG_MAX_LATENCY =           4;
+parameter integer K_AXIS_ARB_TDATA_NUM_BYTES =           2;
+parameter integer K_MAX_USER_BITS_PER_BYTE =           4;
+parameter integer K_MAX_INFO_WIDTH =           1;
+parameter integer K_MAX_OUTSTANDING_REQ =           3;
+parameter integer K_AXI_SIZE_WIDTH =           3;
+parameter integer K_AXI_BURST_WIDTH =           2;
+parameter integer K_AXI_RESP_WIDTH =           2;
+parameter integer K_AXI_LAST_WIDTH =           1;
+parameter integer K_AXI_LEN_WIDTH =           8;
+parameter integer K_AXI_EXCL_LEN_WIDTH =           4;
+parameter integer K_AXI_LOCK_WIDTH =           1;
+parameter integer K_AXI3_LEN_WIDTH =           4;
+parameter integer K_AXI3_LOCK_WIDTH =           2;
+parameter integer K_AXI_PROT_WIDTH =           3;
+parameter integer K_AXI_QOS_WIDTH =           4;
+parameter integer K_AXI_CACHE_WIDTH =           4;
+parameter integer K_MAX_ACCEPTANCE =          256;
+parameter integer K_MAX_FANOUT =         200;
+parameter integer K_MAX_READ_WATERMARK =        4096;
+parameter integer K_MAX_BURST_LENGTH =         256;
+parameter integer CH_R =           0;
+parameter integer CH_W =           1;
+parameter integer CH_AR =           2;
+parameter integer CH_AW =           3;
+parameter integer CH_B =           4;
+parameter integer CLK_DOWN =          -2;
+parameter integer CLK_SYNC_ALIAS =          -1;
+parameter integer CLK_ASYNC =           0;
+parameter integer CLK_SYNC =           1;
+parameter integer CLK_UP =           2;
+parameter integer CLKEN_NONE =           0;
+parameter integer CLKEN_S =           1;
+parameter integer CLKEN_M =           2;
+parameter integer CLKEN_S_AND_M =           3;
+parameter integer ARB_BYPASS =           0;
+parameter integer ARB_ROUNDROBIN =           1;
+parameter integer ARB_SLAVE =           2;
+parameter integer FIFO_LUTRAM =           0;
+parameter integer FIFO_BRAM =           1;
+parameter integer FIFO_NONE =           2;
+parameter integer FIFO_IP_XPM_MEMORY =           0;
+parameter integer FIFO_IP_FG =           1;
+parameter integer FIFO_IP_XPM_FIFO =           2;
+parameter integer K_T_STRUCT_EXCLUSIVE_WIDTH =          11;
+parameter integer K_T_STATIC_ADDR_PAYLD_WIDTH =         102;
+parameter integer K_T_STATIC_RDATA_PAYLD_WIDTH =          17;
+parameter integer K_T_STATIC_WDATA_PAYLD_WIDTH =          15;
+parameter integer K_T_STATIC_BRSP_PAYLD_WIDTH =           2;
+parameter integer K_T_EXCLUSIVE_WIDTH =          43;
+parameter integer K_T_ADDR_AUGMENT_WIDTH =         114;
+parameter integer K_T_DATA_AUGMENT_WIDTH =          14;
+parameter integer K_T_BRSP_AUGMENT_WIDTH =           0;
+parameter integer K_USABLE_T_ADDR_CASCADE_WIDTH =         626;
+parameter integer K_USABLE_T_DATA_CASCADE_WIDTH =         526;
+parameter integer K_USABLE_T_BRSP_CASCADE_WIDTH =         512;
+parameter integer K_T_CASCADE_WIDTH =         627;
+parameter integer K_T_SEG_LEN_WIDTH =           8;
+parameter integer K_USABLE_T_ADDR_SIDEBAND_WIDTH =         699;
+parameter integer K_USABLE_T_DATA_SIDEBAND_WIDTH =         691;
+parameter integer K_USABLE_T_BRSP_SIDEBAND_WIDTH =         691;
+parameter integer K_T_SIDEBAND_WIDTH =         700;
+parameter integer K_USABLE_T_AXPAYLD_WIDTH =         808;
+parameter integer K_USABLE_T_WPAYLD_WIDTH =        1853;
+parameter integer K_USABLE_T_RPAYLD_WIDTH =        1759;
+parameter integer K_USABLE_T_BPAYLD_WIDTH =         734;
+parameter integer K_T_PAYLD_WIDTH =        1854;
+parameter integer K_MAX_PAYLD_WIDTH =        1854;
+parameter integer K_USABLE_T_AXVECTOR_WIDTH =        1145;
+parameter integer K_USABLE_T_WVECTOR_WIDTH =        2177;
+parameter integer K_USABLE_T_RVECTOR_WIDTH =        2083;
+parameter integer K_USABLE_T_BVECTOR_WIDTH =        1058;
+parameter integer K_STATIC_AXVECTOR_WIDTH =          25;
+parameter integer K_STATIC_WVECTOR_WIDTH =           1;
+parameter integer K_STATIC_RVECTOR_WIDTH =           3;
+parameter integer K_STATIC_BVECTOR_WIDTH =           2;
+parameter integer K_T_VECTOR_WIDTH =        2178;
+parameter integer K_MAX_VECTOR_WIDTH =        2178;
+`endif

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/1ddd/hdl/verilog/sc_util_v1_0_4_structs.svh

@@ -0,0 +1,297 @@
+//  (c) Copyright 2016 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  // cascade parameters and typedefs
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  typedef logic [((T_SC_AWUSER_WIDTH == 0) ? 1 : T_SC_AWUSER_WIDTH)-1:0]    t_sc_awuser;
+  typedef logic [((T_SC_ARUSER_WIDTH == 0) ? 1 : T_SC_ARUSER_WIDTH)-1:0]    t_sc_aruser;
+  typedef logic [((T_SC_BUSER_WIDTH ==  0) ? 1 : T_SC_BUSER_WIDTH )-1:0]    t_sc_buser;
+  typedef logic [((T_SC_RUSER_BITS_PER_BYTE == 0) ? 1 : (T_SC_RUSER_BITS_PER_BYTE*(T_SC_RDATA_WIDTH/8)))-1:0] t_sc_ruser;
+  typedef logic [((T_SC_WUSER_BITS_PER_BYTE == 0) ? 1 : (T_SC_WUSER_BITS_PER_BYTE*(T_SC_WDATA_WIDTH/8)))-1:0] t_sc_wuser;
+  typedef logic [T_SC_ADDR_WIDTH-1:0]                     t_sc_addr;
+  typedef logic [T_SC_MSC_ROUTE_WIDTH-1:0]                t_sc_msc_route;
+  typedef logic [T_SC_SSC_ROUTE_WIDTH-1:0]                t_sc_ssc_route;
+  typedef logic [(T_SC_ID_WIDTH==0?1:T_SC_ID_WIDTH)-1:0]  t_sc_id;
+  typedef logic [(T_SC_WUSER_BITS_PER_BYTE+8)-1:0]        t_sc_wuserdata_unit;
+  typedef logic [(T_SC_RUSER_BITS_PER_BYTE+8)-1:0]        t_sc_ruserdata_unit;
+  typedef logic [T_SC_RDATA_WIDTH -1:0]                   t_sc_rdata;
+  typedef logic [T_SC_WDATA_WIDTH-1:0]                    t_sc_wdata;
+  typedef logic [(T_SC_WDATA_WIDTH/8)-1:0]                t_sc_wstrb;
+
+  typedef struct packed {
+    t_sc_wuserdata_unit   userdata;
+    logic                 strb;
+  } t_sc_wdata_unit;
+
+  typedef struct packed {
+    t_sc_ruserdata_unit   userdata;
+  } t_sc_rdata_unit;
+
+  typedef struct packed {
+    t_sc_id                 id;
+    t_axi_len               len;
+    t_axi_size              size;
+  } t_sc_addr_exclusive;
+
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  // payld parameters and typedefs
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  typedef struct packed {
+    t_axi_cache             cache;
+    t_axi_qos               qos;
+    t_axi_prot              prot;
+    t_axi_lock              lock;
+    t_sc_addr               addr;
+    t_sc_id                 id;
+    t_sc_aruser             user;
+    t_max_byte_size         last_offset;
+    t_sc_addr_exclusive     exclusive;
+    t_max_ep_route          ep_route;
+    t_axi_len               seg_len;
+    t_sc_msc_route          sc_route;
+  } t_sc_arpayld;
+
+  typedef struct packed {
+    t_axi_cache             cache;
+    t_axi_qos               qos;
+    t_axi_prot              prot;
+    t_axi_lock              lock;
+    t_sc_addr               addr;
+    t_sc_id                 id;
+    t_sc_awuser             user;
+    t_max_byte_size         last_offset;
+    t_sc_addr_exclusive     exclusive;
+    t_max_ep_route          ep_route;
+    t_axi_len               seg_len;
+    t_sc_msc_route          sc_route;
+  } t_sc_awpayld;
+
+  typedef struct packed {
+    t_sc_wdata_unit[(T_SC_WDATA_WIDTH/8)-1:0] bytes;
+    t_axi_last              last;
+    t_max_byte_size         last_offset;
+    t_max_byte_size         first_offset;
+    t_sc_msc_route          sc_route;
+  } t_sc_wpayld;
+
+  typedef struct packed {
+    t_sc_rdata_unit[(T_SC_RDATA_WIDTH/8)-1:0] bytes;
+    t_axi_last              last;
+    t_axi_resp              resp;
+    t_sc_id                 id;
+    t_max_byte_size         last_offset;
+    t_max_byte_size         first_offset;
+    t_sc_ssc_route          sc_route;
+  } t_sc_rpayld;
+
+  typedef struct packed {
+    t_axi_resp              resp;
+    t_sc_id                 id;
+    t_sc_buser              user;
+    t_sc_ssc_route          sc_route;
+  } t_sc_bpayld;
+
+//synthesis translate_off
+`ifdef MODEL_TECH
+
+  function string sprint_sc_addr_exclusive(
+    input t_sc_addr_exclusive  excl
+  );
+    string str;
+    str = "";
+    str = $sformatf("exclusive.id           = 0x%0x\n%s", excl.id,str);
+    str = $sformatf("exclusive.len          = 0x%0x\n%s", excl.len,str);
+    str = $sformatf("exclusive.size         = 0x%0x\n%s", excl.size,str);
+    return (str);
+  endfunction
+
+  function string sprint_sc_awpayld(
+    input t_sc_awpayld  pay
+  );
+    string str;
+    str = "";
+    str = sprint_sc_addr_exclusive(pay.exclusive);
+    str = $sformatf("ep_route   = 0x%0x\n%s", pay.ep_route,str);
+    str = $sformatf("user       = 0x%0x\n%s", pay.user,str);
+    str = $sformatf("sc_route   = 0x%0x\n%s", pay.sc_route,str);
+    str = $sformatf("seg_len    = 0x%0x\n%s", pay.seg_len,str);
+    str = $sformatf("id         = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("addr       = 0x%0x\n%s", pay.addr,str);
+    str = $sformatf("lock       = 0x%0x\n%s", pay.lock,str);
+    str = $sformatf("prot       = 0x%0x\n%s", pay.prot,str);
+    str = $sformatf("qos        = 0x%0x\n%s", pay.qos,str);
+    str = $sformatf("cache      = 0x%0x\n%s", pay.cache,str);
+    str = $sformatf("AWPAYLD\n%s",str);
+    return (str);
+  endfunction : sprint_sc_awpayld
+
+  function string sprint_sc_arpayld(
+    input t_sc_arpayld  pay
+  );
+    string str;
+    str = "";
+    str = sprint_sc_addr_exclusive(pay.exclusive);
+    str = $sformatf("ep_route   = 0x%0x\n%s", pay.ep_route,str);
+    str = $sformatf("user       = 0x%0x\n%s", pay.user,str);
+    str = $sformatf("sc_route   = 0x%0x\n%s", pay.sc_route,str);
+    str = $sformatf("seg_len    = 0x%0x\n%s", pay.seg_len,str);
+    str = $sformatf("id         = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("addr       = 0x%0x\n%s", pay.addr,str);
+    str = $sformatf("lock       = 0x%0x\n%s", pay.lock,str);
+    str = $sformatf("prot       = 0x%0x\n%s", pay.prot,str);
+    str = $sformatf("qos        = 0x%0x\n%s", pay.qos,str);
+    str = $sformatf("cache      = 0x%0x\n%s", pay.cache,str);
+    str = $sformatf("ARPAYLD\n%s",str);
+    return (str);
+  endfunction : sprint_sc_arpayld
+
+  function string sprint_sc_wpayld(
+    input t_sc_wpayld  pay
+  );
+    string str;
+    string strb;
+    string data;
+    str = "";
+    strb = "";
+    data = "";
+    str = $sformatf("first_offset = 0x%0x\n%s", pay.first_offset,str);
+    str = $sformatf("last_offset  = 0x%0x\n%s", pay.last_offset,str);
+    str = $sformatf("sc_route     = 0x%0x\n%S", pay.sc_route,str);
+    str = $sformatf("last         = 0x%0x\n%s", pay.last,str);
+    for (int i = 0; i < T_SC_WDATA_WIDTH/8;i++) begin
+      data = $sformatf("%0x%s", pay.bytes[i].userdata, data);
+      strb = $sformatf("%0x%s", pay.bytes[i].strb, strb);
+    end
+    str = $sformatf("WPAYLD\n%sdata:%s\nstrb:%d\n",str,data,strb);
+    return (str);
+  endfunction : sprint_sc_wpayld
+
+  function string sprint_sc_rpayld(
+    input t_sc_rpayld  pay
+  );
+    string str;
+    string data;
+    str = "";
+    data = "";
+    str = $sformatf("first_offset = 0x%0x\n%s", pay.first_offset,str);
+    str = $sformatf("last_offset  = 0x%0x\n%s", pay.last_offset,str);
+    str = $sformatf("sc_route     = 0x%0x\n%S", pay.sc_route,str);
+    str = $sformatf("id           = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("resp         = 0x%0x\n%s", pay.resp,str);
+    str = $sformatf("last         = 0x%0x\n%s", pay.last,str);
+    for (int i = 0; i < T_SC_RDATA_WIDTH/8;i++) begin
+      data = $sformatf("%0x%s", pay.bytes[i].userdata, data);
+    end
+    str = $sformatf("RPAYLD\n%sdata:%s\n",str,data);
+    return (str);
+  endfunction : sprint_sc_rpayld
+
+  function string sprint_sc_bpayld(
+    input t_sc_bpayld  pay
+  );
+    string str;
+    str = "";
+    str = $sformatf("user       = 0x%0x\n%s", pay.user,str);
+    str = $sformatf("sc_route   = 0x%0x\n%s", pay.sc_route,str);
+    str = $sformatf("id         = 0x%0x\n%s", pay.id,str);
+    str = $sformatf("resp       = 0x%0x\n%s", pay.resp,str);
+    str = $sformatf("BPAYLD\n%s",str);
+    return (str);
+  endfunction : sprint_sc_bpayld
+`endif
+//synthesis translate_on
+
+
+typedef struct packed {
+  t_axi_cache       cache;
+  t_axi_qos         qos;
+  t_axi_prot        prot;
+  t_axi_lock        lock;
+  t_axi_len         len;
+  t_sc_addr         addr;
+  t_sc_id           id;
+  t_axi_size        size;
+  t_axi_burst       burst;
+  t_sc_awuser       user;
+} t_sc_awvector;
+
+typedef struct packed {
+  t_axi_cache       cache;
+  t_axi_qos         qos;
+  t_axi_prot        prot;
+  t_axi_lock        lock;
+  t_axi_len         len;
+  t_sc_addr         addr;
+  t_sc_id           id;
+  t_axi_size        size;
+  t_axi_burst       burst;
+  t_sc_aruser       user;
+} t_sc_arvector;
+
+typedef struct packed {
+  t_sc_wstrb        strb;
+  t_sc_wdata        data;
+  t_axi_last        last;
+  t_sc_wuser        user;
+} t_sc_wvector;
+
+typedef struct packed {
+  t_sc_rdata        data;
+  t_axi_last        last;
+  t_axi_resp        resp;
+  t_sc_id           id;
+  t_sc_ruser        user;
+} t_sc_rvector;
+
+
+typedef struct packed {
+  t_axi_resp        resp;
+  t_sc_id           id;
+  t_sc_buser        user;
+} t_sc_bvector;

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/442e/hdl/xlconcat_v2_1_vl_rfs.v

@@ -0,0 +1,278 @@
+//------------------------------------------------------------------------
+//--
+//--  Filename      : xlconcat.v
+//--
+//--  Date          : 06/05/12
+//-
+//-  Description   : Verilog description of a concat block.  This
+//-                  block does not use a core.
+//-
+//-----------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module xlconcat_v2_1_3_xlconcat (In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, In10, In11, In12, In13, In14, In15, In16, In17, In18, In19, In20, In21, In22, In23, In24, In25, In26, In27, In28, In29, In30, In31, dout);
+parameter IN0_WIDTH = 1;
+input 	[IN0_WIDTH -1:0] In0;
+parameter IN1_WIDTH = 1;
+input 	[IN1_WIDTH -1:0] In1;
+parameter IN2_WIDTH = 1;
+input 	[IN2_WIDTH -1:0] In2;
+parameter IN3_WIDTH = 1;
+input 	[IN3_WIDTH -1:0] In3;
+parameter IN4_WIDTH = 1;
+input 	[IN4_WIDTH -1:0] In4;
+parameter IN5_WIDTH = 1;
+input 	[IN5_WIDTH -1:0] In5;
+parameter IN6_WIDTH = 1;
+input 	[IN6_WIDTH -1:0] In6;
+parameter IN7_WIDTH = 1;
+input 	[IN7_WIDTH -1:0] In7;
+parameter IN8_WIDTH = 1;
+input 	[IN8_WIDTH -1:0] In8;
+parameter IN9_WIDTH = 1;
+input 	[IN9_WIDTH -1:0] In9;
+parameter IN10_WIDTH = 1;
+input 	[IN10_WIDTH -1:0] In10;
+parameter IN11_WIDTH = 1;
+input 	[IN11_WIDTH -1:0] In11;
+parameter IN12_WIDTH = 1;
+input 	[IN12_WIDTH -1:0] In12;
+parameter IN13_WIDTH = 1;
+input 	[IN13_WIDTH -1:0] In13;
+parameter IN14_WIDTH = 1;
+input 	[IN14_WIDTH -1:0] In14;
+parameter IN15_WIDTH = 1;
+input 	[IN15_WIDTH -1:0] In15;
+parameter IN16_WIDTH = 1;
+input 	[IN16_WIDTH -1:0] In16;
+parameter IN17_WIDTH = 1;
+input 	[IN17_WIDTH -1:0] In17;
+parameter IN18_WIDTH = 1;
+input 	[IN18_WIDTH -1:0] In18;
+parameter IN19_WIDTH = 1;
+input 	[IN19_WIDTH -1:0] In19;
+parameter IN20_WIDTH = 1;
+input 	[IN20_WIDTH -1:0] In20;
+parameter IN21_WIDTH = 1;
+input 	[IN21_WIDTH -1:0] In21;
+parameter IN22_WIDTH = 1;
+input 	[IN22_WIDTH -1:0] In22;
+parameter IN23_WIDTH = 1;
+input 	[IN23_WIDTH -1:0] In23;
+parameter IN24_WIDTH = 1;
+input 	[IN24_WIDTH -1:0] In24;
+parameter IN25_WIDTH = 1;
+input 	[IN25_WIDTH -1:0] In25;
+parameter IN26_WIDTH = 1;
+input 	[IN26_WIDTH -1:0] In26;
+parameter IN27_WIDTH = 1;
+input 	[IN27_WIDTH -1:0] In27;
+parameter IN28_WIDTH = 1;
+input 	[IN28_WIDTH -1:0] In28;
+parameter IN29_WIDTH = 1;
+input 	[IN29_WIDTH -1:0] In29;
+parameter IN30_WIDTH = 1;
+input 	[IN30_WIDTH -1:0] In30;
+parameter IN31_WIDTH = 1;
+input 	[IN31_WIDTH -1:0] In31;
+parameter dout_width = 2;
+output [dout_width-1:0] dout;
+parameter NUM_PORTS =2;
+
+
+generate if (NUM_PORTS == 1)
+begin : C_NUM_1
+    assign dout = In0; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 2)
+begin : C_NUM_2
+    assign dout = {In1,In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 3)
+begin:C_NUM_3
+	assign dout = {In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 4)
+begin:C_NUM_4
+    assign dout = {In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 5)
+begin:C_NUM_5
+    assign dout = {In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 6)
+begin:C_NUM_6
+    assign dout = {In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 7)
+begin:C_NUM_7
+    assign dout = {In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 8)
+begin:C_NUM_8
+    assign dout = {In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 9)
+begin:C_NUM_9
+    assign dout = {In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 10)
+begin:C_NUM_10
+    assign dout = {In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 11)
+begin:C_NUM_11
+    assign dout = {In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 12)
+begin:C_NUM_12
+    assign dout = {In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 13)
+begin:C_NUM_13
+    assign dout = {In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 14)
+begin:C_NUM_14
+    assign dout = {In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 15)
+begin:C_NUM_15
+    assign dout = {In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 16)
+begin:C_NUM_16
+    assign dout = {In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 17)
+begin:C_NUM_17
+    assign dout = {In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 18)
+begin:C_NUM_18
+    assign dout = {In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 19)
+begin:C_NUM_19
+    assign dout = {In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 20)
+begin:C_NUM_20
+    assign dout = {In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 21)
+begin:C_NUM_21
+    assign dout = {In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 22)
+begin:C_NUM_22
+    assign dout = {In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 23)
+begin:C_NUM_23
+    assign dout = {In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 24)
+begin:C_NUM_24
+    assign dout = {In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 25)
+begin:C_NUM_25
+    assign dout = {In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 26)
+begin:C_NUM_26
+    assign dout = {In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 27)
+begin:C_NUM_27
+    assign dout = {In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 28)
+begin:C_NUM_28
+    assign dout = {In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 29)
+begin:C_NUM_29
+    assign dout = {In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 30)
+begin:C_NUM_30
+    assign dout = {In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 31)
+begin:C_NUM_31
+    assign dout = {In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+generate if (NUM_PORTS == 32)
+begin:C_NUM_32
+    assign dout = {In31, In30, In29, In28, In27, In26, In25, In24, In23, In22, In21, In20, In19, In18, In17, In16, In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0}; 	
+end
+endgenerate
+
+endmodule
+
+

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/66e7/hdl/xlconstant_v1_1_vl_rfs.v

@@ -0,0 +1,31 @@
+//------------------------------------------------------------------------
+//--
+//--  Filename      : xlconstant.v
+//--
+//--  Date          : 06/05/12
+//--
+//--  Description   : VERILOG description of a constant block.  This
+//--                  block does not use a core.
+//--
+//------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------
+//--
+//--  Module        : xlconstant
+//--
+//--  Architecture  : behavior
+//--
+//--  Description   : Top level VERILOG description of constant block
+//--
+//------------------------------------------------------------------------
+`timescale 1ps/1ps
+module xlconstant_v1_1_6_xlconstant (dout);
+	parameter CONST_VAL = 1;
+	parameter CONST_WIDTH = 1;
+	output [CONST_WIDTH-1:0] dout;
+
+	assign dout = CONST_VAL;
+endmodule
+
+

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/7005/hdl/sc_sc2axi_v1_0_vl_rfs.sv

@@ -0,0 +1,348 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+IM4zMLEYn+Zw+WcIErZjwTT77IBisEPapewS+yLn3wkx7V3W8OjF6YahFQqxFVZNGUZdnDayeshZ
+LUycMK2y5g==
+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+Eu2QkoFdoBW80uf+ugFHzBsXwOb//rbSxQSyC7dVL9KhP257iEAgeqSlPWEfiubE4cc2IOwNs5GP
+am98dYH7hBvdPr1pKdkZgGOqk7JSJBFwo8Lte4pPLLrBkdFgkVSy14Jk9Wto7G8MCeAGrOIRLidr
+TDD4jkCyFX+IFcZ4Vn0=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+0R263be52jtxEuz/H8OAcbNT9ZujcMSFXXkzWNuknbgfXxJQPRBNfGAYAHTypmE1BQxpTGN67vjk
+WoMQ74CkCu70v11PmPKx2UCAn0mQNuMGy/oDtLh6G8IMrHNaIPpkJFLfhWWBq4MLlcIyVbDj4FL3
+WWPgCdpFqR39sP8cjnnq06tRw+t46gCHMhV1NDoXZ5dRgpn66sRyuwpNtegYJT8N9LYslz9cVJ5U
+Z1RHEdgcy4168Ry4xmwlbc9NFQVa20Zp3CA+kWokpsN1ODFbzAVTLzORx2XxnOGKwDFUPWVgOfaQ
+wBz0MLCxfqzkamJuKTURXPJkV8HVeG8o/BI99w==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+aD5S1JukDG7C3gZRNVa19WsulNQSnMLjUF1nkyWlcpEejaY4XFvsM7/NjY7JXp2VB/LYrrqCJ0qZ
+Cn6cz/JYIB6KsK/8OaQblWh6I308p5My6llMaAR1p8s9q8dOyOIyCs98SwH628qTln0FO1tjkIuP
+Dy4Gky1IJAMWqShPDZjdhwOikHClI5WXlmutIKYpob1xR871LbMrFa96vE+Ot6/qbHxvS1nt9Vgm
+mPEofNH6Jv4R0TH6XcOWlcCmgfv4bKrZ85N78fN1eMj30japplfXURtBIeHuAvu2G6uVRIOuYYCs
+Nb2ePWRimwTgj4sp9oIEeMYR33b2jJ+HzzVMTA==
+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+e9cey9l4df2vpUhHQjDkWCS0QdMaNFCeDbtps1wDbQEpjCgh7/bZoNNjHLxuDnJKwbDsh6CxVFq5
+JM+5YL19wHkWonvity8YnCXHdzH1BhvciCgQis0v7sjglTrH7VVaAWZ4H9FJBYII4QVMCTZAhVrU
+mbKs3AP7p33a+Wlaikous+oPUp53xhcCNEy4hP8XBrWfMYssK2REyFK/pEX+8CueRotzbTIcG0xi
+HR2fzEKD2NnmMyHL4Ub5lcAnR88O35EhAMQJw9VF4keO49SQQV8LRtpfai6Zrg83v0m56jIJ7f5a
+7KWydLXJZJq7jduDreUkgR2DTPwuzTpJMt5Mrg==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+dVuZV5zwKReJLApF9/r5+V+1GGVdoAyVkyGLijtpsVDMfW90oE3ZwknkHGQ61mG+n0+a31OUxfLd
+50bcIy+YCFeseIEjkeTJqQlkIljY9Mgqf+RPV0U3TIb99eF2ngIc8hEHZ9h5w4E1SK9kHps7R1mW
+O9ovDi/WfGueUcvJgHU=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+Loh2i5EmiONTBonBVlrE9HyptI/Sw9oeHm0d6Hux1Amu13wu9yXRzYrhv8bUJFpZk75MtC/ugdlR
+DsNerEqYmQoKtV4iDn8Uzxb4SFnl8+3zqrFF7GwNHI5g+El2NewjRAhW57trpgi8fiD23jeeGQ0h
+uvR5RuZaAL/1f6WZDFa4ng0TCJXcpSN4Q+26aNNQVmyLgX02BlMVIiAX2SXTbvNzwCKINVO6jCOT
+CjBCLQSRh1zAKbcH6v8UuBUh7RPH09/3ytJ/zoLpfAFrV317bDbKtM3FRzJBD8vaYW/jPrVEc7i6
+gidTY8SHjPqOvqc4cl/XBxG+Fek4jZ0XXkxZcg==
+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16160)
+`pragma protect data_block
+fBHcoUdHeH3TIUr8j1LVLTZFjARTlwOOHPpQh4FAIMurlduil0qmjRE1t2iyOEy6bbWuwRFuYJIc
++uwlBNJBUCtqwJp1dw+JLKUpuLO/wFY3He2VjNZvedhuyhuVz98n9hN2s/9rCGUaVJpQLve5SuFM
+fwVngfD4A3vK6AKyNEIEfMe6EQ0VyC8WcQNOY0g7gDCd9st3XBZVH40nlJE2DTKOZr6+liKsQ3et
+p8i6jhSOoSx/ugydKcbaI8nguiwWJU/Qqmrcaplun6wWgL5AQcjm+v22IVERGKj6lqpEAVAshN49
+6/Db6+3kgLuu8gxJ/GS7vNShhAhjXCEB7NY0M3fGqdE7p6CL0A0vfOLMyBD93ivNCYRto7tFDhaj
+TZIjuFPh7e5drEYt/8grU5yGrPq40D7ZMUBarjSAt5AMFqc/M4302yXPVGTC5rs8uRpXg5+CN2xW
+lVYhoEa1hSm1BDYXLH8oBra/oOfiNsV85F9GeAUJKQ3nh95gE0SWjzJwQ3h3uQp6wqpexidoeiNr
+53oziSxQ7VJVHQiiebDKEvfEJwmO3SmwV5Boa9Vs9owr/EhOUlv3qWfWJb2B6riv83bFv+OPNToL
+ZuMeeskNEIM6WiOgdHaYvc8hQsSEBQlgxL8xjOjZZ9N7M/+XVcuk5E7+pONLAOjz/eW9Wqh5k8O7
+mPyxMsPt1rnp60apxgUOHZFNK+ha7z2ASjzu+0RAgWDwbxk4LvxWMNACvgxuabgD/cjUBhJ9exnZ
+XTZwNS7esL28wTJumc7VBcWKWX5rJHlfzM7Ui3VtKLawG5zjHaUg8LmwxqzZGgUMzHUt/BSTN/Mx
+au6F9QCNXGl0tzh9JokvEIj+s75v4uJvoAMEb8ueCmXQfcT4sCDs6Dv94694V0oQuTGlgwomz+tv
+LYm8vRsDZZkSBuUgB0iQO2omsI/t3R/atdPWYBBfxoWS5RsjgR5faIj5D2HEyv4blEOKdLYLFBXD
+8hnFYbWVf1jOHKF9rWOlr1uDMSbyYZlAPoVdFgxuHpkCoQ5jAv5ScgMIaQipokjA54dB6CrwOe+P
+OcM+ak/Uj61D5YbewigVeB+UH6BNA0HxI9iTOPJjxSXSBNazk2PNEkqwe0vesDtzfVv5R9Q4+lH8
+ajXSdSiOoVFsZRCzUDp9llz8FnuH0LmR8mjvTuWSXXLkAN85NIuUYkQ2GNqiWEYN7T7rtBljwHd1
+v8OxmRJn1LS5RiPYt/xqjm3KhfocL0oBTsXd1gNLyWGfplTq8IAmvs6BcmC7tqH/Tp+oCMCqtdEX
+bBtnh+9kZQhpPb1v7hDgE/ts3dlIy3XUOcENdX6vQir6Ve+WhwYHE254lyWkja/6W/e7nwL2VrW7
+6sl24LK3p+68CHk+g7rKDc0r+mKNVylIwzX5KnaphvOl/QYcuw8T4Ot5Z7KNdF98mtu8rePY7ptT
+VUBwgVofRJJRjafLKswRdxkvEuN2A9alQihWPSPKE6XnF/YDQ+5IcV2AtHJwiJB/I1QxJv8i0iAn
+kAhCizEN+B0KCW7RE+G8B+ULguvY9dmoVVvpQ7V5Z/qcxKcdY0ft9TNbQFH1gExgdXXnHGCN1ycJ
+PpIGVE3YR2eh5spSaLbX9xEZJ1UtR4gP39Kk2/RzZSm5wKx0GAH/Gr1bOe5AEsr7XLHz1LIVYnuX
+VGhIRjR45qwmSKYgcSxHm3/ZSslCKS8+tgAh+i7qA7FHlISt39kaJhB+gWWiQDq9hoWR9ac1nLn/
+lCSWpSz2dTJqvEKf5vVz6/6soKLxmrVtcThz6br2W7CGxzl170ztrm2TaFV3//c7G9SMcKER+I/z
+FAv2tRBfTs97w97u4DhY+a0+2bsZy2U1eOECtVmAQLzXDvZSozTh/D/h+WYh91KhvOy3Ns52T0OU
+Qxq+J1wPbkFZNcfd6DkYo+VaMoiXo8okVALS9Td4oJZFArLn6DBhXCB/f2gDT8Oylfq5Md5MXCJ3
+rR+n2emkF7jhsUTU+8ax+R/AcPHCArHYiURNrOdHmQRF6HxgBdVPv64FeC4as3EDIhyfK5bRr86e
++Xx6XHYNEJ/pn8fAc72U0FlWjODFN7anEORipLNDhBQtHFlz4Wsb/+kcF/b/mgK/Mof7YNY94quo
+h2SouaCws05WA8emv1PBOwh/TymYldy7rnHL6Kl0UbiJmPU74LNXVdwGl/rd5y8SVfM/W1EdDL6+
+NFhrkdLjlqPhgF/dVWpbivck0nxWiv7gMJ4bnL4dqwJdG11dxNLyepGTezFiTWn9DyN3fF+Ovgqm
+/ea+pkjzbxYSR4pLL76FRBFlm81IwTAivi4DzvNb8P2l/kpD1oE3YiHLUI1GH2BXY7UQ0R/J9y81
+y8H8VcRv6mad2NkILUBD6vUg8/7XJGurMwWv2NYOncKz2cibk3wYnROuq9jpnvFyGx5b5UA2ZKKb
+JQkbIUN4oqBo7BBqjjtwn8sHkQeb6MHE6Fyc1yZ0mCodK/RjnNUNwJycVUTZLv5vGTqtIWbyADF3
+6w6mn07gDSksmuTqALz5Mn1Ku6D+amHLi5TqN+4wBUlwh7v/sa/6yzOWhXzcsERTw+nUOzVC/Gxs
+8aWwAk+6Fz1CI10YZmKi7Sw1BaoYrnBoGXRKL/C90DMWHqn+BVbwEovmzQZXvaRYMjA+fDCQn/AV
+PuEdnLthL4IKD369GWYpQ/45jI5yeNIcvElRKmLVJ7keFq0+0OVJw269x+2GZungiTsKRfWbMnuS
+iqsNW7xMzy70fMp1c0hgYudos9p2maN9ecRy+u7Or8ZKJSaE68RlOnHm8mPiJ4vZ4dANZCj16Xmk
+okd41l76Xtw1jINtgRaryXrYiPhesoe90nn5QugNZNgYJ/gFRTBQMrcy/7vg08w/n7S9cesoJ/VD
+oCAC4xMXXm+WDFc27waM8IOcyCph+vHyqBST58UvOrkQp8WPtml0FNvtDENXSzm+4GxIXRAzBPJd
+oxTMWrq9nm3F8mhVu702UpAhDAD7ZmkfrkG4z9YQ68/sj4bj/nqwN2NQpCu8j2peloZWeJ60FrAl
+qMxrxS6Sd61u/unUInprb9pt9KqB8DXIHPWjEgnwehBkFNjrhQUDymk4yYhB1trGIWtAH7XdIUif
+qhT0XzgJl7G/U2adoaEGxoCcEjD4unfr/GbpXGorxI61kUfHhLvqQn67+CohcJlzwqBPJkgmi2oS
+MBux72yEJ1++4soGrggyPR9X0iLFy+0uiTJowxBWkMdP0a2zvkXaOSyEp3doX8p89bnAmFgXZi3l
+2WjRR368nr5+8U+IPDstvTmCxLGOfI0YvfL7lSSP1mZmn0raAdpKXKM3wR5dEnA+UGcCrXU46koc
+oTBvZjvQn2KimS+wVzPCpAcLWuhaAiJ0Hc3tZdW3DR0wu5XyBwce2tH3w7WxiyeCLDxXgegUwyO+
+GTfT2WXMOR29clpYEySVmDbrVd6DeQzfj187MlC8t3K7ckeVdm/i2hpMP+KHQWVLX/vuyf0ELAAA
+gS9STcXPcb0ijSOqXGo2rOz5m3ZuCBR9rXkYWQlWglfOypr8jpF4QFHeoC1u5XIHfDQxnooC4Gda
+hSuDcaaLnrk8q7fpUjNhI9tfrLA/1V2Ur+qAFdRukRnQ8oQDLDCVqf/FsSsNvPHKt2IlFSJXZHzN
+V7H5avKTSjNnMtrO50NVmyrnyE/Ag/b4mOYMom0VkYVVpfHFOcILuVve9sUD5ECSC3TEh7vBJjai
+mvb/kkI/lu6ZUf2x7OK9dPfuD9wjg56Wyy2WYQw0napxAhslFbwOC3S1bl3+rJKj/Qa9C0tUX/fB
+vNpuH6HZ26cCm5qW+tmMv6pvm4fJB1gcqLjEIFb4TX6RM+2TVnV7zsgsImtI5RRBSnHZ8MHCmEn1
+JI7UbBuuBVmlHOyxyf7lket+IbSao5S96OMo79v4v28injzTJBpsYS3fvIPN2n8EdeX8Pnp6SckM
+4/NYRHZn9+TMJ9SyJTdD7obMhCP/FEjmcNMzGz/odtnxfPntTewa3XovgeNk4GHT8SZ+di/L7q1R
+AWvQ9DN1zgasun4lV6aRuaECdp+kbKZlIVUkwwIIXjninNaMxcYdo/TKhBdSgiE6zJNzQ3A6LECp
+hWJz6DDvdSgW2NMueV4NQy2XlwvrYqH+D6a9OUaH6Uq9b1H+5TvhBKRGy7wIGgXHVosF8z1tpwJB
+F3mZaEx8QhkIcsB8wolWszWrSFiJl4F5FmbY1eQkBtJghNthV2ISIH+EhDOm6z2daqYm6SQN1vYt
+wzBvBePCWOGlsMf5PzEaSaE2O3f665zDUuUWnQjjeElVduDsXL62TYo8IEDc1S04Vn7f/QkmZ9Be
+qeqSs4550cbfXXw+cbq0+MO7vAufBQkl63F4H3QmAoNgL6p0CMdz1ErV6EaAHktgIW0c46hHeWxt
+jy/P/NMChnMJHWxVX+P2xF2nQ4KVHj/9F94yVTJEuReMpCSxMTEW3NuH2CCl5BXzNcQtDOhSqPU9
+Da1yu311F6w6yuPa+opZkib9/sC3oTqokqoGtet3kPVnL14SWCq52gJbjSXp85/rLIEQbcHVjcXp
+xV0sEF8R+0QwFgtlpnEEMZxne4oa++w7oXY/DOkyjSORtD7JwZLAgJ67p1OlP134GM9+w8wGW3Tl
+b6y2vyEPqEnGPB6uEoUIgKkkne1KqPXgFKvvMmVDP/4C3uAsgWxjVBpT275UBeKkyUk2oXu8u/dG
+7KYqOn4ZylMe2G3zJSICUkgQV7skt6fxBhwzwR3lDpuMJN+aEstvn4AgnJ3FWnrSvp9rTJ2bjLOa
+3qmDCsP4FHbqlnXnpQH1S5PPKSYgZp8xWqfWTJclXpMT1Tz4VtWa1jkTZmU5yHp6lqq7Qsc4z4o7
+xHW6rvTew0caWawApIYQgLfDpHqryt60Dt5z+HSraXRwcm68X1SKrWqqKcUDCWM7WvtCOWZJhLwu
+IFpW+fUMj3jbNIV9DaBiqGYoYiDALXK78fksqB+qO9JhLBt9Qapi+sLQ2XaGipf31gPA7jk3xuEg
+bS/KiWGHsaV3YLbHbO9weF+smhWHsoVLHP0F06CFW42N9XtAScYq7U5UccN63LYgk98YBXVQFq7N
+Tohgoigk11VyZU2r6jt6WTt69eqKFNWh2k6J5GLeHfkqehop2+pa7kvMcGTtnphJNGtqXuT+tCTv
+vDaTxj609nt/Nh4IofUsuyDuJyOi2LTqN0Hc8sqvtq9UeqrufXk0TUyXQ/aQbQrzZAHcf63X28Tm
+cw/BlNhMku2ahXtM0rH0KSxtBUuKZ759Mg+9tQjCxlzbhbifAM++ldTGGF+r9qVf+SsdSPpzpSHY
+4aZ5W2ulhjGBXHrZbMbn75ldYGnFfWQeV4Jk4BdukD1UfLcCaSydWa8ffBzxACNTewI1jhY26IWD
+JHMbZ6CckgZr9zz1SGMutLjcXaFKjg1XgZuQtLgk5bzLq2dGDF9mcZGEyxL+mW4QuyELZU7sQLNf
+3hKk3QrjfOFV4L/XC5yh+pYw/rMdSqn4SQ62dK9bDc6GLfK0SnYDiw8qe2lngDzq6R/mXLbJsIyk
+blT4pQndK4loeNRIadUTmG4tXtGD/jk3RpKYy9RYHvysoXRGhjR7glvXr+Wkow96PM81uUfBf6SP
+TcADYcF3is6JSSHctmtkSgw2e6WlEfjhd9wyv0fAHO7NUAQATgBZFCNv/e8KCmVXXNUoGf5vZgPg
+m1ajTrooE3fNiYZE7tkg6oiH596u7UsTq+wa1CErMGoCa8e0+2JmIItH9/uTdO7346KP/LXbkG1u
+IZU43Mth4Nn5iKaYx/g2f3n3xea8RiGgn6XeHzUl4PyQz+vblNGPrxzXf7Q/Nq3QIn+pcPZ3MXNp
+gXB/yyhTpdft1CISqqjo/Z8PoPtwJlAwj3TOIAN8Nbr1GfLGqKrZMK6vTLwf7TVlqWfsPgf20NFJ
+yxrqvFgGKSnVXJlZ5FApv/5d2Y557UwdxZM9QPNI6lkv4hbxri/p+UH9agpTGlRzh6Vp3IYbZDl5
+yboKtIOlR3wMT/Weu761B5gA8bHquPjH+2fBR5kUYde3acgPDRzA4WwZ0rGcklibWEzL0yoME1xX
+Hpa5EpOlmvbjGATh+GMO2gT71VtI73BEDudocBM4QXS9MXEpZC1fRE8vfpH0PosQSiEqf9yNSz3V
+k0ulYHzXeT2dvmwTZs03myCWhmMEj6J9VCxJyG59oM5ds9b9sKFtbokv9WqHu4AemQiNdad4y1BD
+Bx6BYh3j/GJDZ9FIRlEQ7Sx/nGTZSCIn43al+KSPO+abbA9FTW7hP9FBFsdChMlFTVlelHTtmn0v
+NEPphB4ow3sxUyDXLASjbpJpz1+wMNIp2uKfQeA5+siFu0ZcbipCPNNqvWL1TjtIcywFZ0dICVfu
+35fG+s8knTnqWH2w/1iY95A9cDsXVypm34yjnEW90Uc2aCPOb06aBRZGDPPb4l5KDGvHWVcqLHOh
+8n/K8qsL6NJpo7rfEVU+pvtflrKZntTBkkjXD0xzzoDEo6KWKVK9rcjdwa0oLHWGrIEqYf8T+OaG
+HhpHgRiqEAbD5YOr5zYsdrWOYbgd6NGK1cDydPRPeLCxC9RPQ1DVdomgeH5h7U9Vz4jI7uU2mqbr
+7PDzJlrkKtXQIUjZy4dkE6mPXxQunFqg55nmXzh8/q80IQv8KT7Z4uwZqNz1jCjiN9pHjs4IZuzA
+8tKFAdqtzlhInDvteOSrOVwE+HzgCgrxxfaVr8AVTuqNsBfvIvaTxWPPw3SdVZOEk/Yf4dRzeUL6
+BoJB8mrbbAdzpkQ04+qAuE9l2+Rc2ah0j9MTrLQRL23G7FSxV2ntOCsdAQzoEHwumYcvSX8paY4H
+Ea1PCwcWgpELACVScie9trWtqzUeNfatjn92F3g7aPXBEstRAQniLB4/KMWb/MM/s59eTWCbn1Ij
+K1R0u71llEbilUy52DYZSirDjq/TvHbZGEzY73Cw2x5RZqkWN1afab5XUwp1ALsiOQUSZjJvDn/m
+C1JvhwLiBD8NREZ5+/ETVUEwm5XNB0r1p5yMBxf7diYD7xycZmC7Wn83gu91NXvKrwNZMiL7xKJu
+izdn8kwswZPxKiB/FCKIe2NHWN6LQozo2BSb1+TWVwpqqSVl2x6D171d4AvG6Bxee3oikCksh/MC
+TWcEeHAMlfhm/MKEd5gWn8en0ryHTzI5c89H6iEBAz1ZmEGwelssjsp0zfA9vxBuf9iw13oVVVTv
+9Q5u00Bo7qyU0ch5k87shBkjSPDAVtfUHO2SKugEixgbkbM15b/RJyBJUZmSM3k/6EAZ3kzeGF2w
+TBUg0bXO/EhGMycAIYcgU/3J/7kE2d43ZBF860vWo5frT5iTZzPc54qsLbGyUDKnUNU7vq+bXhQH
+3/3wUScXCUH40fVCxYW3pb26wk/TTTEYOyBRMbTevUU1MFZihFPYPidl85Oi6vNnqqcTIPVRLuBd
+eklRoBOYMi7+OqToE5lRu6ChOWBRpyyqG2bAMFnVpBUd1BNeao+O/zBkeXGGG3l16AHvfcY3Vy/w
+21F57/6sjUtc6uL8T82U4Lz5rA7mCBRKutK7UisMqz1/nv99gRk0kRKUuRKjtJo5HFu9YSC823ov
+K56v0bBbVDsUOfbH3AEfomx8OO4va+acbwleuUzBWDMnqlfoPfCxeH4psniedElfTy/CcGTYWIFm
+1O9lk8EzTXz6jaow1ktdxxDKux2kCKvtfl6LiAFiAzoYPpAd3w9Nu0079kvh69xj7Uqpf32gtXX3
+Yqime15y48akEULS6SyFLQcGBPjafRRDajOwbjZ9XSEbz2kinQcCNiaVkCmHc95oG9byf5NPrBhh
+xhtq4MowQY1qbquHeyfFgfufCoMlROiS81aLLj0/ESUl6Amt6+6Rks0xxrwAg8DJzaHqtC52KBS8
++pG34ckcavU9FEXn2W4m6mNK4L4JNd9P+/f7tnE+Y5Kp5Qch4yBsYQ3c47zbTZTGSuqvPIjN1wWC
+aAtNSpgOfk9sVReWBkBblOhr0UejZJ/2Zn4qUoBtXh7zq2/PAxYJG5K6e02qsdGNzAYZf2NFxliA
+7Yw0cF+DS7xlzxq7yZbg5eYndrnIgWxnk1FuRZkYNGCRXzyTQl2aizNfyHMrWsElj9WrjFhbVLsv
+ilbz3n8YDuOsRoV1FtNteNujG1uxD2Y4TH948SjqV2LwttVlLNJEyAnHHOWBMNQPv1JuilSSuROA
+cJmbL05FdSAOkD8UzGdzSwfGfNdqrS0OJD3qqRDL1hoUy1R2INd9Xr06ZSa1sPypZDbjmnMRYbh3
+J608ptJFcwS5dugInNnW6Ra6rs6wSMtZ3Koa6X6abMYWX2AhCfpQv8zdqNqvxoJ5YYNkjksrK5DK
+/7ftBX1ud7umQ24fWfwb66Eq/i4offJqTeAdRu1Wf/tQtfrofyyxWgYoQWk98IQjaJ6iUVfa1aIr
+avEb5lFPMv5CgIOYJTWfliLXwhGMRTUldMiWCt1EqjlxX8rXuVvZsPzIbf7G02UDCZFbFp4rNCsb
+FbLcJiZoC3vzJ0cnbO+PixS2hvB6o7pr7fV5+b5jjzN7iGHpXuitdSUPte7BlNniGZjIa3Cnjfrd
+FaKHJzvVRE+rcb9MisRfH3cZYEWjLAMRhx1lJidXh/vYQSyg5C0BJ6FHyHoFu5jP9tJnTSi3Kqxi
+iWQVwVAlTfV6aFEW2D9iK2cwP7b835hfYqYgrVJtZ66UOIn0COQ6nPu0EJOmKBmEe1Cnu0SiNPPF
+BCbKeOffrcms4L7MTAaZqxxT1g+5nm4DHA2ss2qOFFN/LYgdH70uQg/zivdwM9KEQ3iOY4RI6UDD
+99sgwKE0L3xN4TGl7liE8wjBh7Hpt8Ednp0oisktPp05XocgXrb0tAHtPouIA7rgOkGBBWFQTMNR
+tIwxHDlU50NQJcKOriRMlawFW/AtN9l86o7pA7d1MI7/npiQrojVwNtuKFYYWLz9avS1ffGr/jyj
+gcedNWps3Sb9Kx4cNfacuXpVKJJz9lFq2JrObcmMTTYzyouZdp987ZUnE8xijhYE3rjjkhH6zsXL
+4q7UDDwUtTDRnD6KLXJbr4a8CSUJQ+iCad1OmHgOWXYr8E725Xrf6L0JSBHxvVgy5Ntij5vAZb22
+oqGyX7xHxXU5ZXaTcvUzlt5h/ZxlIgvgooYq7UqefA28ALxH0luYrafUwD+H/+al3qAsdgGIkQOo
+xhHvh3NE+4Dgwy95dOYNkW64EAR87mksm0h6jPZB5ctMu7Yz3fj7dKY/Hvgt1LwPwQJNOC57Od7s
+t1uNMrlxN7HbltZWef2iwP0COuiZeIGIEaDBBeajPgQjuiwrghSj3yNN5XbcYnUStOK5+IAQtqrA
+GQu2KdNhiKetHhoCcx1SgupPCB8PbQuJJkCJ01d8vZLobn6XC5tbDA4qPwiUSVW1EMPgR0gqoo2o
+Vpr58T7kbZE2SkgQ/CG7TgIQXix3RcUkQEwiMDZptDrM4jMtz2LylPyjyXPVKRflYWvPoK+vDdb7
+cCpzDicDbdcTRBFZ03tHEn23xZtxrKESX3GunaTErPMBMj6eVnlbHxbDaXX85oqRlR4XoQkL7OQu
+H49qawj+h3Eo2BUFSu4l+kw1/5QAPtb9AkSXwwNgSbwKgHRc3k4sPJ67lFobo2/XrpfKwgEAJZJv
+CGEkKrEtCyoxLEI5lJvUo+8T871P5lmZ4jADxisNkWxJthS3g18mVHVPpL81Cs5VNKmWtSpgVCeq
+DjcZpxmvhXnhsfiBMVrBiZm64dmem4pHDX5MuVrRgYds44N/PlqQR1qVonW6GOhGT3tpoAD5PcP7
+t/RyCzDXmiHuLm6KOwcnWCDlLgchcvxFbp13iIexoZm8wd7wghFIt1OcHXxXmq4n7TbEgnenAC2+
+XZ/1mIC+8SDR8u5dN6xJfzdvoZtevzaY7WXklzWoMOOUIYd9yRYL75sEoMAZZoBAlC1Lk//tP8FF
+rsX/P02x0+u8Hk/Dkcf1bM9lmaWNy1v/eWZpFdANZB87HkxUF6qalZjpsaU4hvNsRXZinGWgAfbV
+shVWPHCyKNNbzUKslPuE7Q6ww1ZaO5u1HYXy0+gRLfjKUTHORWEaCzNe25RsjwJBFcsUGVhCEtq/
+zBdxwF5tFiIaKcf0Ps97Gx4/dmjEq5EDn7yNoOblv1QLEpwZtBlJmMmS3/QhK6kJV4kdvTT3r19d
+lxC1PPl8O6XQE4JFLqqsj+Ajb/8ZYGU1k2J0flOM9ekz//gBwSOwLebiQfKd/rDeENAT9HDUtpGp
+MDfRafuynlEm4uRr3J/hIAT+AZweDOqtgFIVDjL/ujmN6uLoseXyLk4Qpmi7OGTSDi5b0IGrH9tL
+UG8Jwnh9wtsTryv9JkoQgMWK+EaWeJO8/ZSt6u2wsWewKvRE0k20xCf08eChf3kzR82SswdEaQST
+HC4O1QT4//hs75YP7f0uveK1bRb+J1Fi6X1Rsvpw+Raxi9bIqqhZQDeEvbQD5IoI5hINiGDqN/5z
+S0/7RPRlQ2+eBshum4QZqlimb+xolhu8cn5W1a6Xqx8fE9Na9dTucABhnrIi6a2k+WxhkLppv23Q
+nMk08QXXKdMD31DlBJtTN6Fd8TrJJkiTK/UYn7pXywkJxbxBlM5h69t0HLq1Kfy35cUndEsMQFOu
+YV4wOmt1YKdwZPWv2rKcj5Uh4KqVGfNmece/YSOTJtsZiW/Vu4UYjhgCrXX437v1/A9+FQJBw7q0
+fu4Ds1xTnsda9mMHjaf33AdTFRy/bHKwFsyiuzpCW3mip8NSM/NcNxRaPJEblpULVBm/CGsNpEH0
+VxllYxeU2sK6n/6pj6KwWpa+hHz3uMcOI2na1wevNvSmGrihx+SW3qVJuhMKL0UDhyJkKiM8dW8G
+1VnVYRG7N95QkzctIvbgR2B0iIjHLvRInuYk/4WSuKhqnLk8OrcMkFtkBft3THqfErS+Chgq09Zv
+2U+0YSUIjDlKSkIAiCsyhfYB7tZtGVxr0KQE8Mx6PXjBt8dNuYQ/NT3yS5ivysfeDiig4+4nxywc
+R3M/uHBNJJURyIyYZmyDp3Rl7Wyols7PA3YUOivO6w3Yf95JyMr1s9k3xuugun6FwCKsAXrny8r5
+8Jx396KnlJBvFYJDqTCZhY0cKOQgRWEGPg9J0TTixc2YZTSJiXvyS7Od6LcpiqUiPgR7g+QpcXLh
+jopxwkLiktSiK9BQOZSZmC8gYW4d+6/K3urIiLh58E6k6rXu5xdn4zJKDj9smcd5vAQosOVlGR3A
+u5PaITawcbi2/lzQR9CqgPpPmckLwphlnin5OupoJiIMktEIsh0VCmFMyYUo6tJl+LqUkX8m1qLV
+WR9TxCF4Xa1tTihaRGYbCtyglMicJQEAuwpsVVaW5g1eEPiSHKAJTPgQ8jS3TunzrTdJ6r5whLVP
+zJCrgrnlt9dostKaGjwAjUSfSkEfMvFN5u1M19v75F/8VhSFvTOZJuB4Wbj3WDSG7auZ+ousEkYw
+bWeuZndxqSb/CaYAXLYN3uaQNgMiWoCjm4Iek7lRQuvYYZN9PZRb4DGl2pTt2TyDCcuhsHsW92wl
+Cv2NwUZ3yDE5hQXCpKIgpq1dvQhMOuV0CsFy98lOMb9AR3b1fB3c2lSb1nQjsdaxZ96LpAd7Zjhr
+Si93RBCbUI2/p1N1A4SIP7i4Gm7E+VwlFQ/MwfXi0XHAEOHA4udc8TQxKdZJCEfk6oOSvWESL6pp
+TWDfX2EFXxHVQvUXNroxZgpbLnKz0+tCWeDrYNa+iqaBB4USsQiy1cGVOMJlUTChTXNzHz/Du/m7
+TLGWEWBb6kNa9Dtt5sha2+fold3jmtiCazstd23l5yuCkRtaicaNpdg4DdKryNjP/IS971eblQ7m
+uDbseyCluUqWdm1IV5jYlcG89bHsu1UV4OQDe2rCYsX0UbADdB5spGUUVvd0oA8WmSQKKI6MmflN
+YDPUZ3EZQro6fclmZhDxof8yKdvfE3jZKA5aFM2AjEjWfE8uV6mugw1Xwg/CyQrTXWzrgU92LQC1
+MZhTxpt/+XzXLNicO7P+HcNdeu759ZW05RMuX5JFrceX2L4q5Aq29hjvZU4Xl/c1LgUIUTbG6JkZ
+ESgLjk6Ym9CQ2wAl/NupwdSUuCQaONyBZANv3/cpxvxjlGANd4HBdYAFMm7KwpktCEq4lzA7fApE
+Ax9J/DV5DxhHGuC0QYvM0XmvlZARYOOUbS3dMVVXZxlHl4xWd80EuWVN8pd/AYv5HDHOWF+27riY
+DBp+ZGKRa2dGlNgjLB0CSB4mZACK8bzNh/gFC8pfL1R5I4hOyfTNt98Z2x6w6zLBqzpu8yFc+pvV
+Hylmmt+BS4uKEvfN45fToc1CQfWQh4VEM/rOMF3F8WOcKNhDWaO3wE144L4V7EOr0UQt3L7eGytZ
+uG7BwORPpnXK7TRGS0e2CTVMIeAkBIQ/HCeH8GC90KEcXAtVnICt8apl7zU/p+GTdxypHYASfsD5
+Lrpd5c/ec2QjaXwdIsBjJm4WB2Nrtc1M6HrZt4xsaKuib2lp8rk515ddxhr96wD4//zTSe+RSxFj
+IwYsvs20YDnVAQqwuAlPysvcsa2R8OFyM0DMnLpTMVQhTDZSA7jWf8ea/0wUw7lKYnMhH0ZCUk4P
+nX6bGCFYxaTnoXjPX7myenCa+DpA4lEWDPmv94NLfkuDk81d38zi1rKtSIKK1fsCCKhXdF+zrh4e
+/TUj+EGdl/WQb9Z30HBRgjC4gBn4WFEXmL3HLhMAcz2CZgxd7UIiIMebSzWENLV/ui2/BhJP9YF8
+qxtb+onhdcwfx/yEacVSOOfhln3z+mrtPbFQ9hpLAdc9EpMbbgd4eUmiVKMLtqEd1NZO2j7KxlFa
+nhgTCuHINi8ugGLEaYHtucp/dt1kEo+Gtbc8On9lVNGs7cfE2FvhSOczCVwCa1NvFnusImp7f/ZN
+iAGZJx9OzSchUvgJm+ojddkLI5od9BjpuSikG6/Kjm8e0tjmlu0kEeceRKsWHgWvZpzjk9lrpEJJ
+G42i+/WLFT/6OVTEYWIVi2BuBkdX2zemZ7WLhyzivu46COqlRG8LdViYQTeDYw4vUqTT4oj10TUJ
+76tuU8fdrvwBbsHsVbwUBwt+VvW80CbwRO5fsPvH1D3nJzX0SGm+s+s+c3Zf7BEYQy5s7WGgWklJ
+5Lm2Q07uvJPY0cBSh08UqqKl0y4QBbxVsyOMQv4zAnwQxxAah0gc0BxeWRZonjVhLVz/WhH81ay4
+e97KIZsNH8cLyJLHd+cUjvwh/Q5xLlYQp9JL/3YhBm6OuFhEOovYOQu628Oos4Z7MqkvxmLA6h6V
+qQjpegl7VEI2e9Qxa/faJuqVO343yVj6tZdroYGL4jsiPHeHGpW/wvpv8LDEWwegO2M/n79YuPnK
+alInknEj8bu89B9uzPSx/QALn1HMzrBiDi6dxh6JOO48l6FxeQBFuH6gsRs6061YWbjPTjjVNGqg
+l5ttYbYBdS7bBWU6y8r2NzRvI3lJmIL5FrnDJnlw1HmvXLRUrJDTHxQnQUdrKqcyWuE5T2rW3qui
+rB4kb2y3wo2vpNT7ycJz5u1PpitHAgvCIR3K4QpXEWRQJmf9zfu3qEzqXnk/1hv0CxkzvQHChi4z
+tuKjLZfL81LvRKxtiGzdlOeSNnyckENfcIP+pDOEEXLVacUXT9tOTaI+dV08kQZLegO1EC1UmnQ2
+HqwEJ6qjI2C0wQI8sxm/0rQBKL/8z2krYBjdpnZceulX3KVrSM41OWMZ0Zrhd0MW5A29qkjM1x7I
+xPX0WEYY9YXp5s5cuQyFPRn1Tmyyrls9JDK790l9MUv8c3QOXlgmZF8m5dT43o5h/X5cf/OGJgSb
+2Tn9GHojnrpgw2vb1v0HnrNKUdIaIKjNxh2vYVm8Z8nANtL/Ua0OckKHI051NpV877q+w297k6lF
+ghrrnQIqemyboGgo4LMZXsZbWZlhQ0Xfg20dqQnRQ2fCY0dndw3+PWkolrkZGI0rse/rBfuf0T0S
+KagSx1tc7asbbslYTbfMfktloUZThbNjn8bnZY93RfmodqWC7IkAMpZoNXf8zekhkqP6ZZbDZxz5
+yAiN1Ug+NY29FnhvsU91c3Hb9Xq47i5xWOfJZgqS2WgzPQenWOSN3L90oEpVPJycdimVaO9p88OA
+QpAPv3BHakpcd/tJZaqC/apJuIywaSHQHV7+NStBEox3wERr5D1s8bq+5WTdU2DKmhLOoKFWu470
+Kk7BNabJFCY4UtrcwoddUZpWpSP3ijHrv7tNvKuelt6pR7jl0HEeusPS58rpJnlLip/S67VIybyk
+Eeq+Fmig+PXDMv+O2ixnDBZ76QyTKi8v3UPXquV9+8rW9V7vEInbB7S2NnHtX4ZbE2ORTr99/W0E
+CaGoU2aWRus8imFZ44V/LxKTMMe4fXD6jLX+cD8cnz5HCRFOszYsQdZytrlgOquRBL9y2yOMlrBm
+SK6vApu0IB8Tk4ebD0wGx25tpGIB34RPZQXisxXM0jZQnx+aSO2zpVu0sg2BIPqI5fnLSh+5Ko1p
+s3YTRYGNp38fDYvOpOL/UZSA0RCbs35xA1vYP+tuJx/XJF670T8vnPR/bpa88xTHLOZwCGHH6ca9
+JgyMC9WBGihwZtgtCVDAVMQ3qlS6LeGrL4pFdDlSNkGkcM0mM9LqL/HFisrlv8oPRLpc6epAga9J
+YqGoZdeSDdAw5RW1NoMtZbcN4p9ghWEjOw0SPgD/gX6PxDGeN0iYqp+G+YLrpEwqtDeAZE6W4+u/
+8WmwtXnwWxqaQP/joJjs7ZYWH+oEbxIcV9NUrwgxfjeS7MUeoaZLqItZQZN+SEQmydEAmJ1J0dRl
+W+mnzl8da76p3HdK8QNA4KOPET9jNgminwjbDzZpaUqANrWLggvPEeWw3k8B7efnslvv853WBEcy
+5nmsgbN6dfsIhF9nlIoZTkpDyOcI3mrd9xITdiodOfxNRPWbF1nl0H2MkVzf8M4UqHBYAcmFn3OQ
+HSVUS7KtOfgumIsyItVGK8lOr2If1Jxm5Qq+lln2K+dkygpd3vodWTIuyLjwaXrQ8er7FdOHX1XK
+oOXk59HEg+saRg1jlQDBY0cswZpX9VTHvcKgZHWvnRrHlPEA9B/x4Zssj5516tgT8a0x1rg+haas
+odnWSbOuH1gCEUAPVBUGAngdWDrHrBKjEeCFkVDZC2NQdYjjZol8jKGSjBmbN8OzMBrsesreeAIL
+IFhIUL6dMGFShHD7j23NHiXcakAGFMonsJm/UEW92upBeH5OVwajBZuVO45N/QytIc3hC4C3eUMe
+Sx6ezs4NQoXS3A2YalnmkAeaGW80J+rjZurT4O98Myn6Q6f7078J2quHVE+gJt4lkYIn4slGZprL
+C00CSuenqPBKALDqOfIpEc4LH9QjGWw/Gz8to8qVD6jPhOLDL2hgLTjKWr3bzj4blLuGgZ3qbe4h
+MKn3xxjgIHtoyozZWBoTGnkiDASRjUGyNVnInpjiRN9XHs81DuvObZScSI0PPU5QVUeOD8Itn00L
+8ISwrAdBOIP4BoMAIyFI1FjUkjFA0L2r5g3tFWetC4JUpS2drC3LlsQ/HQ/c/qVoE1IYvTb5goiB
+o54UyJ2H4wf9fs3tTkPWp+b1lp0bwgVSJEmbnO2yJmZ6Aq8mAKEZUnYzxT27MJyg58CGzkDrvmmo
+6mED/fKRZxcY5EqKIRLa0G3ZS8y1n6LzF7RAoefpisJ5f9Z5s1cCHAEkHpwhlk1N82xKC95vTNj+
+aXjMbvNgzTZl7kA9JCYOE+lWXOiEcCt3+nbQWPhpBHGyc9wERBj8cc/u6672AJ/MNtN4TRK0NSRP
+6yKqVwqn3Wc+FVULMgCFLamDyGwfKwIWIHXNy0gM/coZEwoK+4sX5wV9IGuuE4e7+dNG2iHMXwM+
+3ITBhDk8eIqEVC6vN5h4KQyhPHIfc2fy/491v/+zeLOKxN/eVLCoBnj3IeHDqAhh1qRcEdIqeys+
+J/9dIBpMcquA6ltyYUdEG0MemYA/PG3MaA5Hc+whmqhujVFgCWcwMLda2B5QRimEmOZPlqz+nPhs
+Cut5AwyhqSC8avwy3NeSnG8/wVkUge88gxZTytSQha0O2c4QS0FE/zftOD2w9gkyNeuoG6cGQcDU
+nt3WchrIfkmCvuqFN0Tbb2OQr7ZKZPP8oNXGuCIe/RxU7LbACfZ0JoowJER5L0GZ7EcWBrtq2jtN
+Av1vLmxzVdZfK2QR+uKrB+ylQEw1DvGqE+UwwkvFLxks88/fqdov7dFkMSsoNNsz+5kJAlzOQ7Ma
+AEMQEsxLHc4EuujJHi6fqmMn+PpKWi3KRc1GD3zyGHu3IZP2DOvns7GTTRJPVVGymAy79/8FLQX1
+ruE2nUkO2jSKK/Z8yemqPINbY+dv5faz/9qUtTYRzm3bnCcYlIxNs2z6KBCBxbZcIKLoD6hQoiOm
+NwUpncp4VX6nVImIcHJz0N3jUYWLcThCBiAjQWIgFTP3+xeqjnDIr9xJO+C5wjYSifuuMzMtCF3V
+9whVFZ+rnFYCJgBU1P3pZ242GBNHkA5fFusV15Jnf2sT9AbFlps73Th4a9A6YgccdAMJMvz75FRt
+QYwIPLBaUHhM1dkfzopfj/PNUBGzAcoJEZQfk2h6yBJ+Wcs7HoORtz342gmVp/mrTOAgf85N7LCs
+6TOHg07nSAOn1wxa34ELmREEeEEXVBba6Gt6Q0fuu2VPHenYXAD/0v5Ao4My5NpnEmriOO3U7tmE
+hFoxCWOfzJD4Gn+AtIEHWRSYvwXA3wjFAFxsFOgalnispQX5UC4IIuy6hZRUxBcLscIg+sF/oR/0
+cIoFwA10QP584v0vpm4XK/7UZLUei2INaP4Tp4MGZWlR8OMUCPYM5cWaNLzwMgZmUgsxJKhaFRIQ
+ek+jKyi1JBYIxpFnwYxFB+dlPQ6HysZ34apyvERONzRe18DkjB2IsycZQrJ7WV+sICvbSxCl1/U+
+c2tFoK35WOHbEAo4wgEfNfV1TNj9XZx22yNHAaR+K0Gc3nLmgMlPed5bqDWYx3oZlfRrLJ1/vtDU
+BHxKZ6YLX/WJbLvPaEDSc9OmOJqxT3Cw+UaIjXAU9NG5dXr4zWOO6yuWgl0Qp26T4G5+aupYP8zo
+6ubEdmnupTaQIGPxkeR9ImPBEp+G8MH+8W8ZeUYERu4WGqse73Q7QTLmjQ/pGGJ3brmm3xeCiH1k
+fHHc+zfK4kCmp+L5u7NI5hBkw/jCtPw0bo9Bxi6QerkTL/Nv/TN7UImeQ4oyFGKVh/DiK4rHV9Pr
+CbSmKfSnhXpoMfh/DSMzUlsUGDpLEzdMqn1k78zmtISvOYNa8cht+R3xg7D+Do1vS2o3lt124q7G
+2OljCnLPAX8Gi5QP376nYdUpWLCEfFDLtjNVgyMRP6vFR2tPe7MO4I8vKVFJrRqLxPJTzTSxsh2L
+Rtosl9C+EnbGkIVZ+YxFEABBn1EHwKX7cMr7lAUmhZG2EybX+vMwj7Do8YQf5fGw3s8hK49Aiczi
+0fMLl4KrmHK3MwCRrWus3Lkth8EW+1ak4CgFguNw56lhkBnWL4Zt0jlXJ57zvCxEglgKVIBfwDAJ
+Fp2M/RjEP5w14JdHo6KFHhUYmNgiZ5ygro7uLlkAituAFWKvYZglSbdOJWZapnzvXOnaRMDzOC8U
+YS9RsUt1nt888YTzId6ET+daVfDTY+5eVqiQRKDzd9uqWPl18Lok1xqF4c2hwJzF7YUTc9KjMCQ2
+NCPFzCqiYvO318e1zBulMIwHpo12kNrvYCO+tvUsB4fQNsQqitQIkV+jlCB88egSg9cukFwCi//T
+RZAfHmw/H8DJIIe6k6Mp4FdOyTM6PZno0rL7f/59REzx76ZaWbOuNo1o3B5VNlD9iIwyHWR94KTG
+tM03iWqlENiW61kgI+FRIyzN5ZeqgZJjYZSTwa+vbvL9S9MwBl5fmBzTcx8IX+jBUvviVud+175w
+4pj9tZW12XVtC2f27JWziOTq6pfTvv2CExAJSgeMmUS8u232YV9I3GtfDBUHanK5pHQQJAgbhdX8
++2PAsgQwtT8wZTPhLGcGi/rR/iqxbYnJXYO1338hpbY0iWyZOxDWQKMBOvZfjk9XThjNKwFIbCao
+fBkdXUD+usCjGXZ4+dtvvYIIUM3CdHPQXeOdN+SJSTkgQx37g1x17qODvlcQynnAqo1kFwl5m3jG
+GHyy47RmTTMqs+guapt35972DRK7gNuntHDZ9NzEjzhbZU98/6KRUFu+qyycSWQ288W9leCiNWLh
+3ylT8x2TP5LctInF07YG2ioIGFY22BwimlElS4JDiDSKqTUSHPPJSugenntWLqv2pZ2pvVstovcp
+VV0/TnL6XTqr8i7n+WYa0/xUexyDgdphH7BAdjjggeXqM0VL3GJI9yygtOIdxGL08AqONhU6vyAi
+AX0jsNs5orNqsFLFY8liOoCxmDIfrAb7Xw8hX5JP+zc6O52/6hZZe/1Hiy94BPz9AQqbSWgM7rR5
+nXY/4m9cB6O1zDKS4E4VBl/+JoI1hjDiK4JUZliVbnipEbQTDEZSGWqRdZoSHWCuXWoYrCFtfqsl
+n0gXOMb6Ims6nGAG/iBQmFx3jLed7Wuer7FFY3ZMSFViR8osC21Sbe9eWUwSBFHRJHXZ8HoXLK7a
+HEKpjzGW1XP5tGvZ6NOtd7P/HjC7AQrU6dV9fl1S1K8L+SCh3YwHUv+ixOo7WEoEsOmuvLW3c2ea
+F5z92P23XI1OX2sEqJ3GThnZdQSunAHVvJSZdzM3G5HOW6AQf+lEkxffsbuGqozQquNovOvEMJ2C
+AU2dYs1UiirCqCMPaKAErng3sefE280EcdrOnCFhGPE7vrHnJrTeB87cZfV/akdZovxnGqNmyHij
+04Kt6S0JyKPLU6KxQCSON5qldrkd8KSdmolx0K0qq7sOxHYAYVfZW7cWvhWfbkN60FTnlA8A4pRK
+9HKLL8V8BZ6oq8B7Ft/zTHC14OEYBx/SNjCTp5NskTezhqD5YYeCqVR9Ao6x2svRrktMIa6vEi5F
+d+AgM8nCcDRmCmRGnj4Hco/g4ggooar3aVaMr7wwivI3KgOQVebrfYtf5vMSqiutd4XtR0C0OxdW
+Hx44fkmMin5AHd/jNYR3LGoCSoqPhAzHmnXirWTY0GwHUYiKmChHj2NpYklvJxPDo2/IkBPAnZTj
+RpDKQmXupmh/tJ/eV7Rv80BYIsMU9Ln/KryJBGgExdJCsKUQi1uOo5u/h/xSq8mF3Z9ieplImKQ+
+CM1PY+64BXveswDREe8NmwO7rdvTfWtBTduhWDFFJnM3MRLHGaoSOUiMiVVQYJeekuwHZWBKlYOA
+saySna8xH0BjkhjW6jeuuU5uyP3+uYebFLbT9G7heAkG4Q9bNiEc3LyaepSruZsiGH47ne5cjyJj
+PXj66Ae1QXIw+eihattVM10GRX/35bh+CUgmxmyViJtAlKsg8qmh1ZCFQkbdI/oqoY7CXBS6voHA
+52aLtUvFFCE1WRh6xoa/oHM+nPidnOvMfTnMrZrTzMj9p9WQV2LWDCWrG+r1/jPZG8P62IeNN+S6
+0PgvZkhQolnf1HRpJwrfxyXZLGnnu+gth0rDn/Q+PTEN32gZlIj2PlQlj5K4A/D3K01/Qw95mPja
+C5cTzxDtOu0G0qJNvkadzmGTIXNQUyU0tyFh4rpo0zqyGvKxHHPS4rM6pw5AQxJ7ql0qmyujQf4k
+ahxTIRDLiVNbopiQXOjH0xx8rK2zoJrOVlNqa/oQma8oQYd2WN+U97f1OhmdYs5pzGqfBkx8Hggx
+iiQX1NVgn8y3yV9DVdVeU1J64Sg+02vikYDz1YJLWEbCWwc1mqTXt4nITICz1DDu8t0BtD3I9+jk
+2qxIvhEkk17cOIRk0VVDHH8vkrDyhovPdT+64MIjc+PWPLoqbHA7DRmRCOgaBTRu/iR60quLZNPv
+el30QMu620WTx2+Uq1pbKWY0EYDYdVTSes1cJQcgM7QRSD+xen4oywmFMXzahWLX3lyjxhiQSgNx
+Za7WSoQxcHUElb8Ughf1SRtWQjr62G+YGXMfyWxoBtdCx3m274pRIFm5fjXYKFtbN0rxFnQi5joq
+GaDnZeK3EpVp/1uia/6VRfWvZI92WPsmBkR3O5cobehPjnBJvoefIlmRX2A7CM2d/Y8tQDbHAdZN
++9+IIsQOXwLkuKtHgQy+KUh/e/cVu9lcUhL58e4232VI2lsuITbZzRPaUu0Y/9JxERcclHnh1AGW
+UlZCMMsl1lqeKxZAQZHKtFRrhrMnRE+UE+kuVZlkoaLvkS2rLfMn55Oe5oor/kQBN7hn6ir1MlIp
+BYEkFbOiS8aKbZ9pzcsldKd5za9pEQO/Q5gMI1pUb0V++5XShJuZVolpF6ev2wq7Lo6zaSKeIGk8
+AuPG7VuDxwFG16HMwhQyksrVZ4pCzRuI6wwK34Txk3kD4BJCQ+stscbrUXMswB3ZRMA7S4vR2Uez
+RO9mpcjjICYVx5R19276xZbhH/UHGzkL2mS52AtKuC0YHphrxDBqn7bTVxUEOu62Pwd2shmyqfGZ
+8GKkmYV1RFZ2oXL/vSa5zHBmaCWrC+6kq3lZTeJaYta/M+C4VVISQcGwSvshzQb+TkCqLydaJZeA
+XOwFgCL6m16LFtvtFgTAGzOsJS0OAUJ/gQWV/jFgJfQXz7NRhMHYPCIUsar5uTdUg7GT+Y9SGZq2
+nNf3R2z+Zt8m3xjSUs9WWJU+HE/dzaORD9BIC6aO3kqr+jgCg7go1JIxiKWhFiyZQQwmWK6Mp9K/
+ZStz/NB956DlSoOjG2tW0NmgUtZANacJcUeBamxRJ84rm2v2LGWpdrl4hIDueTkkL2GdK7BfFPv6
+9WzFfLjWqUVu/A2LGark1N90hu1aHScFY6ChbLgaTZW2tMWeZ7nj12wLtsalQ6GPiYQZPc0RyUWC
+zIW+hEaN3bUTBi6OBXjt9qfIphxX4x0z9tLY02RBWILG9XhpLnhOaAunoIVvLyW6znnnH5ysGci1
+HxUDbLzV0AYJhlaAZng9frdbllnRucHeoosagcBEkuTMWpOGpKfNczHPS4gq0mZLNZMyL/7WLifI
+N+fGZWIYDAQz6rlRn7ztBR5ko+XeMZD2OPiCAcIaQl4VrHHVx8aRKzAwRYHD8xbc4JlAST9AsTY0
+ZWAm9BU719YyysNSpcLcGIG/0XX7D1j+le5+jfPVCj5PSu1kphHslcnVoS9cFbSxTkNfZ/nagUe3
+ilZVBS/RfevWxCDZNGy12S5OC58z+KLm1XlB774K2G1wfiObG1H3ZyNJMWb+UXvKSMRZvlCA5P9l
+7pLAxg/P6NQlit5pD96XGjuUfxsSyC8gfvbHX0ITH0HShZ3CfUwKuXwJiOZdac+6KQVVNT0b0EbO
+kVCj5EzgZMZzEs/t4CURkp/zsC7XTZigxsbK2zIn1NvxblzTpcSUqftR68NoxvpfS5tTu7qqHiMJ
+q89jfIYutDvY8uJRxKdXaWybC1LFxbnAxqMo+c8ugfaqqe/f+Ud2ZdIMAfnb5WBkLHe6aiegCBVS
++ekYDA1rYu7eS5sQ3d02UbN2o4CQU96ibLVb/k4=
+`pragma protect end_protected

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8713/hdl/axis_infrastructure_v1_1_0.vh

@@ -0,0 +1,337 @@
+//  (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+//   f_clogb2
+//   f_gcd
+//   f_lcm
+//   f_get_tdata_indx
+//   f_get_tstrb_indx
+//   f_get_tkeep_indx
+//   f_get_tlast_indx
+//   f_get_tid_indx
+//   f_get_tdest_indx
+//   f_get_tuser_indx
+//   f_payload_width
+// Tasks:
+//   t_display_tdata_error
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+// Define Signal Set indices
+localparam G_INDX_SS_TREADY = 0;
+localparam G_INDX_SS_TDATA  = 1;
+localparam G_INDX_SS_TSTRB  = 2;
+localparam G_INDX_SS_TKEEP  = 3;
+localparam G_INDX_SS_TLAST  = 4;
+localparam G_INDX_SS_TID    = 5;
+localparam G_INDX_SS_TDEST  = 6;
+localparam G_INDX_SS_TUSER  = 7;
+localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
+localparam G_MASK_SS_TDATA  = 32'h1 << G_INDX_SS_TDATA;
+localparam G_MASK_SS_TSTRB  = 32'h1 << G_INDX_SS_TSTRB;
+localparam G_MASK_SS_TKEEP  = 32'h1 << G_INDX_SS_TKEEP;
+localparam G_MASK_SS_TLAST  = 32'h1 << G_INDX_SS_TLAST;
+localparam G_MASK_SS_TID    = 32'h1 << G_INDX_SS_TID  ;
+localparam G_MASK_SS_TDEST  = 32'h1 << G_INDX_SS_TDEST;
+localparam G_MASK_SS_TUSER  = 32'h1 << G_INDX_SS_TUSER;
+
+// Task DRC error levels
+localparam G_TASK_SEVERITY_ERR   = 2;
+localparam G_TASK_SEVERITY_WARNING = 1;
+localparam G_TASK_SEVERITY_INFO    = 0;
+
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Functions
+///////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+  function integer f_clogb2 (input integer size);
+    integer s;
+    begin
+      s = size;
+      s = s - 1;
+      for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+            s = s >> 1;
+    end
+  endfunction // clogb2
+
+  // Calculates the Greatest Common Divisor between two integers using the
+  // euclidean algorithm.
+  function automatic integer f_gcd (
+    input integer a,
+    input integer b
+    );
+    begin : main
+      if (a == 0) begin
+        f_gcd = b;
+      end else if (b == 0) begin
+        f_gcd = a;
+      end else if (a > b) begin
+        f_gcd = f_gcd(a % b, b);
+      end else begin
+        f_gcd = f_gcd(a, b % a);
+      end
+    end
+  endfunction
+
+  // Calculates the Lowest Common Denominator between two integers
+  function integer f_lcm (
+    input integer a,
+    input integer b
+    );
+    begin : main
+      f_lcm = ( a / f_gcd(a, b)) * b; 
+    end
+  endfunction
+
+  // Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tdata_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      f_get_tdata_indx = 0;
+    end
+  endfunction
+
+  // Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tstrb_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
+      // If TDATA exists, then add its width to its base to get the tstrb index
+      f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tkeep_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tlast_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tid_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tdest_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
+    end
+  endfunction
+
+  // Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
+  // signal is not enabled.
+  function integer f_get_tuser_indx (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
+      f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
+    end
+  endfunction
+
+  // Payload is the sum of all the AXIS signals present except for
+  // TREADY/TVALID
+  function integer f_payload_width (
+    input integer DAW,  // TDATA Width
+    input integer IDW,  // TID Width
+    input integer DEW,  // TDEST Width
+    input integer USW,  // TUSER Width
+    input [31:0]  SST   // Signal Set
+    );
+    begin : main
+      integer cur_indx;
+      cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
+      f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
+      // Ensure that the return value is never less than 1
+      f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
+    end
+  endfunction
+
+  task t_check_tdata_width(
+    input  integer    data_width,
+    input  [8*80-1:0] var_name,
+    input  [8*80-1:0] inst_name,
+    input  integer    severity_lvl,
+    output integer    ret_val
+  );
+    // Severity levels:
+    // 0 = INFO
+    // 1 = WARNING
+    // 2 = ERROR
+    begin : t_check_tdata_width
+      if (data_width%8 != 0) begin  
+        //       000       1          2         3         4         5         6         7         8
+        //       012       0          0         0         0         0         0         0         0
+        if (severity_lvl >= 2) begin
+        $display("ERROR: %m::%s", inst_name);
+        end else if (severity_lvl == 1) begin
+        $display("WARNING: %m::%s", inst_name);
+        end else begin
+        $display("INFO: %m::%s", inst_name);
+        end
+        $display("       Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
+        $display("       AXI4-Stream data width is only defined for byte multiples. See the ");
+        $display("       AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
+        $display("       information.");
+        ret_val = 1;
+      end else begin
+        ret_val = 0;
+      end
+    end
+  endtask
+
+  task t_check_tuser_width(
+    input  integer    tuser_width,
+    input  [8*80-1:0] tuser_name,
+    input  integer    tdata_width,
+    input  [8*80-1:0] tdata_name,
+    input  [8*80-1:0] inst_name,
+    input  integer    severity_lvl,
+    output integer    ret_val
+  );
+    // Severity levels:
+    // 0 = INFO
+    // 1 = WARNING
+    // 2 = ERROR
+    begin : t_check_tuser_width
+      integer tdata_bytes; 
+      tdata_bytes = tdata_width/8;
+      if ((tuser_width%tdata_bytes) != 0) begin  
+        //       000       1          2         3         4         5         6         7         8
+        //       012       0          0         0         0         0         0         0         0
+        if (severity_lvl >= 2) begin
+        $display("ERROR: %m::%s", inst_name);
+        end else if (severity_lvl == 1) begin
+        $display("WARNING: %m::%s", inst_name);
+        end else begin
+        $display("INFO: %m::%s", inst_name);
+        end
+        $display("       Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
+        $display("       multiple of the width of the interface (%s == %2d) in bytes.'  AXI4-Stream", tdata_name, tdata_width);
+        $display("       TUSER width in this module is only defined when the TUSER is the");
+        $display("       recommended value.  See the AMBA4 AXI4-Stream Protocol Specification v1.0");
+        $display("       Section 2.1, 2.3.3 and 2.8 for more information.  ");
+        ret_val = 1;
+      end else begin
+        ret_val = 0;
+      end
+    end
+  endtask
+

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8c62/hdl/processing_system7_vip_v1_0_7_apis.v

@@ -0,0 +1,842 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_7_apis.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Set of Zynq VIP APIs that are used for writing tests.
+ *                
+ *****************************************************************************/
+
+  /* API for setting the STOP_ON_ERROR*/  
+  task automatic set_stop_on_error;
+    input LEVEL;
+    begin
+      $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
+      STOP_ON_ERROR = LEVEL;
+//    M_AXI_GP0.master.set_stop_on_error(LEVEL);
+//    M_AXI_GP1.master.set_stop_on_error(LEVEL);
+//    S_AXI_GP0.slave.set_stop_on_error(LEVEL);
+//    S_AXI_GP1.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP0.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP1.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP2.slave.set_stop_on_error(LEVEL);
+//    S_AXI_HP3.slave.set_stop_on_error(LEVEL);
+//    S_AXI_ACP.slave.set_stop_on_error(LEVEL);
+      M_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      M_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_GP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP0.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP1.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP2.STOP_ON_ERROR = LEVEL;
+      S_AXI_HP3.STOP_ON_ERROR = LEVEL;
+      S_AXI_ACP.STOP_ON_ERROR = LEVEL;
+
+    end
+  endtask 
+
+  /* API for setting the verbosity for channel level info*/  
+  task automatic set_channel_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+//     "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
+//     "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
+//    "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+//    "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+      "ALL"       : begin
+//                     M_AXI_GP0.master.set_channel_level_info(LEVEL);
+//                     M_AXI_GP1.master.set_channel_level_info(LEVEL);
+//                    S_AXI_GP0.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_GP1.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP0.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP1.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP2.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_HP3.slave.set_channel_level_info(LEVEL);
+//                    S_AXI_ACP.slave.set_channel_level_info(LEVEL);
+                    end
+      default     : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the verbosity for function level info*/  
+  task automatic set_function_level_info;
+    input [1023:0] name;
+    input LEVEL;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO,  name , LEVEL);
+     case(name)
+//     "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
+//     "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
+//    "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
+//    "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
+//    "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
+//    "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
+      "ALL"       : begin
+//                     M_AXI_GP0.master.set_function_level_info(LEVEL);
+//                     M_AXI_GP1.master.set_function_level_info(LEVEL);
+//                    S_AXI_GP0.slave.set_function_level_info(LEVEL);
+//                    S_AXI_GP1.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP0.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP1.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP2.slave.set_function_level_info(LEVEL);
+//                    S_AXI_HP3.slave.set_function_level_info(LEVEL);
+//                    S_AXI_ACP.slave.set_function_level_info(LEVEL);
+                    end
+      default     : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting the Message verbosity */  
+  task automatic set_debug_level_info;
+    input LEVEL;
+    begin
+      $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO,  LEVEL);
+      DEBUG_INFO = LEVEL;
+      M_AXI_GP0.DEBUG_INFO = LEVEL;
+      M_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_GP0.DEBUG_INFO = LEVEL;
+      S_AXI_GP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP0.DEBUG_INFO = LEVEL;
+      S_AXI_HP1.DEBUG_INFO = LEVEL;
+      S_AXI_HP2.DEBUG_INFO = LEVEL;
+      S_AXI_HP3.DEBUG_INFO = LEVEL;
+      S_AXI_ACP.DEBUG_INFO = LEVEL; 
+    end
+  endtask
+
+  /* API for setting ARQos Values */  
+  task automatic set_arqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO,  name , value);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
+      "S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
+      "S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
+      "S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
+      "S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
+      "S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
+      "S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
+      default     : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for setting AWQos Values */  
+  task automatic set_awqos;
+    input [1023:0] name;
+    input [axi_qos_width-1:0] value;
+    begin
+     $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO,  name , value);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
+      "S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
+      "S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
+      "S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
+      "S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
+      "S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
+      "S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
+      default     : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
+     endcase
+    end
+  endtask
+
+  /* API for soft reset control */
+  task automatic fpga_soft_reset;
+    input[data_width-1:0] reset_ctrl;
+    begin
+      if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO,  reset_ctrl); 
+      gen_rst.fpga_soft_reset(reset_ctrl);  
+    end
+  endtask
+
+    /* API for por and strb reset control */
+//    task automatic por_srstb_reset;
+//      input por_reset_ctrl;
+//      begin
+//        if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO,  por_reset_ctrl); 
+//  //      gen_rst.por_srstb_reset(por_reset_ctrl); 
+//        gen_rst.por_srstb_reset(por_reset_ctrl);  
+//  
+//      end
+//    endtask
+
+  /* API for pre-loading memories from (DDR/OCM model) */
+  task automatic pre_load_mem_from_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      succ = $fopen(file_name,"r");
+      if(succ == 0) begin
+        $display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+ 
+  /* API for pre-loading memories (DDR/OCM) */
+  task automatic pre_load_mem;
+    input [1:0] data_type;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+		          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        DDR_MEM : begin
+                  ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR) $stop; 
+      end
+    end
+  endtask
+
+  /* API for backdoor write to memories (DDR/OCM) */
+  task automatic write_mem;
+    input [max_burst_bits-1 :0] data;
+    input [addr_width-1:0] start_addr;
+    input [max_burst_bytes_width:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+		          if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid); 
+                  else
+                    ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+    /* read_memory */
+    task automatic read_mem;
+      input [addr_width-1:0] start_addr;
+      input [max_burst_bytes_width :0] no_of_bytes;
+      output[max_burst_bits-1 :0] data;
+      reg [1:0] mem_type;
+      integer succ;
+      begin
+        mem_type = decode_address(start_addr);
+        if(check_addr_aligned(start_addr)) begin    
+          case(mem_type)
+          OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.read_mem(data,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                    if(DEBUG_INFO)
+                      $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          DDR_MEM : begin
+                    ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
+                    if(DEBUG_INFO)
+                      $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO,  start_addr, no_of_bytes); 
+                    end 
+          default : begin
+                    $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                    if(STOP_ON_ERROR) $stop; 
+                    end 
+          endcase
+        end else begin 
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
+          if(STOP_ON_ERROR)
+            $stop; 
+        end
+      end
+  endtask
+
+  /* API for backdoor read to memories (DDR/OCM) */
+  task automatic peek_mem_to_file;
+    input [(max_chars*8)-1:0] file_name;
+    input [addr_width-1:0] start_addr;
+    input [int_width-1:0] no_of_bytes;
+    reg [1:0] mem_type;
+    integer succ;
+    begin
+      mem_type = decode_address(start_addr);
+      if(check_addr_aligned(start_addr)) begin    
+        case(mem_type)
+        OCM_MEM : begin
+                  if (!C_HIGH_OCM_EN)
+                    ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); 
+                  else
+                    ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); 
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        DDR_MEM : begin
+                  ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
+                  if(DEBUG_INFO)
+                    $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO,  start_addr, no_of_bytes, file_name); 
+                  end 
+        default : begin
+                  $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+                  if(STOP_ON_ERROR) $stop; 
+                  end 
+        endcase
+      end else begin 
+        $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
+        if(STOP_ON_ERROR)
+          $stop; 
+      end
+    end
+  endtask
+
+  /* API to read interrupt status */
+  task automatic read_interrupt;
+    output[irq_width-1:0] irq_status;
+    begin
+      irq_status = IRQ_F2P;
+      if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO,  irq_status);
+    end
+  endtask
+
+  /* API to wait on interrup */
+  task automatic wait_interrupt;
+    input [3:0] irq;
+    output[irq_width-1:0] irq_status;
+    begin
+      if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO,  irq);
+
+      case(irq) 
+      0 :  wait(IRQ_F2P[0] === 1'b1);
+      1 :  wait(IRQ_F2P[1] === 1'b1);
+      2 :  wait(IRQ_F2P[2] === 1'b1);
+      3 :  wait(IRQ_F2P[3] === 1'b1);
+      4 :  wait(IRQ_F2P[4] === 1'b1);
+      5 :  wait(IRQ_F2P[5] === 1'b1);
+      6 :  wait(IRQ_F2P[6] === 1'b1);
+      7 :  wait(IRQ_F2P[7] === 1'b1);
+      8 :  wait(IRQ_F2P[8] === 1'b1);
+      9 :  wait(IRQ_F2P[9] === 1'b1);
+      10:  wait(IRQ_F2P[10] === 1'b1);
+      11:  wait(IRQ_F2P[11] === 1'b1);
+      12:  wait(IRQ_F2P[12] === 1'b1);
+      13:  wait(IRQ_F2P[13] === 1'b1);
+      14:  wait(IRQ_F2P[14] === 1'b1);
+      15:  wait(IRQ_F2P[15] === 1'b1);
+      default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
+      endcase
+      if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO,  irq);
+      irq_status = IRQ_F2P;
+    end
+  endtask
+
+  /* API to wait for a certain match pattern*/ 
+  task automatic wait_mem_update;
+    input[addr_width-1:0] address;
+    input[data_width-1:0] data_in;
+    output[data_width-1:0] data_out;
+    reg[data_width-1:0] datao;
+    begin
+      if(mem_update_key) begin
+        mem_update_key = 0;
+        if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in); 
+        if(check_addr_aligned(address)) begin
+         ddrc.ddr.wait_mem_update(address, datao);
+         if(datao != data_in)begin 
+           $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
+           $stop;
+         end else
+           $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO,  address, data_in);
+         data_out = datao;
+        end else begin
+           $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR,  address); 
+           if(STOP_ON_ERROR) $stop;
+        end
+        mem_update_key = 1;
+      end else 
+        $display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end
+  endtask
+
+
+ /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ 
+ task automatic write_from_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] wr_size;
+   output [axi_rsp_width-1:0] response;
+   integer succ;
+   begin
+      succ = $fopen(file_name,"r");
+      if(succ == 0) begin
+        $display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name); 
+        if(STOP_ON_ERROR) $stop; 
+      end   
+      else if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         $fclose(succ);
+         // case(start_addr[31:30])
+         if (start_addr[31:30] === 2'b01) begin
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end else if(start_addr[31:30] === 2'b10) begin
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO,  start_addr, wr_size, file_name); 
+            M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
+            if(DEBUG_INFO)
+              $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end else begin
+           $display("[%0d] : %0s : Invalid Address(0x%0h)  'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); 
+          end
+         // endcase
+      end else begin
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+ endtask
+
+ /* API to initiate a READ transaction on one of the AXI-Master ports*/ 
+ task automatic read_to_file;
+   input [(max_chars*8)-1:0] file_name;
+   input [addr_width-1:0] start_addr;
+   input [int_width-1:0] rd_size;
+   output [axi_rsp_width-1:0] response;
+   begin
+      if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR ,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+      end else if(check_addr_aligned(start_addr)) begin
+         // case(start_addr[31:30])
+         if (start_addr[31:30] === 2'b01) begin
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          end else if(start_addr[31:30] === 2'b10) begin
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO,  start_addr, rd_size, file_name); 
+            M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
+            if(DEBUG_INFO)
+               $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO,  start_addr); 
+          // end
+          // default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); 
+         // endcase
+      end else begin
+          $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR,  start_addr); 
+          if(STOP_ON_ERROR) $stop;
+      end
+   end
+   end
+ endtask
+
+ /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic write_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] wr_size;
+   input [(max_transfer_bytes*8)-1:0] w_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+         $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(wr_size > max_transfer_bytes) begin
+         $display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, wr_size); 
+       M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); 
+   end
+ endtask
+
+ /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ 
+ task automatic read_data;
+   input [addr_width-1:0] start_addr;
+   input [max_transfer_bytes_width:0] rd_size;
+   output[(max_transfer_bytes*8)-1:0] rd_data;
+   output [axi_rsp_width-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(rd_size > max_transfer_bytes) begin
+         $display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR,  start_addr); 
+         if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO,  start_addr, rd_size); 
+       M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); 
+    end
+ endtask
+
+/* Hooks to call to VIP APIs */
+ task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === 2'b01) begin
+    // end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === 2'b10) begin
+    // end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
+   reg[511:0] rsp; /// string for response
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === 2'b01) begin
+    // end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === 2'b10) begin
+    // end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO,  start_addr, datasize); 
+       M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr); 
+   end
+ endtask 
+
+ task automatic read_burst;
+   input [addr_width-1:0] start_addr;
+   input [axi_len_width-1:0] len;
+   input [axi_size_width-1:0] siz;
+   input [axi_brst_type_width-1:0] burst;
+   input [axi_lock_width-1:0] lck;
+   input [axi_cache_width-1:0] cache;
+   input [axi_prot_width-1:0] prot;
+   output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
+   output [(axi_rsp_width*axi_burst_len)-1:0] response;
+   reg[511:0] rsp;
+   begin
+    if(!check_master_address(start_addr)) begin
+       $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR,  start_addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(start_addr[31:30] === 2'b01) begin
+    // end else if(start_addr[31:30] === GP_M0) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else if(start_addr[31:30] === 2'b10) begin
+    // end else if(start_addr[31:30] === GP_M1) begin
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO,  start_addr); 
+       M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
+       rsp = get_resp(response);
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO,  start_addr, rsp); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr); 
+    end
+ endtask 
+
+ task automatic wait_reg_update;
+   input [addr_width-1:0] addr;
+   input [data_width-1:0] data_i;
+   input [data_width-1:0] mask_i;
+   input [int_width-1:0] time_interval;
+   input [int_width-1:0] time_out;
+   output [data_width-1:0] data_o;
+
+   reg upd_done0;
+   reg upd_done1;
+   begin
+    if(!check_master_address(addr)) begin
+       $display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR,  addr); 
+       if(STOP_ON_ERROR) $stop;
+    end else if(addr[31:30] === 2'b01) begin
+    // end else if(addr[31:30] === GP_M0) begin
+     if(reg_update_key_0) begin
+       reg_update_key_0 = 0;
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
+       if(DEBUG_INFO && upd_done0)
+         $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); 
+       reg_update_key_0 = 1;
+     end else
+       $display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end else if(addr[31:30] === 2'b10) begin
+    // end else if(addr[31:30] === GP_M1) begin
+     if(reg_update_key_1) begin
+       reg_update_key_1 = 0;
+       if(DEBUG_INFO)
+         $display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); 
+       M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
+       if(DEBUG_INFO && upd_done1)
+         $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO,  addr); 
+       reg_update_key_1 = 1;
+     end else
+       $display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); 
+    end else
+       $display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr); 
+   end
+ endtask 
+
+/* API to read register map */
+ task read_register_map;
+   input [addr_width-1:0] start_addr;
+   input [max_regs_width:0] no_of_registers;
+   output[max_burst_bits-1 :0] data;
+   reg [max_regs_width:0] no_of_regs;
+   begin
+    no_of_regs = no_of_registers;
+    if(no_of_registers > 32) begin
+      $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
+      no_of_regs = 32;
+    end
+    if(check_addr_aligned(start_addr)) begin
+      if(decode_address(start_addr) == REG_MEM) begin
+        if(DEBUG_INFO)  $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO,  start_addr,no_of_regs ); 
+        regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
+        if(DEBUG_INFO)  $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO,  start_addr, data ); 
+      end else begin
+       $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
+      end
+    end else begin
+       data = 0;
+       $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
+    end
+   end
+ endtask
+
+/* API to read single register */
+ task read_register;
+   input [addr_width-1:0] addr;
+   output[data_width-1:0] data;
+   begin
+    if(check_addr_aligned(addr)) begin
+       if(decode_address(addr) == REG_MEM) begin
+         if(DEBUG_INFO)  $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO,  addr ); 
+         regc.regm.get_data(addr >> 2, data);
+         if(DEBUG_INFO)  $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO,  addr, data ); 
+       end else begin
+         $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
+       end
+    end else begin
+       data = 0;
+       $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
+    end
+
+   end
+ endtask
+
+  /* API to set the AXI-Slave profile*/ 
+ task automatic set_slave_profile;
+    input[1023:0] name;
+    input[1:0] latency ;
+    begin 
+     if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO,  name);
+     case(name)
+      "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
+      "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
+      "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
+      "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
+      "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
+      "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
+      "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
+      "ALL"       : begin
+                     S_AXI_GP0.set_latency_type(latency);
+                     S_AXI_GP1.set_latency_type(latency);
+                     S_AXI_HP0.set_latency_type(latency);
+                     S_AXI_HP1.set_latency_type(latency);
+                     S_AXI_HP2.set_latency_type(latency);
+                     S_AXI_HP3.set_latency_type(latency);
+                     S_AXI_ACP.set_latency_type(latency);
+                    end  
+     endcase
+    end
+ endtask
+
+
+/*------------------------------ LOCAL APIs ------------------------------------------------ */
+
+  /* local API for address decoding*/
+  function automatic [1:0] decode_address;
+    input [addr_width-1:0] address;
+    begin
+      if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) 
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= ddr_start_addr && address <= ddr_end_addr)
+        decode_address = DDR_MEM; /// DDR 
+      else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
+        decode_address = OCM_MEM; /// OCM 
+      else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
+        decode_address = REG_MEM; /// Register Map
+      else
+        decode_address = INVALID_MEM_TYPE; /// ERROR in Address 
+    end
+  endfunction 
+
+  /* local API for checking address is 32-bit (4-byte) aligned */
+  function automatic check_addr_aligned;
+    input [addr_width-1:0] address;
+    begin 
+      if((address%4) !=0 ) begin // 
+        check_addr_aligned = 0; ///not_aligned
+      end else
+        check_addr_aligned = 1;
+    end
+  endfunction
+
+ /* local API to check address for GP Masters */
+ function check_master_address; 
+   input [addr_width-1:0] address;
+   begin
+     if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) 
+       check_master_address = 1'b1; 
+     else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) 
+       check_master_address = 1'b1; 
+     else
+       check_master_address = 1'b0; /// ERROR in Address 
+   end
+ endfunction
+
+ /* Response decode */
+ function automatic [511:0] get_resp;
+   input[axi_rsp_width-1:0] response;
+   begin 
+    case(response)
+     2'b00 : get_resp = "OKAY";
+     2'b01 : get_resp = "EXOKAY";
+     2'b10 : get_resp = "SLVERR";
+     2'b11 : get_resp = "DECERR";
+    endcase
+   end
+ endfunction 

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8c62/hdl/processing_system7_vip_v1_0_7_axi_acp.v

@@ -0,0 +1,94 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_7_axi_acp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for ACP port
+ *
+ *****************************************************************************/
+
+/* AXI Slave ACP */
+  processing_system7_vip_v1_0_7_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
+               axi_acp_name, // name
+               axi_acp_data_width, // data width
+               addr_width, /// address width
+               axi_acp_id_width, // ID width
+               C_S_AXI_ACP_BASEADDR, // slave base address
+               C_S_AXI_ACP_HIGHADDR,// slave size
+               axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes 
+               axi_slv_excl_support, // Exclusive access support
+               axi_acp_wr_outstanding,
+               axi_acp_rd_outstanding)
+  S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
+            .S_ACLK   (S_AXI_ACP_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_ACP_AWID),
+            .S_AWADDR  (S_AXI_ACP_AWADDR),
+            .S_AWLEN   (S_AXI_ACP_AWLEN),
+            .S_AWSIZE  (S_AXI_ACP_AWSIZE),
+            .S_AWBURST (S_AXI_ACP_AWBURST),
+            .S_AWLOCK  (S_AXI_ACP_AWLOCK),
+            .S_AWCACHE (S_AXI_ACP_AWCACHE),
+            .S_AWPROT  (S_AXI_ACP_AWPROT),
+            .S_AWVALID (S_AXI_ACP_AWVALID),
+            .S_AWREADY (S_AXI_ACP_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_ACP_WID),
+            .S_WDATA  (S_AXI_ACP_WDATA),
+            .S_WSTRB  (S_AXI_ACP_WSTRB), 
+            .S_WLAST  (S_AXI_ACP_WLAST), 
+            .S_WVALID (S_AXI_ACP_WVALID),
+            .S_WREADY (S_AXI_ACP_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_ACP_BID),
+            .S_BRESP  (S_AXI_ACP_BRESP),
+            .S_BVALID (S_AXI_ACP_BVALID),
+            .S_BREADY (S_AXI_ACP_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_ACP_ARID),
+            .S_ARADDR  (S_AXI_ACP_ARADDR),
+            .S_ARLEN   (S_AXI_ACP_ARLEN),
+            .S_ARSIZE  (S_AXI_ACP_ARSIZE),
+            .S_ARBURST (S_AXI_ACP_ARBURST),
+            .S_ARLOCK  (S_AXI_ACP_ARLOCK),
+            .S_ARCACHE (S_AXI_ACP_ARCACHE),
+            .S_ARPROT  (S_AXI_ACP_ARPROT),
+            .S_ARVALID (S_AXI_ACP_ARVALID),
+            .S_ARREADY (S_AXI_ACP_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_ACP_RID),
+            .S_RDATA  (S_AXI_ACP_RDATA),
+            .S_RRESP  (S_AXI_ACP_RRESP),
+            .S_RLAST  (S_AXI_ACP_RLAST),
+            .S_RVALID (S_AXI_ACP_RVALID),
+            .S_RREADY (S_AXI_ACP_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_ACP_AWQOS),
+            .S_ARQOS  (S_AXI_ACP_ARQOS),            // Side band signals 
+
+            .SW_CLK   (net_sw_clk),
+/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
+            .WR_DATA_ACK_DDR (ddr_wr_ack_port0),
+            .WR_DATA_ACK_OCM (ocm_wr_ack_port0),
+            .WR_DATA  (net_wr_data_acp), 
+            .WR_DATA_STRB  (net_wr_strb_acp), 
+            .WR_ADDR  (net_wr_addr_acp), 
+            .WR_BYTES  (net_wr_bytes_acp), 
+            .WR_DATA_VALID_DDR  (ddr_wr_dv_port0), 
+            .WR_DATA_VALID_OCM  (ocm_wr_dv_port0), 
+            .WR_QOS (net_wr_qos_acp),
+
+            .RD_REQ_DDR (ddr_rd_req_port0),
+            .RD_REQ_OCM (ocm_rd_req_port0),
+            .RD_REQ_REG (reg_rd_req_port0),
+            .RD_ADDR (net_rd_addr_acp),
+            .RD_DATA_DDR (ddr_rd_data_port0),
+            .RD_DATA_OCM (ocm_rd_data_port0),
+            .RD_DATA_REG (reg_rd_data_port0),
+            .RD_BYTES (net_rd_bytes_acp),
+            .RD_DATA_VALID_DDR (ddr_rd_dv_port0),
+            .RD_DATA_VALID_OCM (ocm_rd_dv_port0),
+            .RD_DATA_VALID_REG (reg_rd_dv_port0),
+            .RD_QOS (net_rd_qos_acp)
+
+);

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8c62/hdl/processing_system7_vip_v1_0_7_axi_gp.v

@@ -0,0 +1,311 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_7_axi_gp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI GP ports
+ *
+ *****************************************************************************/
+
+    /* IDs for Masters 
+       // l2m1 (CPU000)
+       12'b11_000_000_00_00    
+       12'b11_010_000_00_00     
+       12'b11_011_000_00_00   
+       12'b11_100_000_00_00   
+       12'b11_101_000_00_00   
+       12'b11_110_000_00_00     
+       12'b11_111_000_00_00     
+       // l2m1 (CPU001)
+       12'b11_000_001_00_00    
+       12'b11_010_001_00_00     
+       12'b11_011_001_00_00    
+       12'b11_100_001_00_00    
+       12'b11_101_001_00_00    
+       12'b11_110_001_00_00     
+       12'b11_111_001_00_00    
+   */
+ 
+/* AXI -Master GP0 */
+  processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP0, // enable
+               axi_mgp0_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
+            .M_ACLK   (M_AXI_GP0_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP0_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP0_AWADDR),
+            .M_AWLEN   (M_AXI_GP0_AWLEN),
+            .M_AWSIZE  (M_AXI_GP0_AWSIZE),
+            .M_AWBURST (M_AXI_GP0_AWBURST),
+            .M_AWLOCK  (M_AXI_GP0_AWLOCK),
+            .M_AWCACHE (M_AXI_GP0_AWCACHE),
+            .M_AWPROT  (M_AXI_GP0_AWPROT),
+            .M_AWVALID (M_AXI_GP0_AWVALID),
+            .M_AWREADY (M_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP0_WID_FULL),
+            .M_WDATA  (M_AXI_GP0_WDATA),
+            .M_WSTRB  (M_AXI_GP0_WSTRB), 
+            .M_WLAST  (M_AXI_GP0_WLAST), 
+            .M_WVALID (M_AXI_GP0_WVALID),
+            .M_WREADY (M_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP0_BID_FULL),
+            .M_BRESP  (M_AXI_GP0_BRESP),
+            .M_BVALID (M_AXI_GP0_BVALID),
+            .M_BREADY (M_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP0_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP0_ARADDR),
+            .M_ARLEN   (M_AXI_GP0_ARLEN),
+            .M_ARSIZE  (M_AXI_GP0_ARSIZE),
+            .M_ARBURST (M_AXI_GP0_ARBURST),
+            .M_ARLOCK  (M_AXI_GP0_ARLOCK),
+            .M_ARCACHE (M_AXI_GP0_ARCACHE),
+            .M_ARPROT  (M_AXI_GP0_ARPROT),
+            .M_ARVALID (M_AXI_GP0_ARVALID),
+            .M_ARREADY (M_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP0_RID_FULL),
+            .M_RDATA  (M_AXI_GP0_RDATA),
+            .M_RRESP  (M_AXI_GP0_RRESP),
+            .M_RLAST  (M_AXI_GP0_RLAST),
+            .M_RVALID (M_AXI_GP0_RVALID),
+            .M_RREADY (M_AXI_GP0_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP0_AWQOS),
+            .M_ARQOS  (M_AXI_GP0_ARQOS)
+            ); 
+ 
+ /* AXI Master GP1 */
+  processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP1, // enable
+               axi_mgp1_name,// name
+               axi_mgp_data_width, /// Data Width
+               addr_width, /// Address width
+               axi_mgp_id_width,  //// ID Width
+               axi_mgp_outstanding,  //// Outstanding transactions
+               axi_mst_excl_support, // EXCL Access Support
+               axi_mgp_wr_id, //WR_ID
+               axi_mgp_rd_id) //RD_ID
+  M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
+            .M_ACLK   (M_AXI_GP1_ACLK),
+            // Write Address Channel
+            .M_AWID    (M_AXI_GP1_AWID_FULL),
+            .M_AWADDR  (M_AXI_GP1_AWADDR),
+            .M_AWLEN   (M_AXI_GP1_AWLEN),
+            .M_AWSIZE  (M_AXI_GP1_AWSIZE),
+            .M_AWBURST (M_AXI_GP1_AWBURST),
+            .M_AWLOCK  (M_AXI_GP1_AWLOCK),
+            .M_AWCACHE (M_AXI_GP1_AWCACHE),
+            .M_AWPROT  (M_AXI_GP1_AWPROT),
+            .M_AWVALID (M_AXI_GP1_AWVALID),
+            .M_AWREADY (M_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .M_WID    (M_AXI_GP1_WID_FULL),
+            .M_WDATA  (M_AXI_GP1_WDATA),
+            .M_WSTRB  (M_AXI_GP1_WSTRB), 
+            .M_WLAST  (M_AXI_GP1_WLAST), 
+            .M_WVALID (M_AXI_GP1_WVALID),
+            .M_WREADY (M_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .M_BID    (M_AXI_GP1_BID_FULL),
+            .M_BRESP  (M_AXI_GP1_BRESP),
+            .M_BVALID (M_AXI_GP1_BVALID),
+            .M_BREADY (M_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .M_ARID    (M_AXI_GP1_ARID_FULL),
+            .M_ARADDR  (M_AXI_GP1_ARADDR),
+            .M_ARLEN   (M_AXI_GP1_ARLEN),
+            .M_ARSIZE  (M_AXI_GP1_ARSIZE),
+            .M_ARBURST (M_AXI_GP1_ARBURST),
+            .M_ARLOCK  (M_AXI_GP1_ARLOCK),
+            .M_ARCACHE (M_AXI_GP1_ARCACHE),
+            .M_ARPROT  (M_AXI_GP1_ARPROT),
+            .M_ARVALID (M_AXI_GP1_ARVALID),
+            .M_ARREADY (M_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .M_RID    (M_AXI_GP1_RID_FULL),
+            .M_RDATA  (M_AXI_GP1_RDATA),
+            .M_RRESP  (M_AXI_GP1_RRESP),
+            .M_RLAST  (M_AXI_GP1_RLAST),
+            .M_RVALID (M_AXI_GP1_RVALID),
+            .M_RREADY (M_AXI_GP1_RREADY),
+            // Side band signals 
+            .M_AWQOS  (M_AXI_GP1_AWQOS),
+            .M_ARQOS  (M_AXI_GP1_ARQOS)
+           );
+
+/* AXI Slave GP0 */
+  processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP0, /// enable
+              axi_sgp0_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP0_BASEADDR,//// base address
+              C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access not supported
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
+            .S_ACLK   (S_AXI_GP0_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP0_AWID),
+            .S_AWADDR  (S_AXI_GP0_AWADDR),
+            .S_AWLEN   (S_AXI_GP0_AWLEN),
+            .S_AWSIZE  (S_AXI_GP0_AWSIZE),
+            .S_AWBURST (S_AXI_GP0_AWBURST),
+            .S_AWLOCK  (S_AXI_GP0_AWLOCK),
+            .S_AWCACHE (S_AXI_GP0_AWCACHE),
+            .S_AWPROT  (S_AXI_GP0_AWPROT),
+            .S_AWVALID (S_AXI_GP0_AWVALID),
+            .S_AWREADY (S_AXI_GP0_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP0_WID),
+            .S_WDATA  (S_AXI_GP0_WDATA),
+            .S_WSTRB  (S_AXI_GP0_WSTRB), 
+            .S_WLAST  (S_AXI_GP0_WLAST), 
+            .S_WVALID (S_AXI_GP0_WVALID),
+            .S_WREADY (S_AXI_GP0_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP0_BID),
+            .S_BRESP  (S_AXI_GP0_BRESP),
+            .S_BVALID (S_AXI_GP0_BVALID),
+            .S_BREADY (S_AXI_GP0_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP0_ARID),
+            .S_ARADDR  (S_AXI_GP0_ARADDR),
+            .S_ARLEN   (S_AXI_GP0_ARLEN),
+            .S_ARSIZE  (S_AXI_GP0_ARSIZE),
+            .S_ARBURST (S_AXI_GP0_ARBURST),
+            .S_ARLOCK  (S_AXI_GP0_ARLOCK),
+            .S_ARCACHE (S_AXI_GP0_ARCACHE),
+            .S_ARPROT  (S_AXI_GP0_ARPROT),
+            .S_ARVALID (S_AXI_GP0_ARVALID),
+            .S_ARREADY (S_AXI_GP0_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP0_RID),
+            .S_RDATA  (S_AXI_GP0_RDATA),
+            .S_RRESP  (S_AXI_GP0_RRESP),
+            .S_RLAST  (S_AXI_GP0_RLAST),
+            .S_RVALID (S_AXI_GP0_RVALID),
+            .S_RREADY (S_AXI_GP0_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP0_AWQOS),
+            .S_ARQOS  (S_AXI_GP0_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
+            .WR_DATA  (net_wr_data_gp0), 
+            .WR_DATA_STRB  (net_wr_strb_gp0), 
+            .WR_ADDR  (net_wr_addr_gp0), 
+            .WR_BYTES  (net_wr_bytes_gp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp0), 
+            .WR_QOS (net_wr_qos_gp0),
+            .RD_REQ_DDR (net_rd_req_ddr_gp0),
+            .RD_REQ_OCM (net_rd_req_ocm_gp0),
+            .RD_REQ_REG (net_rd_req_reg_gp0),
+            .RD_ADDR (net_rd_addr_gp0),
+            .RD_DATA_DDR (net_rd_data_ddr_gp0),
+            .RD_DATA_OCM (net_rd_data_ocm_gp0),
+            .RD_DATA_REG (net_rd_data_reg_gp0),
+            .RD_BYTES (net_rd_bytes_gp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
+            .RD_QOS (net_rd_qos_gp0)
+
+);
+
+/* AXI Slave GP1 */
+  processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP1, /// enable
+              axi_sgp1_name, //name
+              axi_sgp_data_width, /// data width
+              addr_width, /// address width
+              axi_sgp_id_width,  /// ID width
+              C_S_AXI_GP1_BASEADDR,//// base address
+              C_S_AXI_GP1_HIGHADDR,/// HIGh_addr 
+              axi_sgp_outstanding, // outstanding transactions
+              axi_slv_excl_support, // exclusive access
+              axi_sgp_wr_outstanding,
+              axi_sgp_rd_outstanding)
+  S_AXI_GP1(.S_RESETN  (net_axi_gp1_rstn),
+            .S_ACLK    (S_AXI_GP1_ACLK),
+            // Write Address Channel
+            .S_AWID    (S_AXI_GP1_AWID),
+            .S_AWADDR  (S_AXI_GP1_AWADDR),
+            .S_AWLEN   (S_AXI_GP1_AWLEN),
+            .S_AWSIZE  (S_AXI_GP1_AWSIZE),
+            .S_AWBURST (S_AXI_GP1_AWBURST),
+            .S_AWLOCK  (S_AXI_GP1_AWLOCK),
+            .S_AWCACHE (S_AXI_GP1_AWCACHE),
+            .S_AWPROT  (S_AXI_GP1_AWPROT),
+            .S_AWVALID (S_AXI_GP1_AWVALID),
+            .S_AWREADY (S_AXI_GP1_AWREADY),
+            // Write Data Channel Signals.
+            .S_WID    (S_AXI_GP1_WID),
+            .S_WDATA  (S_AXI_GP1_WDATA),
+            .S_WSTRB  (S_AXI_GP1_WSTRB), 
+            .S_WLAST  (S_AXI_GP1_WLAST), 
+            .S_WVALID (S_AXI_GP1_WVALID),
+            .S_WREADY (S_AXI_GP1_WREADY),
+            // Write Response Channel Signals.
+            .S_BID    (S_AXI_GP1_BID),
+            .S_BRESP  (S_AXI_GP1_BRESP),
+            .S_BVALID (S_AXI_GP1_BVALID),
+            .S_BREADY (S_AXI_GP1_BREADY),
+            // Read Address Channel Signals.
+            .S_ARID    (S_AXI_GP1_ARID),
+            .S_ARADDR  (S_AXI_GP1_ARADDR),
+            .S_ARLEN   (S_AXI_GP1_ARLEN),
+            .S_ARSIZE  (S_AXI_GP1_ARSIZE),
+            .S_ARBURST (S_AXI_GP1_ARBURST),
+            .S_ARLOCK  (S_AXI_GP1_ARLOCK),
+            .S_ARCACHE (S_AXI_GP1_ARCACHE),
+            .S_ARPROT  (S_AXI_GP1_ARPROT),
+            .S_ARVALID (S_AXI_GP1_ARVALID),
+            .S_ARREADY (S_AXI_GP1_ARREADY),
+            // Read Data Channel Signals.
+            .S_RID    (S_AXI_GP1_RID),
+            .S_RDATA  (S_AXI_GP1_RDATA),
+            .S_RRESP  (S_AXI_GP1_RRESP),
+            .S_RLAST  (S_AXI_GP1_RLAST),
+            .S_RVALID (S_AXI_GP1_RVALID),
+            .S_RREADY (S_AXI_GP1_RREADY),
+            // Side band signals 
+            .S_AWQOS  (S_AXI_GP1_AWQOS),
+            .S_ARQOS  (S_AXI_GP1_ARQOS),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
+            .WR_DATA  (net_wr_data_gp1), 
+            .WR_DATA_STRB  (net_wr_strb_gp1), 
+            .WR_ADDR  (net_wr_addr_gp1), 
+            .WR_BYTES  (net_wr_bytes_gp1), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_gp1), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_gp1), 
+            .WR_QOS (net_wr_qos_gp1),
+            .RD_REQ_OCM (net_rd_req_ocm_gp1),
+            .RD_REQ_DDR (net_rd_req_ddr_gp1),
+            .RD_REQ_REG (net_rd_req_reg_gp1),
+            .RD_ADDR (net_rd_addr_gp1),
+            .RD_DATA_DDR (net_rd_data_ddr_gp1),
+            .RD_DATA_OCM (net_rd_data_ocm_gp1),
+            .RD_DATA_REG (net_rd_data_reg_gp1),
+            .RD_BYTES (net_rd_bytes_gp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
+            .RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
+            .RD_QOS (net_rd_qos_gp1)
+
+);

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8c62/hdl/processing_system7_vip_v1_0_7_axi_hp.v

@@ -0,0 +1,350 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_7_axi_hp.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Connections for AXI HP ports
+ *
+ *****************************************************************************/
+
+/* AXI Slave HP0 */  
+ processing_system7_vip_v1_0_7_afi_slave #(  C_USE_S_AXI_HP0, // enable
+               axi_hp0_name, // name
+               C_S_AXI_HP0_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP0_BASEADDR, // slave base address
+               C_S_AXI_HP0_HIGHADDR, // slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+  S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
+            .S_ACLK   (S_AXI_HP0_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP0_AWID),
+            .S_AWADDR  (S_AXI_HP0_AWADDR),
+            .S_AWLEN   (S_AXI_HP0_AWLEN),
+            .S_AWSIZE  (S_AXI_HP0_AWSIZE),
+            .S_AWBURST (S_AXI_HP0_AWBURST),
+            .S_AWLOCK  (S_AXI_HP0_AWLOCK),
+            .S_AWCACHE (S_AXI_HP0_AWCACHE),
+            .S_AWPROT  (S_AXI_HP0_AWPROT),
+            .S_AWVALID (S_AXI_HP0_AWVALID),
+            .S_AWREADY (S_AXI_HP0_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP0_WID),
+            .S_WDATA  (S_AXI_HP0_WDATA),
+            .S_WSTRB  (S_AXI_HP0_WSTRB), 
+            .S_WLAST  (S_AXI_HP0_WLAST), 
+            .S_WVALID (S_AXI_HP0_WVALID),
+            .S_WREADY (S_AXI_HP0_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP0_BID),
+            .S_BRESP  (S_AXI_HP0_BRESP),
+            .S_BVALID (S_AXI_HP0_BVALID),
+            .S_BREADY (S_AXI_HP0_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP0_ARID),
+            .S_ARADDR  (S_AXI_HP0_ARADDR),
+            .S_ARLEN   (S_AXI_HP0_ARLEN),
+            .S_ARSIZE  (S_AXI_HP0_ARSIZE),
+            .S_ARBURST (S_AXI_HP0_ARBURST),
+            .S_ARLOCK  (S_AXI_HP0_ARLOCK),
+            .S_ARCACHE (S_AXI_HP0_ARCACHE),
+            .S_ARPROT  (S_AXI_HP0_ARPROT),
+            .S_ARVALID (S_AXI_HP0_ARVALID),
+            .S_ARREADY (S_AXI_HP0_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP0_RID),
+            .S_RDATA  (S_AXI_HP0_RDATA),
+            .S_RRESP  (S_AXI_HP0_RRESP),
+            .S_RLAST  (S_AXI_HP0_RLAST),
+            .S_RVALID (S_AXI_HP0_RVALID),
+            .S_RREADY (S_AXI_HP0_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP0_AWQOS), 
+            .S_ARQOS  (S_AXI_HP0_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP0_RCOUNT),
+            .S_WCOUNT (S_AXI_HP0_WCOUNT),
+            .S_RACOUNT (S_AXI_HP0_RACOUNT),
+            .S_WACOUNT (S_AXI_HP0_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
+            .WR_DATA  (net_wr_data_hp0), 
+            .WR_DATA_STRB  (net_wr_strb_hp0), 
+            .WR_ADDR  (net_wr_addr_hp0), 
+            .WR_BYTES (net_wr_bytes_hp0), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp0), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp0), 
+            .WR_QOS (net_wr_qos_hp0),
+            .RD_REQ_DDR (net_rd_req_ddr_hp0),
+            .RD_REQ_OCM (net_rd_req_ocm_hp0),
+            .RD_ADDR (net_rd_addr_hp0),
+            .RD_DATA_DDR (net_rd_data_ddr_hp0),
+            .RD_DATA_OCM (net_rd_data_ocm_hp0),
+            .RD_BYTES (net_rd_bytes_hp0),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
+            .RD_QOS (net_rd_qos_hp0)
+ );
+
+/* AXI Slave HP1 */  
+ processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP1, // enable
+               axi_hp1_name, // name
+               C_S_AXI_HP1_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP1_BASEADDR, // slave base address
+               C_S_AXI_HP1_HIGHADDR, // Slave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
+            .S_ACLK   (S_AXI_HP1_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP1_AWID),
+            .S_AWADDR  (S_AXI_HP1_AWADDR),
+            .S_AWLEN   (S_AXI_HP1_AWLEN),
+            .S_AWSIZE  (S_AXI_HP1_AWSIZE),
+            .S_AWBURST (S_AXI_HP1_AWBURST),
+            .S_AWLOCK  (S_AXI_HP1_AWLOCK),
+            .S_AWCACHE (S_AXI_HP1_AWCACHE),
+            .S_AWPROT  (S_AXI_HP1_AWPROT),
+            .S_AWVALID (S_AXI_HP1_AWVALID),
+            .S_AWREADY (S_AXI_HP1_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP1_WID),
+            .S_WDATA  (S_AXI_HP1_WDATA),
+            .S_WSTRB  (S_AXI_HP1_WSTRB), 
+            .S_WLAST  (S_AXI_HP1_WLAST), 
+            .S_WVALID (S_AXI_HP1_WVALID),
+            .S_WREADY (S_AXI_HP1_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP1_BID),
+            .S_BRESP  (S_AXI_HP1_BRESP),
+            .S_BVALID (S_AXI_HP1_BVALID),
+            .S_BREADY (S_AXI_HP1_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP1_ARID),
+            .S_ARADDR  (S_AXI_HP1_ARADDR),
+            .S_ARLEN   (S_AXI_HP1_ARLEN),
+            .S_ARSIZE  (S_AXI_HP1_ARSIZE),
+            .S_ARBURST (S_AXI_HP1_ARBURST),
+            .S_ARLOCK  (S_AXI_HP1_ARLOCK),
+            .S_ARCACHE (S_AXI_HP1_ARCACHE),
+            .S_ARPROT  (S_AXI_HP1_ARPROT),
+            .S_ARVALID (S_AXI_HP1_ARVALID),
+            .S_ARREADY (S_AXI_HP1_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP1_RID),
+            .S_RDATA  (S_AXI_HP1_RDATA),
+            .S_RRESP  (S_AXI_HP1_RRESP),
+            .S_RLAST  (S_AXI_HP1_RLAST),
+            .S_RVALID (S_AXI_HP1_RVALID),
+            .S_RREADY (S_AXI_HP1_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP1_AWQOS), 
+            .S_ARQOS  (S_AXI_HP1_ARQOS), 
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP1_RCOUNT),
+            .S_WCOUNT (S_AXI_HP1_WCOUNT),
+            .S_RACOUNT (S_AXI_HP1_RACOUNT),
+            .S_WACOUNT (S_AXI_HP1_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
+            .WR_DATA  (net_wr_data_hp1), 
+			.WR_DATA_STRB  (net_wr_strb_hp1),
+            .WR_ADDR  (net_wr_addr_hp1), 
+            .WR_BYTES (net_wr_bytes_hp1), 
+            .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), 
+            .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), 
+            .WR_QOS (net_wr_qos_hp1),
+            .RD_REQ_DDR (net_rd_req_ddr_hp1),
+            .RD_REQ_OCM (net_rd_req_ocm_hp1),
+            .RD_ADDR (net_rd_addr_hp1),
+            .RD_DATA_DDR (net_rd_data_ddr_hp1),
+            .RD_DATA_OCM (net_rd_data_ocm_hp1),
+            .RD_BYTES (net_rd_bytes_hp1),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
+            .RD_QOS (net_rd_qos_hp1)
+
+  );
+
+/* AXI Slave HP2 */  
+ processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP2, // enable
+               axi_hp2_name, // name
+               C_S_AXI_HP2_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP2_BASEADDR, // slave base address
+               C_S_AXI_HP2_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
+            .S_ACLK    (S_AXI_HP2_ACLK),
+            // Write Address channel
+            .S_AWID    (S_AXI_HP2_AWID),
+            .S_AWADDR  (S_AXI_HP2_AWADDR),
+            .S_AWLEN   (S_AXI_HP2_AWLEN),
+            .S_AWSIZE  (S_AXI_HP2_AWSIZE),
+            .S_AWBURST (S_AXI_HP2_AWBURST),
+            .S_AWLOCK  (S_AXI_HP2_AWLOCK),
+            .S_AWCACHE (S_AXI_HP2_AWCACHE),
+            .S_AWPROT  (S_AXI_HP2_AWPROT),
+            .S_AWVALID (S_AXI_HP2_AWVALID),
+            .S_AWREADY (S_AXI_HP2_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP2_WID),
+            .S_WDATA  (S_AXI_HP2_WDATA),
+            .S_WSTRB  (S_AXI_HP2_WSTRB), 
+            .S_WLAST  (S_AXI_HP2_WLAST), 
+            .S_WVALID (S_AXI_HP2_WVALID),
+            .S_WREADY (S_AXI_HP2_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP2_BID),
+            .S_BRESP  (S_AXI_HP2_BRESP),
+            .S_BVALID (S_AXI_HP2_BVALID),
+            .S_BREADY (S_AXI_HP2_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP2_ARID),
+            .S_ARADDR  (S_AXI_HP2_ARADDR),
+            .S_ARLEN   (S_AXI_HP2_ARLEN),
+            .S_ARSIZE  (S_AXI_HP2_ARSIZE),
+            .S_ARBURST (S_AXI_HP2_ARBURST),
+            .S_ARLOCK  (S_AXI_HP2_ARLOCK),
+            .S_ARCACHE (S_AXI_HP2_ARCACHE),
+            .S_ARPROT  (S_AXI_HP2_ARPROT),
+            .S_ARVALID (S_AXI_HP2_ARVALID),
+            .S_ARREADY (S_AXI_HP2_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP2_RID),
+            .S_RDATA  (S_AXI_HP2_RDATA),
+            .S_RRESP  (S_AXI_HP2_RRESP),
+            .S_RLAST  (S_AXI_HP2_RLAST),
+            .S_RVALID (S_AXI_HP2_RVALID),
+            .S_RREADY (S_AXI_HP2_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP2_AWQOS), 
+            .S_ARQOS  (S_AXI_HP2_ARQOS), 
+             // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP2_RCOUNT),
+            .S_WCOUNT (S_AXI_HP2_WCOUNT),
+            .S_RACOUNT (S_AXI_HP2_RACOUNT),
+            .S_WACOUNT (S_AXI_HP2_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
+            .WR_DATA  (net_wr_data_hp2), 
+			.WR_DATA_STRB  (net_wr_strb_hp2),
+            .WR_ADDR  (net_wr_addr_hp2), 
+            .WR_BYTES (net_wr_bytes_hp2), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp2), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp2), 
+            .WR_QOS (net_wr_qos_hp2),
+            .RD_REQ_DDR (net_rd_req_ddr_hp2),
+            .RD_REQ_OCM (net_rd_req_ocm_hp2),
+            .RD_ADDR (net_rd_addr_hp2),
+            .RD_DATA_DDR (net_rd_data_ddr_hp2),
+            .RD_DATA_OCM (net_rd_data_ocm_hp2),
+            .RD_BYTES (net_rd_bytes_hp2),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
+            .RD_QOS (net_rd_qos_hp2)
+
+ );
+
+/* AXI Slave HP3 */  
+ processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP3, // enable
+               axi_hp3_name, // name
+               C_S_AXI_HP3_DATA_WIDTH, // data width
+               addr_width, /// address width
+               axi_hp_id_width, // ID width
+               C_S_AXI_HP3_BASEADDR, // slave base address
+               C_S_AXI_HP3_HIGHADDR, // SLave size
+               axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
+               axi_slv_excl_support) // Exclusive access support
+ S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
+            .S_ACLK   (S_AXI_HP3_ACLK),
+            // Write ADDRESS CHANNEL
+            .S_AWID    (S_AXI_HP3_AWID),
+            .S_AWADDR  (S_AXI_HP3_AWADDR),
+            .S_AWLEN   (S_AXI_HP3_AWLEN),
+            .S_AWSIZE  (S_AXI_HP3_AWSIZE),
+            .S_AWBURST (S_AXI_HP3_AWBURST),
+            .S_AWLOCK  (S_AXI_HP3_AWLOCK),
+            .S_AWCACHE (S_AXI_HP3_AWCACHE),
+            .S_AWPROT  (S_AXI_HP3_AWPROT),
+            .S_AWVALID (S_AXI_HP3_AWVALID),
+            .S_AWREADY (S_AXI_HP3_AWREADY),
+            // Write Data channel signals.
+            .S_WID    (S_AXI_HP3_WID),
+            .S_WDATA  (S_AXI_HP3_WDATA),
+            .S_WSTRB  (S_AXI_HP3_WSTRB), 
+            .S_WLAST  (S_AXI_HP3_WLAST), 
+            .S_WVALID (S_AXI_HP3_WVALID),
+            .S_WREADY (S_AXI_HP3_WREADY),
+            // Write Response channel signals.
+            .S_BID    (S_AXI_HP3_BID),
+            .S_BRESP  (S_AXI_HP3_BRESP),
+            .S_BVALID (S_AXI_HP3_BVALID),
+            .S_BREADY (S_AXI_HP3_BREADY),
+            // Read Address channel signals.
+            .S_ARID    (S_AXI_HP3_ARID),
+            .S_ARADDR  (S_AXI_HP3_ARADDR),
+            .S_ARLEN   (S_AXI_HP3_ARLEN),
+            .S_ARSIZE  (S_AXI_HP3_ARSIZE),
+            .S_ARBURST (S_AXI_HP3_ARBURST),
+            .S_ARLOCK  (S_AXI_HP3_ARLOCK),
+            .S_ARCACHE (S_AXI_HP3_ARCACHE),
+            .S_ARPROT  (S_AXI_HP3_ARPROT),
+            .S_ARVALID (S_AXI_HP3_ARVALID),
+            .S_ARREADY (S_AXI_HP3_ARREADY),
+            // Read Data channel signals.
+            .S_RID    (S_AXI_HP3_RID),
+            .S_RDATA  (S_AXI_HP3_RDATA),
+            .S_RRESP  (S_AXI_HP3_RRESP),
+            .S_RLAST  (S_AXI_HP3_RLAST),
+            .S_RVALID (S_AXI_HP3_RVALID),
+            .S_RREADY (S_AXI_HP3_RREADY),
+            // Side band signals
+            .S_AWQOS  (S_AXI_HP3_AWQOS), 
+            .S_ARQOS  (S_AXI_HP3_ARQOS),
+            // these are needed only for HP ports
+            .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
+            .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
+            .S_RCOUNT (S_AXI_HP3_RCOUNT),
+            .S_WCOUNT (S_AXI_HP3_WCOUNT),
+            .S_RACOUNT (S_AXI_HP3_RACOUNT),
+            .S_WACOUNT (S_AXI_HP3_WACOUNT),
+
+            .SW_CLK   (net_sw_clk),
+            .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
+            .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
+            .WR_DATA  (net_wr_data_hp3), 
+			.WR_DATA_STRB  (net_wr_strb_hp3),
+            .WR_ADDR  (net_wr_addr_hp3), 
+            .WR_BYTES (net_wr_bytes_hp3), 
+            .WR_DATA_VALID_DDR  (net_wr_dv_ddr_hp3), 
+            .WR_DATA_VALID_OCM  (net_wr_dv_ocm_hp3), 
+            .WR_QOS (net_wr_qos_hp3),
+            .RD_REQ_DDR (net_rd_req_ddr_hp3),
+            .RD_REQ_OCM (net_rd_req_ocm_hp3),
+            .RD_ADDR (net_rd_addr_hp3),
+            .RD_DATA_DDR (net_rd_data_ddr_hp3),
+            .RD_DATA_OCM (net_rd_data_ocm_hp3),
+            .RD_BYTES (net_rd_bytes_hp3),
+            .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
+            .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
+            .RD_QOS (net_rd_qos_hp3)
+ );

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8c62/hdl/processing_system7_vip_v1_0_7_local_params.v

@@ -0,0 +1,244 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_7_local_params.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Parameters used in Zynq VIP
+ *
+ *****************************************************************************/
+
+
+/* local */ 
+parameter m_axi_gp0_baseaddr = 32'h4000_0000;
+parameter m_axi_gp1_baseaddr = 32'h8000_0000;
+parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
+parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
+
+parameter addr_width = 32;   // maximum address width
+parameter data_width = 32;   // maximum data width.
+parameter max_chars  = 128;  // max characters for file name
+parameter mem_width  = data_width/8; /// memory width in bytes
+parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
+parameter int_width  = 32; //integre width
+
+/* for internal read/write APIs used for data transfers */
+parameter max_burst_len   = 16;  /// maximum brst length on axi 
+parameter max_data_width  = 64; // maximum data width for internal AXI bursts 
+parameter max_burst_bits  = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts 
+parameter max_burst_bytes = (max_burst_bits)/8;                // maximum data bytes in each transfer 
+parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts 
+
+parameter max_registers   = 32;
+parameter max_regs_width  = clogb2(max_registers);
+
+parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11; 
+
+/* Interrupt bits supported */
+parameter irq_width = 16;
+
+/* GP Master0 & Master1 address decode */
+parameter GP_M0 = 2'b01;
+parameter GP_M1 = 2'b10;
+
+parameter ALL_RANDOM= 2'b00;
+parameter ALL_ZEROS = 2'b01;
+parameter ALL_ONES  = 2'b10;
+
+parameter ddr_start_addr = 32'h0008_0000;
+parameter ddr_end_addr   = 32'h7FFF_FFFF;
+
+parameter ocm_start_addr = 32'h0000_0000;
+parameter ocm_end_addr   = 32'h0003_FFFF;
+parameter high_ocm_start_addr = 32'hFFFC_0000;
+parameter high_ocm_end_addr   = 32'hFFFF_FFFF;
+parameter ocm_low_addr   = 32'hFFFF_0000;
+
+parameter reg_start_addr = 32'hE000_0000;
+parameter reg_end_addr   = 32'hF8F0_2F80;
+
+
+/* for Master port APIs and AXI protocol related signal widths*/
+parameter axi_burst_len  = 16;
+parameter axi_len_width  = clogb2(axi_burst_len);
+parameter axi_size_width = 3;
+parameter axi_brst_type_width = 2;
+parameter axi_lock_width = 2;
+parameter axi_cache_width = 4;
+parameter axi_prot_width = 3;
+parameter axi_rsp_width = 2;
+parameter axi_mgp_data_width = 32;
+parameter axi_mgp_id_width   = 12;
+parameter axi_mgp_outstanding = 8;
+parameter axi_mgp_wr_id = 12'hC00;
+parameter axi_mgp_rd_id = 12'hC0C;
+parameter axi_mgp0_name  = "M_AXI_GP0";
+parameter axi_mgp1_name  = "M_AXI_GP1";
+parameter axi_qos_width  = 4;
+parameter max_transfer_bytes = 256; // For Master APIs.
+parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
+
+
+/* for GP slave ports*/
+parameter axi_sgp_data_width = 32;
+parameter axi_sgp_id_width   = 6;
+parameter axi_sgp_rd_outstanding = 8;
+parameter axi_sgp_wr_outstanding = 8;
+parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
+parameter axi_sgp0_name  = "S_AXI_GP0";
+parameter axi_sgp1_name  = "S_AXI_GP1";
+
+/* for ACP slave ports*/
+parameter axi_acp_data_width = 64;
+parameter axi_acp_id_width   = 3;
+parameter axi_acp_rd_outstanding = 7;
+parameter axi_acp_wr_outstanding = 3;
+parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
+parameter axi_acp_name  = "S_AXI_ACP";
+
+/* for HP slave ports*/
+parameter axi_hp_id_width   = 6;
+parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
+parameter axi_hp0_name  = "S_AXI_HP0";
+parameter axi_hp1_name  = "S_AXI_HP1";
+parameter axi_hp2_name  = "S_AXI_HP2";
+parameter axi_hp3_name  = "S_AXI_HP3";
+
+
+parameter axi_slv_excl_support = 0; // For Slave  ports EXCL access is not supported
+parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
+
+/* AXI transfer types */
+parameter AXI_FIXED = 2'b00;
+parameter AXI_INCR  = 2'b01;
+parameter AXI_WRAP  = 2'b10;
+
+/* Exclusive Access */
+parameter AXI_NRML  = 2'b00;
+parameter AXI_EXCL  = 2'b01;
+parameter AXI_LOCK  = 2'b10;
+
+/* AXI Response types */
+parameter AXI_OK = 2'b00;
+parameter AXI_EXCL_OK  = 2'b01;
+parameter AXI_SLV_ERR  = 2'b10;
+parameter AXI_DEC_ERR  = 2'b11;
+
+function automatic integer clogb2;
+  input [31:0] value;
+  begin
+      value = value - 1;
+      for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
+          value = value >> 1;
+      end
+  end
+endfunction
+
+/* needed only for AFI modules  and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
+  /* WR FIFO data */
+  // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
+  // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
+  // parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
+  // parameter wr_bytes_lsb = 0;
+  // parameter wr_bytes_msb = max_burst_bytes_width;
+  // parameter wr_addr_lsb  = wr_bytes_msb + 1;
+  // parameter wr_addr_msb  = wr_addr_lsb + addr_width-1;
+  // parameter wr_data_lsb  = wr_addr_msb + 1;
+  // parameter wr_data_msb  = wr_data_lsb + max_burst_bits-1;
+  // parameter wr_data_msb  = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
+  // parameter wr_qos_lsb   = wr_data_msb + 1;
+  // `parameter wr_qos_msb   = wr_qos_lsb + axi_qos_width-1;
+ 
+  /* WR AFI FIFO data */ 
+    /* ID -  1071:1066
+     Resp - 1065:1064
+     data - 1063:40   
+     address - 39:8
+     valid_bytes - 7:0
+    */
+  // parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
+  // parameter wr_afi_bytes_lsb = 0;
+  // parameter wr_afi_bytes_msb = max_burst_bytes_width;
+  // parameter wr_afi_addr_lsb  = wr_afi_bytes_msb + 1;
+  // parameter wr_afi_addr_msb  = wr_afi_addr_lsb + addr_width-1;
+  // parameter wr_afi_data_lsb  = wr_afi_addr_msb + 1;
+  // parameter wr_afi_rsp_msb   = wr_afi_rsp_lsb + axi_rsp_width-1; 
+  // parameter wr_afi_id_lsb    = wr_afi_rsp_msb + 1; 
+  // parameter wr_afi_id_msb    = wr_afi_id_lsb + axi_hp_id_width-1; 
+  // parameter wr_afi_ln_lsb    = wr_afi_id_msb + 1;
+  // parameter wr_afi_ln_msb    = wr_afi_ln_lsb + axi_len_width-1;
+  // parameter wr_afi_qos_lsb   = wr_afi_ln_msb + 1;
+  // parameter wr_afi_qos_msb   = wr_afi_qos_lsb + axi_qos_width-1;
+
+
+  parameter afi_fifo_size    = 1024; /// AFI FIFO is stored as 1024-bytes 
+  parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
+  parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
+
+/* for interconnect fifo models */
+  parameter intr_max_outstanding = 8;
+  parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
+  parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width +  axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
+  parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
+
+  //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
+  parameter rd_afi_bytes_lsb = 0;
+  parameter rd_afi_bytes_msb = max_burst_bytes_width;
+  parameter rd_afi_rsp_lsb   = rd_afi_bytes_msb + 1; 
+  parameter rd_afi_rsp_msb   = rd_afi_rsp_lsb + axi_rsp_width-1; 
+  parameter rd_afi_id_lsb    = rd_afi_rsp_msb + 1; 
+  parameter rd_afi_id_msb    = rd_afi_id_lsb + axi_hp_id_width-1; 
+  parameter rd_afi_ln_lsb    = rd_afi_id_msb + 1;
+  parameter rd_afi_ln_msb    = rd_afi_ln_lsb + axi_len_width-1;
+  parameter rd_afi_brst_lsb  = rd_afi_ln_msb + 1;
+  parameter rd_afi_brst_msb  = rd_afi_brst_lsb + axi_brst_type_width-1;
+  parameter rd_afi_siz_lsb   = rd_afi_brst_msb + 1;
+  parameter rd_afi_siz_msb   = rd_afi_siz_lsb + axi_size_width-1;
+  parameter rd_afi_addr_lsb  = rd_afi_siz_msb + 1;
+  parameter rd_afi_addr_msb  = rd_afi_addr_lsb + addr_width-1;
+  parameter rd_afi_data_lsb  = rd_afi_addr_msb + 1;
+  parameter rd_afi_data_msb  = rd_afi_data_lsb + max_burst_bits-1; 
+
+
+/* Latency types */
+ parameter BEST_CASE  = 0;
+ parameter AVG_CASE   = 1;
+ parameter WORST_CASE = 2;
+ parameter RANDOM_CASE  = 3;
+
+/* Latency Parameters ACP  */
+  parameter acp_wr_min   =  21;
+  parameter acp_wr_avg   =  16;
+  parameter acp_wr_max   =  27;
+  parameter acp_rd_min   =  34;
+  parameter acp_rd_avg   =  125;
+  parameter acp_rd_max   =  130; 
+
+/* Latency Parameters GP  */
+  parameter gp_wr_min   =  21;
+  parameter gp_wr_avg   =  16;
+  parameter gp_wr_max   =  46;
+  parameter gp_rd_min   =  38;
+  parameter gp_rd_avg   =  125;
+  parameter gp_rd_max   =  130; 
+
+/* Latency Parameters HP  */
+  parameter afi_wr_min  =  37;
+  parameter afi_wr_avg  =  41;
+  parameter afi_wr_max  =  42;
+  parameter afi_rd_min  =  41;
+  parameter afi_rd_avg  =  221;
+  parameter afi_rd_max  =  229; 
+
+/* ID VALID and INVALID */
+  parameter secure_access_enabled = 0;
+  parameter id_invalid = 0;
+  parameter id_valid = 1;
+
+/* Display */
+  parameter DISP_INFO = "*ZYNQ_VIP_INFO";
+  parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
+  parameter DISP_ERR  = "*ZYNQ_VIP_ERROR";
+  parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
+
+  parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8c62/hdl/processing_system7_vip_v1_0_7_unused_ports.v

@@ -0,0 +1,433 @@
+/*****************************************************************************
+ * File : processing_system7_vip_v1_0_7_unused_ports.v
+ *
+ * Date : 2012-11
+ *
+ * Description : Semantic checks for unused ports.
+ *
+ *****************************************************************************/
+
+/* CAN */
+assign CAN0_PHY_TX = 0;
+assign CAN1_PHY_TX = 0;
+always @(CAN0_PHY_RX or CAN1_PHY_RX)
+begin 
+ if(CAN0_PHY_RX | CAN1_PHY_RX)
+  $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* ETHERNET */
+/* ------------------------------------------- */
+
+assign ENET0_GMII_TX_EN = 0;
+assign ENET0_GMII_TX_ER = 0;
+assign ENET0_MDIO_MDC = 0;
+assign ENET0_MDIO_O = 0; /// confirm
+assign ENET0_MDIO_T = 0;
+assign ENET0_PTP_DELAY_REQ_RX = 0;
+assign ENET0_PTP_DELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_REQ_RX = 0;
+assign ENET0_PTP_PDELAY_REQ_TX = 0;
+assign ENET0_PTP_PDELAY_RESP_RX = 0;
+assign ENET0_PTP_PDELAY_RESP_TX = 0;
+assign ENET0_PTP_SYNC_FRAME_RX = 0;
+assign ENET0_PTP_SYNC_FRAME_TX = 0;
+assign ENET0_SOF_RX = 0;
+assign ENET0_SOF_TX = 0;
+assign ENET0_GMII_TXD = 0;
+always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or 
+        ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
+        ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
+begin 
+ if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | 
+        ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
+        ENET0_GMII_TX_CLK | ENET0_MDIO_I )
+  $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
+end
+
+assign ENET1_GMII_TX_EN = 0;
+assign ENET1_GMII_TX_ER = 0;
+assign ENET1_MDIO_MDC = 0;
+assign ENET1_MDIO_O = 0;/// confirm
+assign ENET1_MDIO_T = 0;
+assign ENET1_PTP_DELAY_REQ_RX = 0;
+assign ENET1_PTP_DELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_REQ_RX = 0;
+assign ENET1_PTP_PDELAY_REQ_TX = 0;
+assign ENET1_PTP_PDELAY_RESP_RX = 0;
+assign ENET1_PTP_PDELAY_RESP_TX = 0;
+assign ENET1_PTP_SYNC_FRAME_RX = 0;
+assign ENET1_PTP_SYNC_FRAME_TX = 0;
+assign ENET1_SOF_RX = 0;
+assign ENET1_SOF_TX = 0;
+assign ENET1_GMII_TXD = 0;
+always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or 
+        ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
+        ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
+begin 
+ if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | 
+        ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
+        ENET1_GMII_TX_CLK | ENET1_MDIO_I )
+  $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* GPIO */
+/* ------------------------------------------- */
+
+assign GPIO_O = 0;
+assign GPIO_T = 0;
+always@(GPIO_I)
+begin
+// if(GPIO_I !== 0)
+// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* I2C */
+/* ------------------------------------------- */
+
+assign I2C0_SDA_O = 0;
+assign I2C0_SDA_T = 0;
+assign I2C0_SCL_O = 0;
+assign I2C0_SCL_T = 0;
+assign I2C1_SDA_O = 0;
+assign I2C1_SDA_T = 0;
+assign I2C1_SCL_O = 0;
+assign I2C1_SCL_T = 0;
+always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
+begin
+ if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
+  $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* JTAG  */
+/* ------------------------------------------- */
+
+assign PJTAG_TD_T = 0;
+assign PJTAG_TD_O = 0;
+always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
+begin
+ if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
+  $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SDIO  */
+/* ------------------------------------------- */
+
+assign SDIO0_CLK = 0;
+assign SDIO0_CMD_O = 0;
+assign SDIO0_CMD_T = 0;
+assign SDIO0_DATA_O = 0;
+assign SDIO0_DATA_T = 0;
+assign SDIO0_LED = 0;
+assign SDIO0_BUSPOW = 0;
+assign SDIO0_BUSVOLT = 0;
+always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
+begin
+ if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
+  $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
+end
+
+assign SDIO1_CLK = 0;
+assign SDIO1_CMD_O = 0;
+assign SDIO1_CMD_T = 0;
+assign SDIO1_DATA_O = 0;
+assign SDIO1_DATA_T = 0;
+assign SDIO1_LED = 0;
+assign SDIO1_BUSPOW = 0;
+assign SDIO1_BUSVOLT = 0;
+always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
+begin
+ if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
+  $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* SPI  */
+/* ------------------------------------------- */
+
+assign SPI0_SCLK_O = 0;
+assign SPI0_SCLK_T = 0;
+assign SPI0_MOSI_O = 0;
+assign SPI0_MOSI_T = 0;
+assign SPI0_MISO_O = 0;
+assign SPI0_MISO_T = 0;
+assign SPI0_SS_O = 0; /// confirm
+assign SPI0_SS1_O = 0;/// confirm
+assign SPI0_SS2_O = 0;/// confirm
+assign SPI0_SS_T = 0;
+always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
+begin
+ if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
+  $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
+end
+
+assign SPI1_SCLK_O = 0;
+assign SPI1_SCLK_T = 0;
+assign SPI1_MOSI_O = 0;
+assign SPI1_MOSI_T = 0;
+assign SPI1_MISO_O = 0;
+assign SPI1_MISO_T = 0;
+assign SPI1_SS_O = 0;
+assign SPI1_SS1_O = 0;
+assign SPI1_SS2_O = 0;
+assign SPI1_SS_T = 0;
+always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
+begin
+ if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
+  $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* UART  */
+/* ------------------------------------------- */
+/// confirm
+assign UART0_DTRN = 0;
+assign UART0_RTSN = 0;
+assign UART0_TX = 0;
+always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
+begin
+ if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
+  $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
+end
+
+assign UART1_DTRN = 0;
+assign UART1_RTSN = 0;
+assign UART1_TX = 0;
+always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
+begin
+ if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
+  $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TTC  */
+/* ------------------------------------------- */
+
+assign TTC0_WAVE0_OUT = 0;
+assign TTC0_WAVE1_OUT = 0;
+assign TTC0_WAVE2_OUT = 0;
+always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
+begin
+ if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
+  $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
+end
+
+assign TTC1_WAVE0_OUT = 0;
+assign TTC1_WAVE1_OUT = 0;
+assign TTC1_WAVE2_OUT = 0;
+always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
+begin
+ if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
+  $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* WDT  */
+/* ------------------------------------------- */
+
+assign WDT_RST_OUT = 0;
+always@(WDT_CLK_IN)
+begin
+ if(WDT_CLK_IN)
+  $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* TRACE  */
+/* ------------------------------------------- */
+
+assign TRACE_CTL = 0;
+assign TRACE_DATA = 0;
+always@(TRACE_CLK)
+begin
+ if(TRACE_CLK)
+  $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* USB  */
+/* ------------------------------------------- */
+assign USB0_PORT_INDCTL = 0;
+assign USB0_VBUS_PWRSELECT = 0;
+always@(USB0_VBUS_PWRFAULT)
+begin
+ if(USB0_VBUS_PWRFAULT)
+  $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
+end
+
+assign USB1_PORT_INDCTL = 0;
+assign USB1_VBUS_PWRSELECT = 0;
+always@(USB1_VBUS_PWRFAULT)
+begin
+ if(USB1_VBUS_PWRFAULT)
+  $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
+end
+
+always@(SRAM_INTIN)
+begin
+ if(SRAM_INTIN)
+  $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
+end 
+
+/* ------------------------------------------- */
+/* DMA  */
+/* ------------------------------------------- */
+
+assign DMA0_DATYPE = 0;
+assign DMA0_DAVALID = 0;
+assign DMA0_DRREADY = 0;
+assign DMA0_RSTN = 0;
+always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
+begin
+ if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA1_DATYPE = 0;
+assign DMA1_DAVALID = 0;
+assign DMA1_DRREADY = 0;
+assign DMA1_RSTN = 0;
+always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
+begin
+ if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA2_DATYPE = 0;
+assign DMA2_DAVALID = 0;
+assign DMA2_DRREADY = 0;
+assign DMA2_RSTN = 0;
+always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
+begin
+ if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+assign DMA3_DATYPE = 0;
+assign DMA3_DAVALID = 0;
+assign DMA3_DRREADY = 0;
+assign DMA3_RSTN = 0;
+always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
+begin
+ if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
+  $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FTM  */
+/* ------------------------------------------- */
+
+assign FTMT_F2P_TRIGACK = 0;
+assign FTMT_P2F_TRIG = 0;
+assign FTMT_P2F_DEBUG = 0;
+always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or 
+        FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
+begin
+ if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
+  $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* EVENT  */
+/* ------------------------------------------- */
+
+assign EVENT_EVENTO = 0;
+assign EVENT_STANDBYWFE = 0;  
+assign EVENT_STANDBYWFI = 0;
+always@(EVENT_EVENTI)
+begin
+ if(EVENT_EVENTI)
+  $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MIO */
+/* ------------------------------------------- */
+
+always@(MIO)
+begin
+// if(MIO !== 0)
+// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* FCLK_TRIG */
+/* ------------------------------------------- */
+
+always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
+begin
+ if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
+  $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* MISC */
+/* ------------------------------------------- */
+
+always@(FPGA_IDLE_N)
+begin
+ if(FPGA_IDLE_N)
+  $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
+end
+
+always@(DDR_ARB)
+begin
+//  if(DDR_ARB !== 0)
+//  $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
+end
+
+always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
+begin
+ if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) 
+  $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* DDR */
+/* ------------------------------------------- */
+
+assign DDR_WEB = 0;
+always@(DDR_Clk or DDR_CS_n)
+begin
+if(!DDR_CS_n)
+ $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
+end
+
+/* ------------------------------------------- */
+/* IRQ_P2F */
+/* ------------------------------------------- */
+
+assign IRQ_P2F_DMAC_ABORT = 0;
+assign IRQ_P2F_DMAC0 = 0;
+assign IRQ_P2F_DMAC1 = 0;
+assign IRQ_P2F_DMAC2 = 0;
+assign IRQ_P2F_DMAC3 = 0;
+assign IRQ_P2F_DMAC4 = 0;
+assign IRQ_P2F_DMAC5 = 0;
+assign IRQ_P2F_DMAC6 = 0;
+assign IRQ_P2F_DMAC7 = 0;
+assign IRQ_P2F_SMC = 0;
+assign IRQ_P2F_QSPI = 0;
+assign IRQ_P2F_CTI = 0;
+assign IRQ_P2F_GPIO = 0;
+assign IRQ_P2F_USB0 = 0;
+assign IRQ_P2F_ENET0 = 0;
+assign IRQ_P2F_ENET_WAKE0 = 0;
+assign IRQ_P2F_SDIO0 = 0;
+assign IRQ_P2F_I2C0 = 0;
+assign IRQ_P2F_SPI0 = 0;
+assign IRQ_P2F_UART0 = 0;
+assign IRQ_P2F_CAN0 = 0;
+assign IRQ_P2F_USB1 = 0;
+assign IRQ_P2F_ENET1 = 0;
+assign IRQ_P2F_ENET_WAKE1 = 0;
+assign IRQ_P2F_SDIO1 = 0;
+assign IRQ_P2F_I2C1 = 0;
+assign IRQ_P2F_SPI1 = 0;
+assign IRQ_P2F_UART1 = 0;
+assign IRQ_P2F_CAN1 = 0;

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v

@@ -0,0 +1,409 @@
+//-----------------------------------------------------------------------------
+//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+//--
+//-- This file contains confidential and proprietary information
+//-- of Xilinx, Inc. and is protected under U.S. and
+//-- international copyright and other intellectual property
+//-- laws.
+//--
+//-- DISCLAIMER
+//-- This disclaimer is not a license and does not grant any
+//-- rights to the materials distributed herewith. Except as
+//-- otherwise provided in a valid license issued to you by
+//-- Xilinx, and to the maximum extent permitted by applicable
+//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//-- (2) Xilinx shall not be liable (whether in contract or tort,
+//-- including negligence, or under any other theory of
+//-- liability) for any loss or damage of any kind or nature
+//-- related to, arising under or in connection with these
+//-- materials, including for any direct, or any indirect,
+//-- special, incidental, or consequential loss or damage
+//-- (including loss of data, profits, goodwill, or any type of
+//-- loss or damage suffered as a result of any action brought
+//-- by a third party) even if such damage or loss was
+//-- reasonably foreseeable or Xilinx had been advised of the
+//-- possibility of the same.
+//--
+//-- CRITICAL APPLICATIONS
+//-- Xilinx products are not designed or intended to be fail-
+//-- safe, or for use in any application requiring fail-safe
+//-- performance, such as life-support or safety devices or
+//-- systems, Class III medical devices, nuclear facilities,
+//-- applications related to the deployment of airbags, or any
+//-- other applications that could lead to death, personal
+//-- injury, or severe property or environmental damage
+//-- (individually and collectively, "Critical
+//-- Applications"). Customer assumes the sole risk and
+//-- liability of any use of Xilinx products in Critical
+//-- Applications, subject only to applicable laws and
+//-- regulations governing limitations on product liability.
+//--
+//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//-- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: ACP Transaction Checker
+// 
+// Check for optimized ACP transactions and flag if they are broken.
+// 
+// 
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   atc
+//     aw_atc
+//     w_atc
+//     b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+`default_nettype none
+
+module processing_system7_v5_5_atc #
+  (
+   parameter         C_FAMILY                         = "rtl",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32,
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_ARUSER_WIDTH               = 1,
+                       // Width of ARUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_WUSER_WIDTH                = 1,
+                       // Width of WUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_RUSER_WIDTH                = 1,
+                       // Width of RUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1
+                       // Width of BUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ACLK,
+   input  wire                                  ARESETN,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output wire [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_ARID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_ARADDR,
+   input  wire [4-1:0]                          S_AXI_ARLEN,
+   input  wire [3-1:0]                          S_AXI_ARSIZE,
+   input  wire [2-1:0]                          S_AXI_ARBURST,
+   input  wire [2-1:0]                          S_AXI_ARLOCK,
+   input  wire [4-1:0]                          S_AXI_ARCACHE,
+   input  wire [3-1:0]                          S_AXI_ARPROT,
+   input  wire [C_AXI_ARUSER_WIDTH-1:0]         S_AXI_ARUSER,
+   input  wire                                  S_AXI_ARVALID,
+   output wire                                  S_AXI_ARREADY,
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_RID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_RDATA,
+   output wire [2-1:0]                          S_AXI_RRESP,
+   output wire                                  S_AXI_RLAST,
+   output wire [C_AXI_RUSER_WIDTH-1:0]          S_AXI_RUSER,
+   output wire                                  S_AXI_RVALID,
+   input  wire                                  S_AXI_RREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY,
+   // Master Interface Write Data Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY,
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   // Master Interface Read Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_ARID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_ARADDR,
+   output wire [4-1:0]                          M_AXI_ARLEN,
+   output wire [3-1:0]                          M_AXI_ARSIZE,
+   output wire [2-1:0]                          M_AXI_ARBURST,
+   output wire [2-1:0]                          M_AXI_ARLOCK,
+   output wire [4-1:0]                          M_AXI_ARCACHE,
+   output wire [3-1:0]                          M_AXI_ARPROT,
+   output wire [C_AXI_ARUSER_WIDTH-1:0]         M_AXI_ARUSER,
+   output wire                                  M_AXI_ARVALID,
+   input  wire                                  M_AXI_ARREADY,
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_RID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_RDATA,
+   input  wire [2-1:0]                          M_AXI_RRESP,
+   input  wire                                  M_AXI_RLAST,
+   input  wire [C_AXI_RUSER_WIDTH-1:0]          M_AXI_RUSER,
+   input  wire                                  M_AXI_RVALID,
+   output wire                                  M_AXI_RREADY,
+   
+   output wire                                  ERROR_TRIGGER,
+   output wire [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+
+   
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  localparam C_FIFO_DEPTH_LOG            = 4;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Internal reset.
+  reg                                   ARESET;
+  
+  // AW->W command queue signals.
+  wire                                  cmd_w_valid;
+  wire                                  cmd_w_check;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id;
+  wire                                  cmd_w_ready;
+  
+  // W->B command queue signals.
+  wire                                  cmd_b_push;
+  wire                                  cmd_b_error;
+  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id;
+  wire                                  cmd_b_full;
+  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr;
+  wire                                  cmd_b_ready;
+  
+
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Internal Reset
+  /////////////////////////////////////////////////////////////////////////////
+  always @ (posedge ACLK) begin
+    ARESET <= !ARESETN;
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Write Channels (AW/W/B)
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Write Address Channel.
+  processing_system7_v5_5_aw_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
+   .C_AXI_AWUSER_WIDTH          (C_AXI_AWUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_addr_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (Out)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+   
+    // Slave Interface Write Address Ports
+    .S_AXI_AWID                 (S_AXI_AWID),
+    .S_AXI_AWADDR               (S_AXI_AWADDR),
+    .S_AXI_AWLEN                (S_AXI_AWLEN),
+    .S_AXI_AWSIZE               (S_AXI_AWSIZE),
+    .S_AXI_AWBURST              (S_AXI_AWBURST),
+    .S_AXI_AWLOCK               (S_AXI_AWLOCK),
+    .S_AXI_AWCACHE              (S_AXI_AWCACHE),
+    .S_AXI_AWPROT               (S_AXI_AWPROT),
+    .S_AXI_AWUSER               (S_AXI_AWUSER),
+    .S_AXI_AWVALID              (S_AXI_AWVALID),
+    .S_AXI_AWREADY              (S_AXI_AWREADY),
+    
+    // Master Interface Write Address Port
+    .M_AXI_AWID                 (M_AXI_AWID),
+    .M_AXI_AWADDR               (M_AXI_AWADDR),
+    .M_AXI_AWLEN                (M_AXI_AWLEN),
+    .M_AXI_AWSIZE               (M_AXI_AWSIZE),
+    .M_AXI_AWBURST              (M_AXI_AWBURST),
+    .M_AXI_AWLOCK               (M_AXI_AWLOCK),
+    .M_AXI_AWCACHE              (M_AXI_AWCACHE),
+    .M_AXI_AWPROT               (M_AXI_AWPROT),
+    .M_AXI_AWUSER               (M_AXI_AWUSER),
+    .M_AXI_AWVALID              (M_AXI_AWVALID),
+    .M_AXI_AWREADY              (M_AXI_AWREADY)
+   );
+   
+  // Write Data channel.
+  processing_system7_v5_5_w_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
+   .C_AXI_WUSER_WIDTH           (C_AXI_WUSER_WIDTH)
+    ) write_data_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_w_valid                (cmd_w_valid),
+    .cmd_w_check                (cmd_w_check),
+    .cmd_w_id                   (cmd_w_id),
+    .cmd_w_ready                (cmd_w_ready),
+    
+    // Command Interface (Out)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    
+    // Slave Interface Write Data Ports
+    .S_AXI_WID                  (S_AXI_WID),
+    .S_AXI_WDATA                (S_AXI_WDATA),
+    .S_AXI_WSTRB                (S_AXI_WSTRB),
+    .S_AXI_WLAST                (S_AXI_WLAST),
+    .S_AXI_WUSER                (S_AXI_WUSER),
+    .S_AXI_WVALID               (S_AXI_WVALID),
+    .S_AXI_WREADY               (S_AXI_WREADY),
+    
+    // Master Interface Write Data Ports
+    .M_AXI_WID                  (M_AXI_WID),
+    .M_AXI_WDATA                (M_AXI_WDATA),
+    .M_AXI_WSTRB                (M_AXI_WSTRB),
+    .M_AXI_WLAST                (M_AXI_WLAST),
+    .M_AXI_WUSER                (M_AXI_WUSER),
+    .M_AXI_WVALID               (M_AXI_WVALID),
+    .M_AXI_WREADY               (M_AXI_WREADY)
+   );
+   
+  // Write Response channel.
+  processing_system7_v5_5_b_atc #
+  (
+   .C_FAMILY                    (C_FAMILY),
+   .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
+   .C_AXI_BUSER_WIDTH           (C_AXI_BUSER_WIDTH),
+   .C_FIFO_DEPTH_LOG            (C_FIFO_DEPTH_LOG)
+    ) write_response_inst
+   (
+    // Global Signals
+    .ARESET                     (ARESET),
+    .ACLK                       (ACLK),
+
+    // Command Interface (In)
+    .cmd_b_push                 (cmd_b_push),
+    .cmd_b_error                (cmd_b_error),
+    .cmd_b_id                   (cmd_b_id),
+    .cmd_b_full                 (cmd_b_full),
+    .cmd_b_addr                 (cmd_b_addr),
+    .cmd_b_ready                (cmd_b_ready),
+    
+    // Slave Interface Write Response Ports
+    .S_AXI_BID                  (S_AXI_BID),
+    .S_AXI_BRESP                (S_AXI_BRESP),
+    .S_AXI_BUSER                (S_AXI_BUSER),
+    .S_AXI_BVALID               (S_AXI_BVALID),
+    .S_AXI_BREADY               (S_AXI_BREADY),
+    
+    // Master Interface Write Response Ports
+    .M_AXI_BID                  (M_AXI_BID),
+    .M_AXI_BRESP                (M_AXI_BRESP),
+    .M_AXI_BUSER                (M_AXI_BUSER),
+    .M_AXI_BVALID               (M_AXI_BVALID),
+    .M_AXI_BREADY               (M_AXI_BREADY),
+    
+    // Trigger detection
+    .ERROR_TRIGGER              (ERROR_TRIGGER),
+    .ERROR_TRANSACTION_ID       (ERROR_TRANSACTION_ID)
+   );
+  
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Handle Read Channels (AR/R)
+  /////////////////////////////////////////////////////////////////////////////
+  // Read Address Port
+  assign M_AXI_ARID     = S_AXI_ARID;
+  assign M_AXI_ARADDR   = S_AXI_ARADDR;
+  assign M_AXI_ARLEN    = S_AXI_ARLEN;
+  assign M_AXI_ARSIZE   = S_AXI_ARSIZE;
+  assign M_AXI_ARBURST  = S_AXI_ARBURST;
+  assign M_AXI_ARLOCK   = S_AXI_ARLOCK;
+  assign M_AXI_ARCACHE  = S_AXI_ARCACHE;
+  assign M_AXI_ARPROT   = S_AXI_ARPROT;
+  assign M_AXI_ARUSER   = S_AXI_ARUSER;
+  assign M_AXI_ARVALID  = S_AXI_ARVALID;
+  assign S_AXI_ARREADY  = M_AXI_ARREADY;
+   
+  // Read Data Port
+  assign S_AXI_RID      = M_AXI_RID;
+  assign S_AXI_RDATA    = M_AXI_RDATA;
+  assign S_AXI_RRESP    = M_AXI_RRESP;
+  assign S_AXI_RLAST    = M_AXI_RLAST;
+  assign S_AXI_RUSER    = M_AXI_RUSER;
+  assign S_AXI_RVALID   = M_AXI_RVALID;
+  assign M_AXI_RREADY   = S_AXI_RREADY;
+  
+  
+endmodule
+`default_nettype wire

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v

@@ -0,0 +1,298 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Address Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   aw_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_aw_atc #
+  (
+   parameter         C_FAMILY                         = "rtl", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_ADDR_WIDTH                 = 32, 
+                       // Width of all ADDR signals on SI and MI side of checker.
+                       // Range: 32.
+   parameter integer C_AXI_AWUSER_WIDTH               = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   output reg                                   cmd_w_valid,
+   output wire                                  cmd_w_check,
+   output wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   input  wire                                  cmd_w_ready,
+   input  wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   input  wire                                  cmd_b_ready,
+   
+   // Slave Interface Write Address Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_AWID,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]           S_AXI_AWADDR,
+   input  wire [4-1:0]                          S_AXI_AWLEN,
+   input  wire [3-1:0]                          S_AXI_AWSIZE,
+   input  wire [2-1:0]                          S_AXI_AWBURST,
+   input  wire [2-1:0]                          S_AXI_AWLOCK,
+   input  wire [4-1:0]                          S_AXI_AWCACHE,
+   input  wire [3-1:0]                          S_AXI_AWPROT,
+   input  wire [C_AXI_AWUSER_WIDTH-1:0]         S_AXI_AWUSER,
+   input  wire                                  S_AXI_AWVALID,
+   output wire                                  S_AXI_AWREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_AWID,
+   output wire [C_AXI_ADDR_WIDTH-1:0]           M_AXI_AWADDR,
+   output wire [4-1:0]                          M_AXI_AWLEN,
+   output wire [3-1:0]                          M_AXI_AWSIZE,
+   output wire [2-1:0]                          M_AXI_AWBURST,
+   output wire [2-1:0]                          M_AXI_AWLOCK,
+   output wire [4-1:0]                          M_AXI_AWCACHE,
+   output wire [3-1:0]                          M_AXI_AWPROT,
+   output wire [C_AXI_AWUSER_WIDTH-1:0]         M_AXI_AWUSER,
+   output wire                                  M_AXI_AWVALID,
+   input  wire                                  M_AXI_AWREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for burst types.
+  localparam [2-1:0] C_FIX_BURST         = 2'b00;
+  localparam [2-1:0] C_INCR_BURST        = 2'b01;
+  localparam [2-1:0] C_WRAP_BURST        = 2'b10;
+  
+  // Constants for size.
+  localparam [3-1:0] C_OPTIMIZED_SIZE    = 3'b011;
+  
+  // Constants for length.
+  localparam [4-1:0] C_OPTIMIZED_LEN     = 4'b0011;
+
+  // Constants for cacheline address.
+  localparam [4-1:0] C_NO_ADDR_OFFSET    = 5'b0;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction properties.
+  wire                                access_is_incr;
+  wire                                access_is_wrap;
+  wire                                access_is_coherent;
+  wire                                access_optimized_size;
+  wire                                incr_addr_boundary;
+  wire                                incr_is_optimized;
+  wire                                wrap_is_optimized;
+  wire                                access_is_optimized;
+  
+  // Command FIFO.
+  wire                                cmd_w_push;
+  reg                                 cmd_full;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  wire [C_FIFO_DEPTH_LOG-1:0]         all_addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Decode:
+  //
+  // Detect if transaction is of correct typ, size and length to qualify as
+  // an optimized transaction that has to be checked for errors.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Transaction burst type.
+  assign access_is_incr         = ( S_AXI_AWBURST == C_INCR_BURST );
+  assign access_is_wrap         = ( S_AXI_AWBURST == C_WRAP_BURST );
+  
+  // Transaction has to be Coherent.
+  assign access_is_coherent     = ( S_AXI_AWUSER[0]  == 1'b1 ) &
+                                  ( S_AXI_AWCACHE[1] == 1'b1 );
+  
+  // Transaction cacheline boundary address.
+  assign incr_addr_boundary     = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
+  
+  // Transaction length & size.
+  assign access_optimized_size  = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & 
+                                  ( S_AXI_AWLEN  == C_OPTIMIZED_LEN  );
+  
+  // Transaction is optimized.
+  assign incr_is_optimized      = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
+  assign wrap_is_optimized      = access_is_wrap & access_is_coherent & access_optimized_size;
+  assign access_is_optimized    = ( incr_is_optimized | wrap_is_optimized );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command FIFO:
+  //
+  // Since supported write interleaving is only 1, it is safe to use only a 
+  // simple SRL based FIFO as a command queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+    
+  // Determine when transaction infromation is pushed to the FIFO.
+  assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        addr_ptr <= addr_ptr + 1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        addr_ptr <= addr_ptr - 1;
+      end
+    end
+  end
+  
+  // Total number of buffered commands.
+  assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_full    <= 1'b0;
+      cmd_w_valid <= 1'b0;
+    end else begin
+      if ( cmd_w_push & ~cmd_w_ready ) begin
+        cmd_w_valid <= 1'b1;
+      end else if ( ~cmd_w_push & cmd_w_ready ) begin
+        cmd_w_valid <= ( addr_ptr != 0 );
+      end
+      if ( cmd_w_push & ~cmd_b_ready ) begin
+        // Going to full.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
+      end else if ( ~cmd_w_push & cmd_b_ready ) begin
+        // Pop in middle of queue doesn't affect full status.
+        cmd_full    <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_w_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {access_is_optimized, S_AXI_AWID};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_AWVALID   = S_AXI_AWVALID & ~cmd_full;
+  
+  // Return ready with push back.
+  assign S_AXI_AWREADY   = M_AXI_AWREADY & ~cmd_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Address Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_AWID      = S_AXI_AWID; 
+  assign M_AXI_AWADDR    = S_AXI_AWADDR;
+  assign M_AXI_AWLEN     = S_AXI_AWLEN;
+  assign M_AXI_AWSIZE    = S_AXI_AWSIZE;
+  assign M_AXI_AWBURST   = S_AXI_AWBURST;
+  assign M_AXI_AWLOCK    = S_AXI_AWLOCK;
+  assign M_AXI_AWCACHE   = S_AXI_AWCACHE;
+  assign M_AXI_AWPROT    = S_AXI_AWPROT;
+  assign M_AXI_AWUSER    = S_AXI_AWUSER;
+  
+  
+endmodule

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v

@@ -0,0 +1,413 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Response Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   b_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_b_atc #
+  (
+   parameter         C_FAMILY                         = "rtl", 
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4, 
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_BUSER_WIDTH                = 1,
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   parameter integer C_FIFO_DEPTH_LOG                 = 4
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface
+   input  wire                                  cmd_b_push,
+   input  wire                                  cmd_b_error,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   output wire                                  cmd_b_ready,
+   output wire [C_FIFO_DEPTH_LOG-1:0]           cmd_b_addr,
+   output reg                                   cmd_b_full,
+   
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_ID_WIDTH-1:0]             S_AXI_BID,
+   output reg  [2-1:0]                          S_AXI_BRESP,
+   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
+   output wire                                  S_AXI_BVALID,
+   input  wire                                  S_AXI_BREADY,
+
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_ID_WIDTH-1:0]             M_AXI_BID,
+   input  wire [2-1:0]                          M_AXI_BRESP,
+   input  wire [C_AXI_BUSER_WIDTH-1:0]          M_AXI_BUSER,
+   input  wire                                  M_AXI_BVALID,
+   output wire                                  M_AXI_BREADY,
+   
+   // Trigger detection
+   output reg                                   ERROR_TRIGGER,
+   output reg  [C_AXI_ID_WIDTH-1:0]             ERROR_TRANSACTION_ID
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Constants for packing levels.
+  localparam [2-1:0] C_RESP_OKAY         = 2'b00;
+  localparam [2-1:0] C_RESP_EXOKAY       = 2'b01;
+  localparam [2-1:0] C_RESP_SLVERROR     = 2'b10;
+  localparam [2-1:0] C_RESP_DECERR       = 2'b11;
+  
+  // Command FIFO settings
+  localparam C_FIFO_WIDTH                = C_AXI_ID_WIDTH + 1;
+  localparam C_FIFO_DEPTH                = 2 ** C_FIFO_DEPTH_LOG;
+    
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  integer index;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Command Queue.
+  reg  [C_FIFO_DEPTH_LOG-1:0]         addr_ptr;
+  reg  [C_FIFO_WIDTH-1:0]             data_srl[C_FIFO_DEPTH-1:0];
+  reg                                 cmd_b_valid;
+  wire                                cmd_b_ready_i;
+  wire                                inject_error;
+  wire [C_AXI_ID_WIDTH-1:0]           current_id;
+  
+  // Search command.
+  wire                                found_match;
+  wire                                use_match;
+  wire                                matching_id;
+  
+  // Manage valid command.
+  wire                                write_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             updated_valid_cmd;
+  reg  [C_FIFO_DEPTH-2:0]             next_valid_cmd;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         search_addr_ptr;
+  reg  [C_FIFO_DEPTH_LOG-1:0]         collapsed_addr_ptr;
+  
+  // Pipelined data
+  reg  [C_AXI_ID_WIDTH-1:0]           M_AXI_BID_I;
+  reg  [2-1:0]                        M_AXI_BRESP_I;
+  reg  [C_AXI_BUSER_WIDTH-1:0]        M_AXI_BUSER_I;
+  reg                                 M_AXI_BVALID_I;
+  wire                                M_AXI_BREADY_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Command Queue:
+  //
+  // Keep track of depth of Queue to generate full flag.
+  // 
+  // Also generate valid to mark pressence of commands in Queue.
+  // 
+  // Maintain Queue and extract data from currently searched entry.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // SRL FIFO Pointer.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        // Pushing data increase length/addr.
+        addr_ptr <= addr_ptr + 1;
+      end else if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        addr_ptr <= collapsed_addr_ptr;
+      end
+    end
+  end
+  
+  // FIFO Flags.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_full  <= 1'b0;
+      cmd_b_valid <= 1'b0;
+    end else begin
+      if ( cmd_b_push & ~cmd_b_ready_i ) begin
+        cmd_b_full  <= ( addr_ptr == C_FIFO_DEPTH-3 );
+        cmd_b_valid <= 1'b1;
+      end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
+        cmd_b_full  <= 1'b0;
+        cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
+      end
+    end
+  end
+  
+  // Infere SRL for storage.
+  always @ (posedge ACLK) begin
+    if ( cmd_b_push ) begin
+      for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
+        data_srl[index+1] <= data_srl[index];
+      end
+      data_srl[0]   <= {cmd_b_error, cmd_b_id};
+    end
+  end
+  
+  // Get current transaction info.
+  assign {inject_error, current_id} = data_srl[search_addr_ptr];
+  
+  // Assign outputs.
+  assign cmd_b_addr = collapsed_addr_ptr;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Search Command Queue:
+  //
+  // Search for matching valid command in queue.
+  // 
+  // A command is found when an valid entry with correct ID is found. The queue
+  // is search from the oldest entry, i.e. from a high value.
+  // When new commands are pushed the search address has to be updated to always 
+  // start the search from the oldest available.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Handle search addr.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
+    end else begin
+      if ( cmd_b_ready_i ) begin
+        // Collapse addr when data is popped.
+        search_addr_ptr <= collapsed_addr_ptr;
+        
+      end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
+        // Skip non valid command.
+        search_addr_ptr <= search_addr_ptr - 1;
+        
+      end else if ( cmd_b_push ) begin
+        search_addr_ptr <= search_addr_ptr + 1;
+        
+      end
+    end
+  end
+  
+  // Check if searched command is valid and match ID (for existing response on MI side).
+  assign matching_id  = ( M_AXI_BID_I == current_id );
+  assign found_match  = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
+  assign use_match    = found_match & S_AXI_BREADY;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Track Used Commands:
+  //
+  // Actions that affect Valid Command:
+  // * When a new command is pushed
+  //   => Shift valid vector one step
+  // * When a command is used
+  //   => Clear corresponding valid bit
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Valid command status is updated when a command is used or a new one is pushed.
+  assign write_valid_cmd  = cmd_b_push | cmd_b_ready_i;
+  
+  // Update the used command valid bit.
+  always @ *
+  begin
+    updated_valid_cmd                   = valid_cmd;
+    updated_valid_cmd[search_addr_ptr]  = ~use_match;
+  end
+  
+  // Shift valid vector when command is pushed.
+  always @ *
+  begin
+    if ( cmd_b_push ) begin
+      next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
+    end else begin
+      next_valid_cmd = updated_valid_cmd;
+    end
+  end
+  
+  // Valid signals for next cycle.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      valid_cmd <= {C_FIFO_WIDTH{1'b0}};
+    end else if ( write_valid_cmd ) begin
+      valid_cmd <= next_valid_cmd;
+    end
+  end
+  
+  // Detect oldest available command in Queue.
+  always @ *
+  begin
+    // Default to empty.
+    collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
+    
+    for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
+      if ( next_valid_cmd[index] ) begin
+        collapsed_addr_ptr = index;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Pipe incoming data:
+  // 
+  // The B channel is piped to improve timing and avoid impact in search
+  // mechanism due to late arriving signals.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Clock data.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      M_AXI_BID_I     <= {C_AXI_ID_WIDTH{1'b0}};
+      M_AXI_BRESP_I   <= 2'b00;
+      M_AXI_BUSER_I   <= {C_AXI_BUSER_WIDTH{1'b0}};
+      M_AXI_BVALID_I  <= 1'b0;
+    end else begin
+      if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
+        M_AXI_BVALID_I  <= 1'b0;
+      end
+      if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
+        M_AXI_BID_I     <= M_AXI_BID;
+        M_AXI_BRESP_I   <= M_AXI_BRESP;
+        M_AXI_BUSER_I   <= M_AXI_BUSER;
+        M_AXI_BVALID_I  <= 1'b1;
+      end
+    end
+  end
+  
+  // Generate ready to get new transaction.
+  assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Inject Error:
+  //
+  // BRESP is modified according to command information.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Inject error in response.
+  always @ *
+  begin
+    if ( inject_error ) begin
+      S_AXI_BRESP = C_RESP_SLVERROR;
+    end else begin
+      S_AXI_BRESP = M_AXI_BRESP_I;
+    end
+  end
+  
+  // Handle interrupt generation.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      ERROR_TRIGGER        <= 1'b0;
+      ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
+    end else begin
+      if ( inject_error & cmd_b_ready_i ) begin
+        ERROR_TRIGGER        <= 1'b1;
+        ERROR_TRANSACTION_ID <= M_AXI_BID_I;
+      end else begin
+        ERROR_TRIGGER        <= 1'b0;
+      end
+    end
+  end
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Response is passed forward when a matching entry has been found in queue.
+  // Both ready and valid are set when the command is completed.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign S_AXI_BVALID   = M_AXI_BVALID_I & cmd_b_valid & found_match;
+  
+  // Return ready with push back.
+  assign M_AXI_BREADY_I = cmd_b_valid & use_match;
+  
+  // Command has been handled.
+  assign cmd_b_ready_i  = M_AXI_BVALID_I & cmd_b_valid & use_match;
+  assign cmd_b_ready    = cmd_b_ready_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write Response Propagation:
+  //
+  // All information is simply forwarded on from MI- to SI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign S_AXI_BID    = M_AXI_BID_I;
+  assign S_AXI_BUSER  = M_AXI_BUSER_I;
+  
+  
+endmodule

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v

@@ -0,0 +1,310 @@
+// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Filename:      trace_buffer.v
+// Description:   Trace port buffer 
+//-----------------------------------------------------------------------------
+// Structure:   This section shows the hierarchical structure of 
+//              pss_wrapper.
+//
+//              --processing_system7
+//							 |	
+//							 --trace_buffer
+//-----------------------------------------------------------------------------
+
+
+module processing_system7_v5_5_trace_buffer #
+  (
+   parameter integer FIFO_SIZE = 128,
+	parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
+   parameter integer C_DELAY_CLKS = 12
+   )
+  (
+   input wire TRACE_CLK,
+   input wire RST,
+   input wire TRACE_VALID_IN,
+   input wire [3:0] TRACE_ATID_IN,
+   input wire [31:0] TRACE_DATA_IN,
+   output wire TRACE_VALID_OUT,
+   output wire [3:0] TRACE_ATID_OUT,
+   output wire [31:0] TRACE_DATA_OUT
+  );
+
+//------------------------------------------------------------
+// Architecture section
+//------------------------------------------------------------
+
+// function called clogb2 that returns an integer which has the 
+// value of the ceiling of the log base 2.
+
+function integer clogb2 (input integer bit_depth);
+ integer i;
+ integer temp_log;
+ begin
+  temp_log = 0;
+  for(i=bit_depth; i > 0; i = i>>1)
+  clogb2 = temp_log;
+  temp_log=temp_log+1;		
+ end
+endfunction
+
+localparam DEPTH  = clogb2(FIFO_SIZE-1);
+
+wire [31:0] reset_zeros;
+reg  [31:0] trace_pedge; // write enable for FIFO
+reg  [31:0] ti;
+reg  [31:0] tom;
+
+reg  [3:0] atid;
+
+reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory 
+
+reg  [4:0]  dly_ctr;
+reg  [DEPTH-1:0]  fifo_wp;
+reg  [DEPTH-1:0]  fifo_rp;
+
+reg         fifo_re;
+wire        fifo_empty;
+wire        fifo_full;
+reg         fifo_full_reg;
+
+assign reset_zeros = 32'h0;  
+
+
+// Pipeline Stage for Traceport ATID ports
+  always @(posedge TRACE_CLK) begin
+    // process pedge_ti
+    // rising clock edge
+    if((RST == 1'b1)) begin
+      atid <= reset_zeros;
+    end
+    else begin	 
+      atid <= TRACE_ATID_IN;
+	 end
+  end
+
+  assign TRACE_ATID_OUT = atid;
+  
+  /////////////////////////////////////////////
+  // Generate FIFO data based on TRACE_VALID_IN
+  /////////////////////////////////////////////
+  generate
+    if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
+  /////////////////////////////////////////////
+        
+		  // memory update process
+		  // Update memory when positive edge detected and FIFO not full
+		  always @(posedge TRACE_CLK) begin
+				if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
+					trace_fifo[fifo_wp]  <= TRACE_DATA_IN;
+				end
+		  end
+
+		  // fifo write pointer
+		  always @(posedge TRACE_CLK) begin
+				// process
+			 if(RST == 1'b1) begin
+				fifo_wp <= {DEPTH{1'b0}};
+			 end
+			 else if(TRACE_VALID_IN ) begin
+				if(fifo_wp == (FIFO_SIZE - 1)) begin
+				  if (fifo_empty) begin
+					 fifo_wp <= {DEPTH{1'b0}};
+				  end
+				end
+				else begin
+				  fifo_wp <= fifo_wp + 1;
+				end
+			 end
+		  end
+
+
+  /////////////////////////////////////////////
+  // Generate FIFO data based on data edge
+  /////////////////////////////////////////////
+    end else begin : gen_data_edge_detector
+  /////////////////////////////////////////////
+
+
+		  // purpose: check for pos edge on any trace input
+		  always @(posedge TRACE_CLK) begin
+			 // process pedge_ti
+			 // rising clock edge
+			 if((RST == 1'b1)) begin
+				ti          <= reset_zeros;
+				trace_pedge <= reset_zeros;
+			 end
+			 else begin
+				ti          <= TRACE_DATA_IN;
+				trace_pedge <= (~ti & TRACE_DATA_IN);
+				//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) &  ~ti;
+				// posedge only
+			 end
+		  end
+		  
+		  // memory update process
+		  // Update memory when positive edge detected and FIFO not full
+		  always @(posedge TRACE_CLK) begin
+			 if(|(trace_pedge)  == 1'b1 && fifo_full_reg != 1'b1) begin
+				trace_fifo[fifo_wp]  <= trace_pedge;
+			 end
+		  end
+
+		  // fifo write pointer
+		  always @(posedge TRACE_CLK) begin
+				// process
+			 if(RST == 1'b1) begin
+				fifo_wp <= {DEPTH{1'b0}};
+			 end
+			 else if(|(trace_pedge)  == 1'b1) begin
+				if(fifo_wp == (FIFO_SIZE - 1)) begin
+				  if (fifo_empty) begin
+					 fifo_wp <= {DEPTH{1'b0}};
+				  end
+				end
+				else begin
+				  fifo_wp <= fifo_wp + 1;
+				end
+			 end
+		  end
+
+
+    end
+  endgenerate
+
+
+  always @(posedge TRACE_CLK) begin
+    tom <= trace_fifo[fifo_rp] ;
+  end
+
+
+//  // fifo write pointer
+//  always @(posedge TRACE_CLK) begin
+//      // process
+//    if(RST == 1'b1) begin
+//      fifo_wp <= {DEPTH{1'b0}};
+//    end
+//    else if(|(trace_pedge)  == 1'b1) begin
+//      if(fifo_wp == (FIFO_SIZE - 1)) begin
+//        fifo_wp <= {DEPTH{1'b0}};
+//      end
+//      else begin
+//        fifo_wp <= fifo_wp + 1;
+//      end
+//    end
+//  end
+
+
+  // fifo read pointer update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      fifo_rp <= {DEPTH{1'b0}};
+      fifo_re <= 1'b0;
+    end
+    else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
+      fifo_re <= 1'b1;
+      if(fifo_rp == (FIFO_SIZE - 1)) begin
+        fifo_rp <= {DEPTH{1'b0}};
+      end
+      else begin
+        fifo_rp <= fifo_rp + 1;
+      end
+    end
+    else begin
+      fifo_re <= 1'b0;
+    end
+  end
+  
+  // delay counter update
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      dly_ctr <= 5'h0;
+    end
+    else if (fifo_re == 1'b1) begin
+      dly_ctr <= C_DELAY_CLKS-1;
+    end
+    else if(dly_ctr != 5'h0) begin
+      dly_ctr <= dly_ctr - 1;
+    end
+  end
+
+  // fifo empty update
+  assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
+
+  // fifo full update
+  assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
+
+  always @(posedge TRACE_CLK) begin
+    if(RST == 1'b1) begin
+      fifo_full_reg <= 1'b0;
+    end
+    else if (fifo_empty) begin
+      fifo_full_reg <= 1'b0;
+	 end else begin	
+      fifo_full_reg <= fifo_full;
+    end
+  end  
+  
+//  always @(posedge TRACE_CLK) begin
+//    if(RST == 1'b1) begin
+//      fifo_full_reg <= 1'b0;
+//    end
+//    else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
+//      fifo_full_reg <= 1'b1;
+//    end
+//	 else begin
+//        fifo_full_reg <= 1'b0;
+//    end
+//  end  
+//  
+  assign TRACE_DATA_OUT     = tom;
+  
+  assign TRACE_VALID_OUT    = fifo_re;  
+  
+  
+
+
+endmodule

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v

@@ -0,0 +1,244 @@
+// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
+// --
+// -- This file contains confidential and proprietary information
+// -- of Xilinx, Inc. and is protected under U.S. and 
+// -- international copyright and other intellectual property
+// -- laws.
+// --
+// -- DISCLAIMER
+// -- This disclaimer is not a license and does not grant any
+// -- rights to the materials distributed herewith. Except as
+// -- otherwise provided in a valid license issued to you by
+// -- Xilinx, and to the maximum extent permitted by applicable
+// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// -- (2) Xilinx shall not be liable (whether in contract or tort,
+// -- including negligence, or under any other theory of
+// -- liability) for any loss or damage of any kind or nature
+// -- related to, arising under or in connection with these
+// -- materials, including for any direct, or any indirect,
+// -- special, incidental, or consequential loss or damage
+// -- (including loss of data, profits, goodwill, or any type of
+// -- loss or damage suffered as a result of any action brought
+// -- by a third party) even if such damage or loss was
+// -- reasonably foreseeable or Xilinx had been advised of the
+// -- possibility of the same.
+// --
+// -- CRITICAL APPLICATIONS
+// -- Xilinx products are not designed or intended to be fail-
+// -- safe, or for use in any application requiring fail-safe
+// -- performance, such as life-support or safety devices or
+// -- systems, Class III medical devices, nuclear facilities,
+// -- applications related to the deployment of airbags, or any
+// -- other applications that could lead to death, personal
+// -- injury, or severe property or environmental damage
+// -- (individually and collectively, "Critical
+// -- Applications"). Customer assumes the sole risk and
+// -- liability of any use of Xilinx products in Critical
+// -- Applications, subject only to applicable laws and
+// -- regulations governing limitations on product liability.
+// --
+// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// -- PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+//
+// Description: Write Channel for ATC
+//
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   w_atc
+//
+//--------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+
+module processing_system7_v5_5_w_atc #
+  (
+   parameter         C_FAMILY                         = "rtl",
+                       // FPGA Family. Current version: virtex6, spartan6 or later.
+   parameter integer C_AXI_ID_WIDTH                   = 4,
+                       // Width of all ID signals on SI and MI side of checker.
+                       // Range: >= 1.
+   parameter integer C_AXI_DATA_WIDTH                 = 64,
+                       // Width of all DATA signals on SI and MI side of checker.
+                       // Range: 64.
+   parameter integer C_AXI_WUSER_WIDTH                = 1
+                       // Width of AWUSER signals. 
+                       // Range: >= 1.
+   )
+  (
+   // Global Signals
+   input  wire                                  ARESET,
+   input  wire                                  ACLK,
+
+   // Command Interface (In)
+   input  wire                                  cmd_w_valid,
+   input  wire                                  cmd_w_check,
+   input  wire [C_AXI_ID_WIDTH-1:0]             cmd_w_id,
+   output wire                                  cmd_w_ready,
+   
+   // Command Interface (Out)
+   output wire                                  cmd_b_push,
+   output wire                                  cmd_b_error,
+   output reg  [C_AXI_ID_WIDTH-1:0]             cmd_b_id,
+   input  wire                                  cmd_b_full,
+   
+   // Slave Interface Write Port
+   input  wire [C_AXI_ID_WIDTH-1:0]             S_AXI_WID,
+   input  wire [C_AXI_DATA_WIDTH-1:0]           S_AXI_WDATA,
+   input  wire [C_AXI_DATA_WIDTH/8-1:0]         S_AXI_WSTRB,
+   input  wire                                  S_AXI_WLAST,
+   input  wire [C_AXI_WUSER_WIDTH-1:0]          S_AXI_WUSER,
+   input  wire                                  S_AXI_WVALID,
+   output wire                                  S_AXI_WREADY,
+
+   // Master Interface Write Address Port
+   output wire [C_AXI_ID_WIDTH-1:0]             M_AXI_WID,
+   output wire [C_AXI_DATA_WIDTH-1:0]           M_AXI_WDATA,
+   output wire [C_AXI_DATA_WIDTH/8-1:0]         M_AXI_WSTRB,
+   output wire                                  M_AXI_WLAST,
+   output wire [C_AXI_WUSER_WIDTH-1:0]          M_AXI_WUSER,
+   output wire                                  M_AXI_WVALID,
+   input  wire                                  M_AXI_WREADY
+   );
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Local params
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Variables for generating parameter controlled instances.
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Functions
+  /////////////////////////////////////////////////////////////////////////////
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Internal signals
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detecttion.
+  wire                                any_strb_deasserted;
+  wire                                incoming_strb_issue;
+  reg                                 first_word;
+  reg                                 strb_issue;
+  
+  // Data flow.
+  wire                                data_pop;
+  wire                                cmd_b_push_blocked;
+  reg                                 cmd_b_push_i;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Detect error:
+  //
+  // Detect and accumulate error when a transaction shall be scanned for
+  // potential issues.
+  // Accumulation of error is restarted for each ne transaction. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Check stobe information
+  assign any_strb_deasserted  = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
+  assign incoming_strb_issue  = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
+  
+  // Keep track of first word in a transaction.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      first_word  <= 1'b1;
+    end else if ( data_pop ) begin
+      first_word  <= S_AXI_WLAST;
+    end
+  end
+  
+  // Keep track of error status.
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      strb_issue  <= 1'b0;
+      cmd_b_id    <= {C_AXI_ID_WIDTH{1'b0}};
+    end else if ( data_pop ) begin
+      if ( first_word ) begin
+        strb_issue  <= incoming_strb_issue;
+      end else begin
+        strb_issue  <= incoming_strb_issue | strb_issue;
+      end
+      cmd_b_id    <= cmd_w_id;
+    end
+  end
+  
+  assign cmd_b_error  = strb_issue;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Control command queue to B:
+  //
+  // Push command to B queue when all data for the transaction has flowed  
+  // through.
+  // Delay pipelined command until there is room in the Queue.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Detect when data is popped.
+  assign data_pop   = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; 
+  
+  // Push command when last word in transfered (pipelined).
+  always @ (posedge ACLK) begin
+    if (ARESET) begin
+      cmd_b_push_i  <= 1'b0;
+    end else begin
+      cmd_b_push_i  <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
+    end
+  end
+  
+  // Detect if pipelined push is blocked.
+  assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
+  
+  // Assign output.
+  assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Transaction Throttling:
+  //
+  // Stall commands if FIFO is full or there is no valid command information 
+  // from AW. 
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // Propagate masked valid.
+  assign M_AXI_WVALID   = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // Return ready with push back.
+  assign S_AXI_WREADY   = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
+  
+  // End of burst.
+  assign cmd_w_ready    = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
+  
+  
+  /////////////////////////////////////////////////////////////////////////////
+  // Write propagation:
+  //
+  // All information is simply forwarded on from the SI- to MI-Side untouched.
+  // 
+  /////////////////////////////////////////////////////////////////////////////
+  
+  // 1:1 mapping.
+  assign M_AXI_WID      = S_AXI_WID;
+  assign M_AXI_WDATA    = S_AXI_WDATA;
+  assign M_AXI_WSTRB    = S_AXI_WSTRB;
+  assign M_AXI_WLAST    = S_AXI_WLAST;
+  assign M_AXI_WUSER    = S_AXI_WUSER;
+  
+  
+endmodule

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/b2d0/hdl/verilog/sc_node_v1_0_10_t_reqsend.svh

@@ -0,0 +1,71 @@
+//  (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+// Begin sc_node_v1_0_10_structs.svh
+//-----------------------------------------------------------------------------
+typedef logic [C_NUM_MI-1:0] t_route;
+typedef logic [C_INFO_WIDTH-1:0] t_info;
+typedef logic [C_LOG_MAX_DOWNSIZER_RATIO-1:0] t_downsizer_count;
+typedef logic [C_LOG_NUM_SI-1:0] t_source;
+typedef struct packed {
+  t_max_byte_size    end_pntr;
+  t_max_byte_size    start_pntr;
+  t_downsizer_count  repeat_count;        
+} t_send;
+
+typedef struct packed {
+  t_source           source;
+  t_route            sc_route;
+  t_info             info;
+} t_req;
+
+typedef struct packed {
+  t_send             send;        
+  t_req              req;         
+} t_reqsend;
+//-----------------------------------------------------------------------------
+// end sc_node_v1_0_10_structs.svh
+//-----------------------------------------------------------------------------

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/b89e/hdl/sc_axi2sc_v1_0_vl_rfs.sv

@@ -0,0 +1,348 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+YpgQyVrhyLTeRj7WRxP6Xi8lXzyXzrPefqGQQIAm26gDcmqfmAXi6sdyFE+PQ6cQ5xTR3P6mi6oJ
+q0FoUhywQg==
+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+sTwu4humGWFtGhfOhWpmycbLRZu8MjBs9lxyp04haKVVHVzFzSkVMJftPKUYbtgdG4drieG/opsA
++xoGkdzuIG1U5Qeyr8aH8SJMFcynwJBWcVBix+msU8gh/eLoCb9XH3QoXmiyzZeCbKO9jevLTkZ6
+x/pdO+KJhzjFfJjjsxk=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+cGgAXS+WA3sVFZn3Ab+z7hkp912iDV2zc//d8Q/HrRPgrRqchL1eLTrGrQq/xWCoEBaSmK2S1klS
+qr3b06UzdNEO4O/vI2MaJ8pHMCTW0l8cq3okT5fjaZ8c13d6SOEC+veBWxEO7+j18oM5tiewHTkd
+ayagUCPCpTFxsLN6IDl6xw5HzuoFPKvHzHv7YmQdNOnTbDPgioFPQhlFaz08UBR3lQpJqiOrH/xe
+4Zk8armUGuK/y+J2+bugti9sfDfKvPQy9QpnjuwMMFHy32WBNBdPpn00hlx1U07tCGxhoykNM+hD
+mSTFfsykmjkmJZNk3Lu1Y0Lp5vPeDSb2CtBLpA==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+EOZsUwEQHGVQfnsb7RQyTM6Rjk4r0yv0Seae3BljTGMHSAXBDuVbAHQuwIq4yvlze0sqjSJ54EBG
+8iA4jHLjNpizuRghuhLeRSg97LXyLQFxJDseE9lVUceEi/p7jjvMERmOqV6cNLucvAA6rexbLGCx
+yz7cGGSER+eEg1xQLc9V+HnxH0/oGmRJmhqEm9a9wXAemOwwO4UoSjq7a39WvhKVcInjArJWOARu
+3edMY/uCaeX6gFzHqjF1/vE52VoYg2A0Ca4O1F1nVPhH3ENW67sOSue5Qi/2Y+JLbNNnsgwmbk1M
+EuDhYhCBItrBZv+NkfhwoARJPDk+jIpvFhqD2A==
+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+nBAhuH6WB0/QtFcYYjqC4o9KdjXHZ9qHKlH6lgUnLZsBS/L4gJ9HWwxnaT1gKRwaXKPmUt3MJgNg
+Jz8GhhCYyYm09s6owsr7N5ZIQmttTOHO+mhuiGAoTnJuV1YlXNO7CCGs21c3puuKpZXUm0p0MELb
+7ATONw6IlLA7hZMfX3IUfOFH0raiilUiw1j9h9liZl5YfAg24SWnQXD5m1b+qelrEGbdlL4lKxBk
+MYPeIg5UFsMRbGU7njUt64FsNFXLKuemn5zIngYFhAKQyK1KNnmBD1LMv2nt538+9D//94EYYh7K
+9dUpM+buchP7DTFsIgVvm1ICgSfN9RPVc6wWng==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+Ma/rvBNsVkZaBf5Og+p7R9nhygvLjqrg00Ji4PGOdH0QLb8kZAUqwblprcZ8PUBXCQXjdqOHlET6
+3bWwCju5OQx1517MHeBYvWsDKp/FGzFr9Cy7WqrXGnq2xb9QaijTTpfA6T2SeFb6nUNZUkP8DKRk
+841cF8vLFzs+XSGprlo=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+DEQKqX3053vJZVYZHaY5TP7qaEvlOVbDMO3sEcWDC+v8UrndiuiSpvz/8Ps+7IFPTMZHGgsx6oWx
+BQQBKVpVQm3kPD6PmMXLarKXSq+DEzaP2jOxaA0DjHh1w0JUN4DpOsYSPvkJJaoTM3VZZuQ1DP3B
+0VALM2G2b4iNtV/uqyG64N3FL0khscF/yPQzd9uAmty8rgHgAC6aqTFsuCW/mwr9GXBOto/Bt5CN
+PLjaaHifLefwWH2WIrM1wk1gCa1lHXxjvsRZsRYPNYiYq8SaLinu9f/gN8CrrNTQecp+6lGyAt+X
+HafwGPliFjgQtVgIu+W13fSiv2OTihAQweuGdQ==
+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16176)
+`pragma protect data_block
+A9Glh5RADf9GVRDZTj2Ny35eUP6Fuyq84H2B16BbMUPasBvj8LvZmvv23j44MKgdHaggCaEIB1po
+zqpynENpItPY/XYVXC/rrsPHNsItH8MF7mATdiqL1Led1FBrqZ83n6nQUMPIruVqTq7+FB8/1cU7
+wvLKcq3mLvWxloZ162zgTvvlkV569DO/q3+TCbV8MGno1MK6kp2Y5+CS5pGCgVFZkuh9U0UBfkDI
+To/W/nSggwyvoM15TkRI5LrAvWHFaQKkq5fpSioaxTWiObSOLdVUAgAUM11SR9cUD2L5sfNmhCyr
+72iY9JB9Q3ezmX3BqojuD7A366RPbvgRDITbMfClMy7wfv/m0KNcqdXcac0PgQdMMyMcUfCpt8Lu
+0x9rEB3lMbbrnfFolzNMgayaje/XJYhTNgf7opGQ1gj7S2K+2UBbU2qv4oIB+hwXUfMGfObKEmLK
+GmFVS04m2N9qFDEWDJKHJPJH+yY0JiDh+2nRblk8XcEWpHmfO8MRYLKOsweVc5gAOqyOYGe03sIi
+z2Otl9AkfQasrDf5SJljelzC5xtYQ5ZE+9W10JE7PntZxfvMrCXeHNJWXCM314nAL0CVUvs1YHif
+GVtIh7ZRCecKWVeVcDhq54Ylo8y9EDWp88K/JX/U/Fg63e532hfoonLU406IRSMhU1UE/cxO6mi+
+kstjWTMG2pZMXxRJw/HhOWzz6d7soDUa38dU5MuPkdiDfL6YgOS2dM31aCW34rDfVS44J5MpLQhZ
+PJcTIN1opP6meR1TlzQrWCY9ROxZULPhZt9k11MqqJPYPP0j9rFfBe7Ntjpgo71XGA7RQ7pHmsAQ
+B/YD15N9EFpX3O//3qSaJ4LCB9lGem5PcFDoRuxG2QtIGJT3qgkmoMn/8Pzt15HJlMBE08ll4psJ
+U8XX0nbPz7r8Wj9Lc+//IbigL3AwULnIb/XmjrY0zgc3xs+W+eMhUOZ94chC1IDEN38rFFJxzPg3
+1Ir8e49zxAtCoS8jHNayy+eS2mbC507b6Oh20ylsMY5lY+nhjZs0qCU36Md0Yipd72bm3k/JYTAc
+MYcTgx2IvCoPXoF/EGV7u72tV/uFmiUzPnU0rMFA+Bo8hqs9KyGfHUILm8ZviUcWwzUeH11b+CYa
+LR5nB8D6aHQD6blRXHtZnRC4HlYL9rmgvyLcl5ZZcN93KMJsrGted6NX9ouyaoiOV9jpMaFdhJ8F
+kpmVOz67R/LQSxHgE3wePbi1i5y6vnENa29KMcoJQ7KR+NFNmwuohWCH1CU8xjwXEDWno4S+qR4d
+mRu2cs4ZIvYXfWx4ShuP9uTV8sjfHS8kqxAfFrJjmn+c7aWklBKPHkCZxnqbJxq+i+tIzDpOavu/
+RVEij2Q/I5DCEIQ8vfiwo0QlrrD+FrL0Xw3XpTu9FQID0TxSQcN2snBlHcTGkvu3rspN3gzTfKKo
+GcNZZRHJvLzBe4qCB3EVNhrlko7poII6s0Sut1Kc7UUxkfF64f+sw2DfInMlzTMB5hfQKqogbfKW
+Nl6qwhtOTy79Bnz0KjipYpNdSyGOeMxLXHEf0M7/f2khxuBQhUDqFOTvIyiLIOWjofDEQOVqUA4M
+OuDivZ2P1j07gFXVYo43cZtuLKmE8H4jGQJd8I8x7Ioe8CG8OFW4sI4o6zoa/ApMDSYAyAlx5Dxh
+DD4Ay1ipvW2KClvwHACsX7OELlDrniBmH18rR6T+gaAlb1Qdr9BDiVTP2ufhu51eYRm1jXQIlupp
+rWIWyCmi+4jNU6flJEZN3WonbHnTdQzO+t5cVtG7uJDbv73NrXTK2YddrsE2vKZZ3KM3YzQ3E0yq
+CWEfYzrcMkOxkRjIKQaMvvTBulzTrjNBDQpJbmHdvkyltNUE+7oK8Ld/RqgRBuqYAA/drQULmzdc
+SFpVS9rADYxwmYMwuAgXU1MSslhREdN9tC4OTzi/CdWft7DdIZGLjn1iDZqHFIuYdykLzIvEMxiO
+4fQbZsSciUkykyiZazAjqvX71tAcLsuJZCi1R+R7kfvkcKIzuSB5uvLbVEXOF9ov/iDxg7IB3ZV4
+nneL20w5+zOlTzBCub+Bl2sgfkiV1Xnucl+T/3j0Sz3P9xS66QQ+t/QZnzRW+5igVWWcY4XPAxHk
+aOy/avAnYgxGymQuyVofEiAfZKPXhXzrJDOz8oS06N7+7Uk3iP+zo82xg3w7qq0JVgxZUM6p+nhp
+G7oHC1pgvEFfGBMArEy8vMhwMLA7JYoEWpvm9cqK1YgyJowOpHkT3i4ozHmo7Ncz83z+3VMwQyYY
+/MnL1o7qBIJClWur9vHt9Su8tOnQQM/K4gK2JOUmws17MVSpkzi/kEwgKLjImb+n3WaD9OCEQTpL
+W8rXhI/PO+a7cgL5dkToj/oTpu7sVPiSf4lJEolVZNRoMlgBPQlUuU/chzS11HBdYkROq8zWFjL3
+JzzmxS8U3YGQ+YW7AaJQre3H1rMx+3eaS0MqKL1sTmt+w/dtafBC4lS4c3ygxS5u0JEAe3Gh3DF+
+2xTntG7aR+4JXVBgS8QZzsLqRiIYglKyHVQvvrquJkkcPXC5FMoLXYbp+Dl+ivfZGLRuhrzpxp41
+GMouniJRWnhbZNjbufebJyeVszTCps+Me07RDplCj5+/ySfu1CWOEEb0PtC+sUUk+JA6GPQQ7DCs
+mI8Dz9h2MHuXKRCPIodpq5mJyKrwF8W9LV8nRGxJjGFJfGF9QC0c1blCn2UjhTNDFRxuQ37eINZk
+25NU1ciuhw6si6N+oIEolgovhHcUWJtSoYMhG+n4J9lvoUiWQdg9haSneFlrGgltw4e0Fja5Jx3T
+rXbsTEFprrWx8t1bSJcVQ+7tlyuAsDi4/dn9iUoZP9EHuFGOFqMYXUBGKpU6mueby7K/nJK8aylH
+kOvhxo1bGHiw4VAR+aevphKyKEn7srv+oRbWP6JpN9xrCdr8gJ7uSY7BsIhGk1BGSkSV0ss/i8Q1
+IlMCsYjnn2fxwR0c7Gg7dDzaDah2Mn4pF47e0EvOD26aXc2Im9pzvEQ1HU83Hv06pM34HJVN8Q+M
+0k6B1cHZedxF+Xckz8+QU+/S8I7M4/PUcS0TuZGODliwX51D+ZbEH2ypgTiENW86MtMiC947GiQ4
+ek3Kw6eq6zBvqPtSUmd0JezI3ruOgM0/Ih21iLQ6OROwNHbFCkrEpMVtWYJHodCShZWvGo4/MLEI
+a+nL7dA5ImpVYtMSI+JXsEpesOwK0Id6usQ6LdsY/5CNTAXVNOFOqch8uZTIpt/iEw28I0d9zpgi
+KR/2VUld5oWarQjn2SuGLW1At3fGr2fS/pO/X5xW9bLFRf28XIJe6ROl221O86jO6Nv3PMBvKFxo
+i9lQmDH+VwtFAs58s+nYHUEh3sQk6FGBc53kUhev+3cXvfW56PFLbJs6abDzl5TrMuLbrVmNnPeN
+ccKQQQYdUkWbPkxqhwqx8hfZtUffeec59xpuP7piQTE15fPbzIMXXuhjOkS8BVK8O6skxWXC9qz8
+G/xCcpW+obRhpmDl8niA7q92OkOQhmlc0qvusBSvsYOqj0yYCgno15udPzyAJ8ahBS78IggfDKYQ
++ERXgmZm8ZzyUL4AnY6jci8ok5acwytLuvyOpbsvBTThKts9khfrk0LpFILAnPzjGzLc7hfqm1lL
+e02hVuuABMDYE8bIjh5kRtRowh/gsGr9sPKMCIrsfAwrOfEEAMyMe6UZmczo96JfHQjU40tF7giM
+/92ZRVmb6IhrRgM6YTler1zp7pNPJRXjclL9+JDmT++ucSlbTeKaRwiCZr9MqjB5UorbSBG25OdS
+wseBbV2GwAtC0hun1YiwuiwYoTRzL0q6GJJsWvIRHAKlr57TRJsJac5lAyUrI0zeGg3CRGDm+Zvj
+bd/+PNojXsVDXZqf76pTEcwGiP7DYrWIUp2B+zEjkgAulvLZdpus3MNMJzS9lGnqeV3XfPAutfWw
+Tlwk0DNI0wZArnmn6hyswmHNs4je1lMautv7vRdzPG6BADSdiPF+b9DxCNknYEJqGr+1bD9Be9tT
+K+ViQBoQ5zoeFHnZgNLFkSQHAYQgH7ikY/4yMPislizJlytYxAh55Gk3GEtfNWeMAdChn6UjWnuy
++cFXClka1cn7FedorfGml/AIc9NBSIWMKTNlfruIOWPSGDjsTiDQZrpBOtvbEha8qZyY76ws/ewG
+rBs4MDbje8Ua66PszJRRybL+qkIyUMAH9CZVCB/y6srMLwHnwaP0ZrC9fuJyDBKAd9pq88dtqsxJ
+Ngjsfmgy56z3mJWlrlnffQdaak086hedtJ4O4T+weeA0mkoVPNw2vZI2x8bIw90E/F0Gsyh0ymW6
+R8f3Qqp/Y0oZ69Y2okBxw/jWbcMronUp44UjyN+BnObkoPE1Gv85iBxdxmkyklgXmrzF9HHr3u+t
+6Inc2X0UdrxAeaTUDdF93oGYYi4KeOPjl6W5kf3fB9UXQ31zKoFTxn8Po0LS2m5Ls/ITDoioYqw3
+1WnihgADBr21LCzyhpNtoagp23wR4+RXsLsUQC9TPhecIAYa4ib+E6yrKu3EmxNEGAnxrJeX3b+W
+qWIulzFyFIcw782MPCubi2O0yUpbuZHj7VzWSy10RYXAkUQmpUtAnIGeFEV63UcHNoAi8fXyW8nU
+XfjBP3VdQDd8KSH9A6S+RIlt7BKHIrfimPZmqRhy2Q9qt7eGgbdwvKS6OESBIyf6TXIKFe8Kd1+0
+2PrREfpmgUH67moPy8Y5DGztsbuVb0IemEL0yLHY49EPDHkqAwz9b7A0rT7ehJHKxds9K7epFZeF
+Hko3MldqpY8YSiRuLhVKxKfwHfo5LBGmF06E4+V9unU10Vaj4WJW2TFSIIi2gIW4gmfVwV/9Az6X
+MW+InU9SZefvXxORsoPOthWanqeSlvYpNjUGO/RUvvY/9kU9SLn1rTKgp00a15Cugp5H28S7MS1Z
+Ck98cEVEcze8b+1BzanTeqNB52Gb0CKKh8sH2M73nqABkoyQJZHsJReKQ9K5NC8TpVFA0A7TxF7a
+9i+yk7vH6AO/OG+tseHcwxJCAGJQ0YADNwWPVtFdomv9SuJBb1rdPKz5xNEB4vNh50vu/rCJdIXJ
++eCdXK7mOdSD5+C0FN1GynICy+4Ca4EMVYyEa15vYM0otPxJuwnYrJR+NT4pK4Aut6e98WTzP1Nx
+GPfN8ttbG9tI6eezyGjvC7OKjPakwRn02NLIZEazpWmxHTgccvq3p8QQ+brQ1mZTRc8UMdTuORgX
+UDIOdf5WMfvAD6M9Pn+uG+z/1D85btg1ahBxFK5hlgcXakSJ12qvK1Mtk0nJDOm8h6rfkAnDSJcz
+qDWZ2HmJJ6iQd4SjiXDZtTI3oqS8GdYz25EQAqrWNKOfgSaLJMIJLDExJqK3lC0VIJjw+DZAJgzl
+NafINijLCr5BJQlul70kW+RebF8vtXlb32dvlk+N7qF4K+mCgdyvqIXiroT6ParIPBElNyt//WY9
+c1FLuROvovFKRqBTczJgCVAFaSZTekRXeRPPs3nyzFNYSD4byH/sGY1mq8TUjQ7BQW7fdFDQk/bA
+J1L2ehYaIEzHdTgMndFDlHqW7lmEQ3QdxVdRI2UbA4VrAbJhA5osvty4dADky3B36kMgQ0cLSPCg
+xYiNf2zIHU5kyjo6tFehnmegaQfumrOQree7fG2gGNBPO1QPvKSAfh36EZiE7/S3blHqwfXHfgeU
+WNfsvGvZbczvq0IimBoDrS1xKqJqCZaqyCwWt0OjBrGwWhDfQEZeEBbyGQanX827/hSNjseo5NAn
+qj49p/GLaaGVvts09YmuSi+7w1L7qA9AC1rvydKncgEQXCfk7UsddE9tHd1/ULmZuTRvRBcbEoWv
+yI8qmyaL719omSnrCPdgQuy+FCZETJ616Wj2d5/ka1gR+bHYVsp6YL7Q505bVx/Aikr5KCe3QrbO
+F/9qgcDqAEACD6RdEEmtZKVlhQMCnfc0X9RF9I4dZ8rDQucEtmwXQXXNsebES8SPLYC81cYS/DYH
+fkLIrPhfZTyhezvxBTgfZdSpexy1qgCsFC9t6IVuW6Lox5BlmJcZ5K+F/GxVxXBHusNmF8ga/DwG
+E+h9pXo7QSg9T65La4ldKltm8+fDC7jA6PaU6vSQcJnert9dmt6pK+8Cd1f+fg5EzePE4GHjdNbs
+zBNCYhbdHiqM3kT7XgxVAADf5dFgRtzEzn2rCJkDRBwckCrUpINxpGGHhga266p5bZkI9tK7VAZ7
+7ZlyXgbUOcHZO8Io9whYMDZEDax5aF3KclpCbRkZ1em57mKzFb9EohBSc9/MSIkkgwe88ieZ4de1
++ONwmSyvlyfD1PL+vbHL+xmAdUqNojhMyUSVReP3ISpLvO+Ck+6AnVagRBMNt98LQ/cutEKjpTF2
+M9LHPbls9ouDv57TiUoVB7a+oI0uIePfrPqPdbZzA4ECYoAFw1Q0YifA7JuqDNgsdMKzQ96RWnZX
+qywPtvw5KNqV96t2DU3N68o408OHR5Fz4YvROvXSRZhNZFYFMZMn2v+QtnonXjFtWWouxxSwii1r
+YfVsRNw6dC5e37KVpSvFsEg8+Yl2esJ7A6G3EeO7Y7O5fTDaiyyCashSJO4f38tw5grwp+t+9+oD
+IOVjT2q36oJzL4pER5zpo9dGpwIJvwq2ZBRYHh+7K6x3sVvvN96t3J+HyoT18QVAFvto4F9N0LYf
+3E8GxQUP7KWEBXKA8MeIRPkBxf9jOQ//YJ6u8taY3GNwHX786HqSj94L+8ULDYipiDqhw3LS1piT
+L1VnisnUPm+3F2yyEXfuq/1VcFOsAbyCDXFNdikZCIZ9exWshUn2DX+YlHTbQguARChyz7fgUu/u
+oqjQo08fNIZ/OH/y2mErPpyJFV69jHLKgsuqM+uLqlVkZtvZ1v9RTMxUxpp8s/4RvfBAxN+NkkA9
+e5YbIObXF7qmV5daoQS7aWbyXWNkXB3uhTldO7fwNW8IPNJEC3OvV+Gb+AXOuiz0TTynfAXtHn18
+Kda/3xYtfRIN2+Pp93kXZv37Bs6bI5It0sQLV+b5M35nLGziXzCLHJaGicyOyzcZNZEshM4/Ldpv
+u4ydgz0cPFBcS/crVlaAbAymOA1FlEtN08diSLSbNPS6Wa82M9D0d9w/uHJBJEN6AmcuizPIevuq
+e9CUUsGO6nbJGCmu3bk+Mwo59CgAQp1Z0VnlXQR5rYvff6j6ujBiMgXrNTuScoDj+2ikPjWxAUVI
+TPYiqVwZnN+4tI+c4gBWoNyDHMaJjKW3uUIf/1izRRSFYoB7a6en6X2ChcJrv+zYUsD/9f8h1bYf
+iboldMjLd3zvUBfxgK76boAcZnSH5oCfvokckVFUARoRYCRaqdT3nu1GXM0T5ahdr9xTZZFMCxht
+yf+XMKolq6WR8viWW0GBbqY8AzCxP8VJ4NlS0GsIdA/LCTJBrS56Fnuce7DTrB7wu2UUa0Bzn8bx
+sv1eu4KBffLgDLfDY3LohNZ7fiGB4Px+Mm5CiKZlSxJvii9wUxMrytx+3xww38SgHONQs+Ep6Ml9
+cgQq2LaXrKw1tiEWiucCqbJV6+T0Y4qBaTK1qDjH+SlokhxnTgCu0gLZgW9YEKYzMKYWJzpDALAf
+h+4QuvgJIwG7bqpjtFngd4q9DlbZ23M+GDFGgMxbky7wO9xwMjnygU8hPrtar3rUUSD4HsixmscR
+mYf7uISbsjvzRQMRZTdokrE/E+DELnyT9v7pZqmDCqSO/PMFwOMG/lPbghb0OuveWWosQvy5DVvV
+m3nkxLKhL9wehqwnrEnavSSo5ff3S6URgc/cO9w3sqy0c59znc/GzvkHO/R8Uzde0j/rEUYFi7GA
+xdHESr7BzZw5VOUmnW7MY5VntjT6Bi7pTJxXnfWck53F3m/UGUufSjM1IC2isRPmoa+T3/RkY3yd
+5ZOzH2OXEHtxMgrWuzjpGOG/avGsjQbsdyVCkPeqVAdzJZ9xVi7MKmVAHGGccnLMhkDU4n+Ubioc
+vYFyASPhmOLK7CBEFEjIp5opyLitIlrFOH5tRovgxdrg6aqpDw1Z5A3D3YEHkZsMtYtTEuTWywF4
+Tr84ywkdncHJoGoWBfKVxHemU+h3n+9SqADkupikgXHJDf/hRvUKwDohanHsUb5b/9PRSP9aKt/l
+4jMo3UTWcecZ4xr7L3Vx07qNsL7oMt2S6y5MLDROm5bKP0zzYL5cChz9kt1fDlq6mvsWz6lmm3yB
+mYtHIwtRDFtwXF4qvFKrGdGPcBU2kil0JHUdPvEtdUVOQyXclpUXKIiXF0s6Q0SgBMUbnitLIfoE
+QVuRWjQBEfd0xgnXOKlyv1RdW+IlM2KX5mV+6MBjr79Rb0/wVAVxXN4PUqVusAFM7V3+QO1G+rMi
+p5fmMyc2poe/iwx7cbqjH/aYGltt5RFWeNzSHpvjsAPJut/mVSukjJzRl62IgMHqn+lBSuejZfb4
+JTwvBt/BK3hMfer5SPHt04dEpasfkkPsx+rTx+m7JaQBm0CRV08Oi2oA7IygVIFPyIUqqtPD/pqW
+aAVnElsqvekWZ5xJuu+jW0E0d3Bbo++DsC6txCZIauSEb6K0rU/K7PPmh2qpTymh+mfWJinJ+IM6
+s4NQlj8URL0wIZUkJDwIKHnupuT0EJ1gSG7+D9KBpl1A1X4G9AFue2MOX3i5zZefa33FxhITy8gl
+eoNMXBgL0IC2gEa/mTBBWORa5kIiP5NnTffoUnueBu4liN3eMx8/2540i5VYe3dOf6tdfkxc+bZo
+cxCx4Iy3ffE+JJc46j2uZS9A2wCG00Bt1fXElMjBHOFN4MULk1DsNUg376eGPw/lhau5yAJyjACA
+fGDf37M1TmMP62928Oa8And85kUozhK9t7ezC0blB6iKXvT2rX5DLrQTb4b7tPdeTcnNI+dy6b2W
+LwIEEy7BEhSP9QhEVrA6I4l5dP19XSlqC4SpWTB9/wod/V/v9x7ATZXM7qYLwtsbAAQRLr/Vy44e
+eDhUqr8AbOU1fD7ExhiyexQIros7H1OwAYZiXbgrDEK6GNtRkLEsGRhww5HPmCaWROd/7q5GAvo4
+oZfStGc2KdOUwVX42dj2By50CyBKxAltIEGzpCFKb7/Rq+pgcqWKp/c/8W8URW0xZGs6d9OMbMbY
+N8lN+ntHazm0ALTYpEJBgnX7bKXKNGb9q5LJ//efVVyB/lALuzoC5RSnh26eLGYKTeU8XHqiLJjK
+g36DkNrFX2xCR0I8kE3XWyP8pbS59czASwhwffXmHT4RBPMw0HcmoyWhfYtLMmUPO08tM5uQCcb4
+R1eI3skF+r6iHSF79AIj5PXghdhSq22AlEvHnf5+zoaaVLS6PPEJ6doLJ5ibyBitffDX349XFeLy
+AL6bCMMzUkbvJcmXtz0u+3h595YoZh4FY1xAwYesMuiblI1X5TZSBn5nVRtUz8KNy3NzVxB9mFy3
+AoO7qmxqyNOtBo99zcgeYrPOsVYROeyw7stOdHt5X8+GJWdGbvlNhBf1zkHxRYKaMDu7HK1A14D7
++I6EdxdP8xXYtkwW1xcSAb8pbZW141DN+AtmZz9ahhDjLTR4C55PC33QdVl0AmLBxoduW9j1fUy7
+ybzdxYxL56MZoslON9ZSHx8VUAA1tFkbmCq0USzw11gbe/v5dejzxLlExyVDtr9kZRBK9Q296Cik
+GKTmLem+njyHQtWS/cmIYNhOgu2H5Qz+PlvtUPYzCqxYPxzPvwU352TaAgaZlV287yhvD0O5c0mE
+H7WuhPiRGagJNPqyt+aqwuUff5LKAYYL40+kbIuiNEuovTNjsQIa0PBeFePkSQ0ex2XuotKO2u0d
+bCNxZ6CFd7HzL85zTMpacyZhBLAdCjq0xDIaBzm8VpuI3cKNPwHdl9CRd6dWZ0/V3mZJSzMld/MZ
+W09N+6xpf4w5lur6gVdtTB7sdnyEt4ULfk8SeKtf39xM8/MWNwd89SocDxnEOghpYHzuaMTQG9li
++ggIudNEG9KDIAWvXWQSy1MCsKNt0mpxDIXw77yVnOqfHPdw/upeZPk1CXfu+1IkfvDkMlV0Tw2m
+ZOCKf/Nh5t4y5fIBZ245JXhP2UUcUBgRa1OPkkZ8O9TIQVvUx4f0qRXL2VAQ3SDYcJLDBssbhcRW
+ysVuEFFD9PDS99fU9UsvlM3CBHOTvO35gUkWqUp1Gmh9bDwLY1NBMpJ6HKCLfBxeGopnQaUEIJwn
+tKtCg4COQr0XfkfTqq69jlh+FTkFc8BZ29TFR73zMd7y/BpDbZa5pjGT317tAqr6eOFdzjLdKbbh
+q7c0nTqA2FrEb+Am2VqrqAK2+gEQ7aJZ7xx/IGwgLZd87OsQqAcJIUixxZrh0tfBz1+WnmeEXucV
+3RlqdUbUYdfq1pdFoEGdEgYPYcGJ5BN/4Rxr0ZmTHJJS1PB2OTDNVzprsGfLVKQN2GZXn1VujuGB
+p3akWMtIjePO1A91WNzNs0zyYEtJ195/A3+gAbem0UTQ3XMuBKnv3CA+dXetg4pZdguA8FUA12+B
+bd62bv/LfOXizyvTx8ZVFIttnp0mTo8JOGnZlEDn6pd/tQfEX0vrxILQmr1pB1cA4ffw0Z9XKFBD
+bAJbJ9iQ4FnaIvc6W/noy5BYU5FuZuvVZ8O28786BG81QalHU4t/OBlv9GfH4tUECF9V4IXCWo5g
+8V1SIJ7FkSNkyD/iPFIap2n7XuNcX26mZsmF6ndnG4pDV5I7b/xweai6v9CTCDzorScgTk5LqRVM
+KolEzbgriNt4ypxM6c1blvFDOZTFR4lwkQQB3QSG5Hc+xBGWnDoBTAgfa/A4ls1SHPjRnXSRPGyN
+rr7TGCvEoSVawNmgkXYKNsRRxltBInpZa2VMokgFYV9bzcp+YEYNbjIafL4mAC9XxSkdnpnvhImR
+mh+fIQT6NdOdzXm59U3tniCXcy3xzbDy9LFJqDhMVKG/YQoF+4tuM+ZLkXtqTMQOO5aPNQj6Ad6o
+d0nyTWoSmtY8xaFazxjPynYZFPx1bL5uePnwI2uSdJOv+Jse3xfQjNQdrgbeyYlxctU2/l0MdFki
+dsj4svsiSUBBW5R7FoGnC3oClHzBuG1zxN8ZV3f+5z/chGS9i62CPaqCc41bhdQCg8lR2yxRtFYm
+KcNDLr9AHyFopzid2MMl4ymWaD/AilWyCV65q2/DohK0j88KaTihniGz3WUQeW8m3QBOjgtch+jJ
+Z0zjNZSXUWgNmajlNnDh8rVDmPIOHvijkZBjD+80L86fu3CL9+C5/CEPOQf16Uhpbyh7MMxCEFZP
+1L72HpVCtWwi3LXmPw7mNHBnwc78lby3mcB9C0WhTCtxyUCG7VAOx1l9owQR6NBnb5Xi9QrgUQvs
+MWhELh6N7ZbbG8TTlNOtb9cOCsSuGCOg/wHl5wXpZkePF14Vw31FipL/4VoqUV9eRx42HuDOohLJ
+LVc40I9TLfE0hpA0OWOuQRHu6QrnvKTX8dixl1YFAA1Jd1R95lZ1M+iqhDl24ecjaYUszHvHJOWC
+vSIiYcoj2cFcl4XS+rYj+0IgcJ9mE27/dSkGrqpUzKseN1b/x+UhPR37YzaUK5/oLGO8q2k+nrHF
+CUpk9Lee6pULMVZu29SRV0D0jQOOmy8GQQ2y6U4wnCys25Wt3q69Y7HYvuNt4j3RRM9dpwJiNyX7
+oUd9dWTVnJm9XIEHCesJbrd9TAoITD3UowAU18MVWzGkZqkxQFJ6llgsDJ31NROGwFiOHYER8DQC
+lwR8XWS6Y6jeGWVG89nuVe+suOITwpMSTVNX1TNXT+/CTVcoRcja8l0AVrKiMe9MJJ+HYWnqIemD
+xnDApQiTFdZkWbN17mBrDaRDmfDDLVNGZ+IXij8KxbJHdP13c7Hk03DelUkURbmayftPqcsPc6CQ
+Dn9QjFjGqEqpg05Tdl+rNTi6etKR6xN49CxM0qFzYPQC/D8phQIJyR+fXxMwntsOuk/gKqns/fAp
+LA8QHczMn5/WKGq9phvHKWWNIIkaAgdoXy9UNc6IBKnkIyb+A3AXWutWU/Cinrnif/hZW53JYWdH
+llDcsep9y+DKZH+ObWD3TR339CcPZSOAwdPykQXNCaZsDiYI2KGQ24tm2ipgEGxjSiYxP57mfMnY
+/S8HOWMCweQFlaHZm0qpxQ2ZmBe56IUmrHX45Y3FBSWysDSX9N/kyihQJXN6CBaAxBvKH9PBeqGR
+DQQKKzl6+xmnVuqdD6zbVg6JUpxh5PcQkQmxcvpyfyCUbsjD3PYzmzA32Ps8uox8dxz7InjkMNUz
+SPFeeOcijRI1v70fGpaZfie8L4sdJNaN5D+uxeCTliIIuBRT461wQRO00PsU0qRmjS4GPzL0+ILZ
+yyso8MkOKJ4yijxQ7IDLv09jJEOAEQEhep+d+b5ERnLQDbXUPVt1hT44an//RjxmlWtq1QHcfJ4H
+tlCikwI8zyZLWFjFwc8Z10q54v3dPq2Rm3X24nGVC+35qQdPLFeDXZ9DeX4MCbUUOIQbG2FftGBf
+4SJCAoliqnoGLqWAZcMj3itog4q9lmx8fW8xb+is088DxJB3T+gux8VehEQdZzTe8yIP3AYUH5AU
+iUqyrFRl8R3TvtEZBXzJLO7gDuTgVXtQ4m3m1dHqAeKgrSuY5Q/kALKkv/Vevs30wlsI4hTIDKa/
+PgoFK/q2ZMHSCEscH08U4fgkO8U0KlrYBI4qfS2Dzq0PJDpzYIsbZAHyjp0p8jdAHlvyz6qsaNUV
++RUDSCWrUJiDe8XkgWHLr70f/dK8ybDOOyZsnrhNl0BVsS5ClIHZtxNK5kCPwbmlcuqUnDwWKLeD
+FO+NRnZ/oXqeHo6Kchjqky78+8YepMu/WnuXRxjwRDW6uUb7SsudhUx2f3Z5Lfq78aFWJGE2gLiQ
+ckyGlhYVuas22qLkW8OKVR6Lhz6SFBbzhLRIKtL56D5lOEVAH+zfpidf43l0rfA6QitSWQV4m+FU
+KtdOkcnGlUo1W6y7g5sw8u0ttqILjO9JoIOWQeM2ABaJzxjo9FE4TckJHiuQV2cSA4gJ1ARBOdPR
+srdQnVhML56iIo1DScrpclzY4atqK0okBW8M9at/Ls0uKRmFJcOeU26DGP8ODYeDo682aM2FOm1e
+OrtSqx3wnmXzlshA9OGs+1pGfj3dTZievFbCWoI8xfZ3e+j4vGnI0okD+xNi0czGD10qSNRO+3zL
+ZjgAJbr2cq1dBB9mMvT2vhUswA1r25L8xxvOfQwrGKJo17Hc1zg/0T/I8mZE2g/HyYJiiGN+PJSv
+6QTCWyXV5+/3igAf0WBAx2jrXGkxjr286UZAjHmB/RhTsfeY2WHri0s4//aAsontvvsr6VzSwAt0
+UtdzRVMuz4sSa2f0uZZm32bW1QS9DaUSzPfEEYET7TdRJ0l2tCvr/HkNqqfZPcT3NcRuBTXI+/Bq
+R7zigP+DetOQbD59oYc0AlSgiOY4yXGrdHcFMC6PrWKkaVea06tDAhOJdDnv3p3H27z3VtM/9+wx
+7rkDIj8rYDBhm2ka9jgeXVujAvKYBQg6B5CajleZe0H1b4cc7n4v/MyAjkLD10aYMpa1TKWhMnhK
+iN5vFXAe1GzgCxzqNVrkr6MJxUTBeyliWZoLTTdMe0UiBUdsjskmWJ68bceQrdFIzIBc2dgv4Blo
+O+DmpwnTtvoJxaSGxUsFZP3eAmyBqYw20UMbSM3qN5y+nhnDtT9GHt/cBY6mvz6wotcA+sR/+GRc
+OjAFSAfYoqHJ2UaI6m9K0aASK3m5PtFwx+BKh08/I57p+1e2QxO/EGtVkC6GST8bWVuToOyfoLkb
+7696fDFKEkYgNdqED6qlXcf9OB2s6MdRNBMh9n3FO1p0D2yji3EjHIfbyHUMYtOPCL9SxL8XyIVi
+BLyjPUJV7Md/aE+iIgmTrY1T0NL/lHeQGDXr/ZNSj+JitUwY09HUouMojrFRpiwtey6UWIszMIr5
+snWrGXwQu0JHEjzw0BSqZGiPs+PcZB4+wjystMNFk8zxaPLgFahM+UNDDY0zouH9OqiEKrRsihKl
+6o7P2JcnCIRr/jzewDIHhoOyHa4lyFKlTpLggatwR3ZFWUmoPLjGefezSC0EQd5XtYn88B2Bkg2A
+SCsluwt5J629VcI4STqith0cZ6a3qNmN2vwjCkYFGmWqgTDs2ociY0SlicnpcGJsDiWVhOy5X1Re
+SImThd/wZsIf6lt5DINUrYd+XCVZ0lSg5FAAumTPPGXrkauMz6LWRK8nDargL/ZDv+Aj0JTIAJh8
+SUR6SZSygLzs4pY1nN6n8EqdRZRYe+b7V/ED2V90hEUqEgyPP7VvzwV1ldzeW80veMoM1/+8V3mB
+GQhL5Q3i1bs3yxhlhI/rAwA2O4iaLDx6oaSTxQ6tzH18AXG2sLAit1RedouwXBsIstNgx3GLOBEW
+LUs3DKyOW44YKedkgI2Qreq3BQQUtsStkoVhkEX7S7irk0LNyTwDpPKm8z6nJj0Dhxt4n1T5dOkN
+SWenWUGFF9C8rrVmU8FAyuMaDJwO79+fgHaXQY0f0QRnLRPKzJkd20UJj4KJw9kPIs5G5LCrgRD6
+xImiLrNRi4ndyoF9HHLA6mVNyAaxcRBEyLF6vMnLb/UfEyJdIGAVjQfo3vH5daUBII7/r5HD61Lf
+W1bzEw7k4IWj4gcfjDVHHOC6eJ4TWEuMRwjGRYL2LE4eW7AsqtQc1X6VErt9v4oCD1mjOoUW0ZSs
+ii8WwnvFQFHVJWkrmm7ahJlZ/0lo/NRylLUai0G1remYgpIoeFGSrFZsdhWNhhYO6NgZM5xer/VW
+G6L8MfIJ+jWujnBW3pI4wHd4gwdb1znhG7W76nl/hRaQP4bHNFf4e7I58tI8X2NzT7Rt98KdQU1S
+FbDePUt/ecDST4RmfBLe3FuVFn0GZuG4rMoUMOF3JQMUkbgqp2BBN9LMrob4KG8NAgHwQMnqujwv
+jbZD8fcvDm0IkVI+BshHNOr9hnHIK9o7DUm1xmN+H4AZXw0tV/MaH0WDyGuM0ou96apyU/+CkWN2
+R0KRoefU6q+eMp+rJ2Aadkpwv5UuOo3HpTpGWNueXlzwEXbe+52jNQS6ok0yHJb6i6jz5USm6dCG
+Rh3uUzj9XdPECkig4mvFkM8N6rD4NZdAee2QltmeVPj+7VbD41s2k7TwX2D73PEJx/GzcfBVOqu1
+ON8MOdrL0vupBfPCOG75dBXSM6DZM6wy32nNuprbbvdosfRXjpM7D3v1PNngf6v3iX+w0tSLUhM0
+gUbpAHpY2tSGddwFtIpViLlLRjMGVP/7TYK2ynH8eQSVrgFdLi+OMZe4KSQX9AcGOLxfFXY8z8Kj
+yrIbjSuh6oGCBWbNNZVzaPm+pA3ozZnP5JR7RrqbY9k7NAmUZFptIiMME+0joNcgsVYhv+GcGi9u
+NV7jCyxFyDAID+vTXZXlNDF9PoHKIu8rYtt/tCiB3qZic5SYv1INHC7mNddi3oDXO8eSPVtEJKLI
+XXzPp7/oE3dZ8HZ1Vn9o1F5cX1N6db5dMAAwVsNkW8DUiAQH9ySU+mR7wH2qRU645MBeINsveHnv
+8KRA0eiE3BWzBg7bjyWajrlkIk8R/wWFiqM0HqtHYeCBu1+yMrVDh6HKMYUUdUSov7UIOsbrtaeZ
+zd4LNA/zJNZgT32cEByOe4nljHsZL9yO8v7Sg/irYcQw+/PE+0xBgbw2I93xDpn4Y/rpK9iOw7KV
+ID6gnxIFIz+v0TeLWg/vGc4rSQKcraeXfML6+GbAQZ2oVK6vFmjtp/psXeNoKoa6tKeNiif0nFZ5
+kjEpc7fIu/M/fL5NCwNwUjVTTiYkrIe2Atk49KGGOSbWIlFqp7rraEF9zD83sq3yCl1F5FXJmztu
+y5wybubqwcGV0lejjpccjX4/vZxopX2Lrx84ps6KSa21S+BwcAhLv9+DSJv4P/Am2DoN5se2vUUa
+HQA3H9K+QVlBU4gliWMXbVhWEj9qZFCMbR+sgy2/JdZXh6U5McPU/c7gz/whlz+VyK8qtvCktDaj
+M6ssdSV7340/ceF4s2vzD2xoOVBXMk0OZ4jv6TJwGSapsSXzLcoE19hCjdY7TBPjPefGsdpJxrwn
+Ic1pV3YFHoRwDUTClFuCIDeJQNbssP1zNC+MsJKTi0WF/M71ZdYb3uokc8fOPCIElwsI0X2TWNz3
+yW/8/ww4pog67xcaH7gjPyWduhR+9H629XcgAWb650JKJf/SzwUA5VzQsHBOrwEO3iRreNUz4CIO
+LiLheRyUdMiqlOVCzZwhKXEU9bA8SYTz15lFkVUE/vBBuQ2a+igMN7RxknETTCg9owRA7r4w433H
+xkw0SBUzhWHpALmhixL2MomM0wBuzU+/0NAFdctrESgxXIl2W91zvawPAO4aX5K+VYNp/ZR9POlA
+RbJmB0no2xaVrHcetF7hScXyhkc6VaGa7IDGEu+Q+QkfiFr5Ur4Y5L7l9QsiSGJaCLq0WfjFM8BN
+xrNEqXA3oo2PrSwjOUD8BXq3r0/7RN8Tz0Pvpt+JjGioncPkh2wrZ5QNyAKAoIJGg9msVAOTNTFk
+9J9ag6zpg79DoeNgiE7s/uUbo5sm46qG5nWlKIGle2Y5qb9qdpeQFT/FBVkJ3mqgYtXCFUTRp4p3
+XLgQfjIkDEcLR4zNuWcMYA+EgMaZ7rVnGpuJn+6fn/+1boOagUwzIfZy9FlhjGYXZ74Te4Iamij/
+VjRc6MGmMnXYo8HKBzSrJgjfRo6Uda04SEPneZ/imsqr2Vcy7lg8O2++ubaErKK/q5akqWWIMTN4
+boIKpBe9GpSkNQVWWok81xjIbLU9Lu1Hs2lvIxcrrNQ+K4mTv1s7lR0ycyb1crpdEmpbPMWHgqR5
+Gyw0jbjObUyV1dVueicPkihU7C4FBukJMRyrcX7MrO5k70o9oi5p5vlJvZmp/N3exUdTc0Z8cBjJ
+kZ8zQo2u2tJKsJCU0Oaex1er1P0i+D8RK/1l1J7Op6f5Hxh5CkondQ8w/puHIZG4fEqNd7vCR0c+
+ieyFN2rxK/PbyzDG/euWtpbgHY4rhlO3TEAQJXtd3pP9cO6CEf0He5FoVQ0KT9Ze969P3wryky4T
+fZyqv8wL3TtadAou7wIbiVDEj/0qPsRKhW+LdrYHe7NhQ0xx1IuEuZM4MGvnGAUa7dPbfI7Gy+aG
+2FrMannSsEb0cFavteOAcS57LYICB4/6C5vnmFZL24saWjaAOsSoMMlNlMnX78o3zSL/1HMrdhWa
+Ndb+pECsksA5YbpXAFpWN+RNg2HMA4guREMZDuYV0NlgZusI5o7ffLH2IwS0I7uy0HR6B1ga3RqO
+Tqa5qgCTTlehRFyPVVCDts+YNGt1M35td8kp9o/IYGjlal8cxlQPyf4TA/eNDgfaplTfEVJL3J+g
+2Gx816RmWpLJx3DpCjJ543lErcDD5yAxyy1xxFtHSM9G0Zdp0FvAvGFwtN5EC/sQJhuznm6oNNNF
+tcwUeIBH04vh4toW8HRjZ6OfbCoz6enCjZK6YnDohRLdbXaqYY2yn6Ii4sOIgyGoTjxl06vcoqvH
+tSJvZSG1qTpHMZ/YGbweaV5VbuabgPTnUkcGPTa4ht4fuX+n8tLLy7zUlhylGUgPcGzJG6pmA3ND
+JxEIXdbiXWEayjayU9rRXYHoS6FvL+H2vleciqjGmAgnqc/dsy/U6IYW1KiQKVaEd2+8cpqNPzXK
+2DrdfPhlAa2VXgh2hQQuyOi/yVKMA1Gv4GLAfe65IdJIUn81OR9Z+DAuG3p+OYbJFM6lbWwwdQNH
+nkn2djZU/kf+oIregnocooS4dhAOKOn863VFBC7CsGIpmaQRC2UXrJr8qZaSlblJedQsjgsE0ZLr
+0e1i8bre9sLOJwruc0kRMgWPzxzOrjPsPjUNn4wjTBrXCHW0mg+ZjJ8IcTRk8iVqq0MNHE5oTUPQ
+pucTHbLjIjh9UFM89Mp4JOvDOzCCoa4Bu/ihlt9XIAXygfK3kEHdN6FM/lCBXTC5mh4ZduQRiwEf
+lKw9vvQ6/cmY1o2jLU/7QUhFwR+OA47nlvza/Q7RYgF4xTSm54PGPNvu2entQJebXCNmq5D4W3A/
+iQ9Hj1P8rVoaDZT2BlOB9CE5Lf3U1ZMV5Yp6EMSX7bmc05mBxXrvtFcdWGjyFNH2XjURj+JkfMln
+tzYXKhxKnKxufBqm8ovoo3zzgF9vvOj/wmTv0HvmaoXJ3EVvfhmTsuI+EQzkibx9UytZe4Lj0oIG
+wlQ8ZMmQtMAYY/+Yz5kgSmBzqxv4vqJ0adanCmyW77I8l9+SVSCZFGQjxOGvw5mK1jzk/c4z0i4d
+BD89p2MHBkEe88DdPMtqyS03roAY+BdF+7RBuWpkzKanBE0hBMT7rj63f7KZYHzDk79kkDxVr5+9
+essNFYMRNAcu41IC9WyTpae0aqGYBlWJReb6Uu5gSmYKWgyLSCQWsEi5bH5ATUZ3NlTSylv2dkmp
+O75h7Z9dDtbMGTM5gpm0NH/iiS9zoGmpwVgq/I1ycV9cbcwEscaaCRNZkHMIb3pMZkYPJNSr+aXh
+pUG8h3R2FVWzetJxs3aQJj4cQRrzcEf4t4An84qoPAIEcnbLneevgAxuVUuAYxdmPXPxQYxojcWI
+XxfqnQZjWBAeXwH/FuZABde5tNu5ijuNVHmvLDxMmSOFK82IE82WMz1YiNQ1yTWBUFCz4ghFuO+w
+2zjMYh/Z/w+4PbuPgjRg07jNB3MBaWVenR2Cup5B8wcS/2Rzsj2pNYZgrIXiWYEGiyKnC+wgehpD
+aCDVFSeqjE2qaapQQyZRhU5LKc4ix0qdJJpemcBdIDWHBV1vCwUFl8GK5KRaCtlTQkyuac5EcoXy
+tHwwf50tjlt0hA8THeT0pT3RERKOhbgNFDTwjqKGXFq2NsOAM7GhtNx9KzkA9rShTMtaWSJTpT1C
+oho5XDBNvaJqC0GhmJM5xar6r+Zi4cr7jVFqMxpV01IlPBFYzLOgagknH4ovbDeMdqGHKPcrbPvi
+ZtE+N5bg24VCBa9jYkid20qHDR2+esjMKcVupm3jfxJMA4f6MO/Jzio9nh72MvPA6O6XLNuJiGu9
+pMZbjTH0f9709QaXiuOE926NwNtPuUmPQ1WCEYIGksiH2+w1PvEtiqKhd4YE0ZBSpqPdZXMOgRZX
+b5J1pF3EbfNGKipwQk0nTAF6hleR9hqgLcRpwuc9NIo0SGWDJZ0UPfcbh3IR3Gatpk7mrvhzs3lg
+yU8S8l894J7zutsoJ7rksmgeE3KW4qG9h+De9y2xsV+8YVOqtY402YeyITOE5mZYg6FSmgMbhj1j
++VsNR3YdWF59eZUI6Be42f8tkJ+slZIB3gSetY7CIb9FgJGPLF3oNABqnNX5yxtl++1RaE+dGhPq
+02EvWv0QgBKHdEQlsz+bG/GN4W2lRs+cb7CAbc9UKzKSUn+VWF7JKouUSROv7ARVpog6Jl0hV1qC
+pw3PoVy5C80lXDcJWlIz86l6qPNSUndetAa7VaOQsaSeMNn37nSaqPEd4gkwPXqEMPyabcr4+Z+2
+C8bQ1pkzxcIBZewQcntvSN2XA1Ff9ZFXgKZjBBnYIycOPOyfwQsvGQwnJazjW9vW7ZDcXD3Z/hJv
+l7w2AsX9Pf3vejNK57N80WE8Lkx8I+WfNTsgX8JIUJUBwOhEDNhbXDCqyVFQqfhJZf0WZoIyX77Q
+/wtDqFiSccvdh7Et2OOEiWio7i+CuYVrAZJWn6tjqBxaHIklWoaenTYYWNN05b45g63GAwBb7c/p
+I9PUZluvQ4c5VYHHPGT7nyROd4bPpTdlYcZTXoUJz/4E2r49ZwgBUY8+wt5JwY4xAvHgZvE4gMt8
+Ce0COtdbjmcAXQv6LrGIBAflnfm3C5Rv5pm08wwbUPuKVmEnFAjQvYsZ5tN6GjOlu/bfZIw7Uswr
+ZquOtrmijJJeElPJKQRLZG/EVTKlrQlCBpB++k/uW2WeZFDIAIROP/tPcmMmN2+FgMvvZOJ8bgFd
+nN0cu1Y5Dzfr01sXjzavNlKYjVa/58iqxQ/280+Lo+sKWf42cu+c1wN9vIBDFAeWe61ZWfTZzmQj
+kYHCAW0YV7nxXlsHyj6HcB2Hm6rrUOYSmzwYmqkHJlDxDGnPnj59uQZLvJbAXj9mDarvx4/xbhBb
+cxQ+n7aw6ZMJc+gJm2HUVQ2U2R8rQjS1e5ARqVwqu783BBH0TkO4czbbsrNt5jbmMCCGdeRPNVzJ
+73CALK+kLBHCmxgACnEWzEhCWpjho8+i65CTR/Zfg/sFb/yRJLE4/L5UdS9T5WwKut6dYpnwTjOL
+U2MqOlqoU2aaNreHnwqRgBONRjNham6VFtQ4hI5yGK/EUq4nG3aOIsYHLNxoTMycazYW0F3+CPZv
+v5LiTkHlN/QKhtqrs/sxlisQYaU4E0ol362fYFEAEpzwDY/Q0dMrPQ8PW73+MWCZwonSJjaMORfY
+aqiW+aB00nW/bhUIFA/yrcIEUnfJwBoZPRycsc0QUrpnnNB30jXylQSa2U+/kSfhmOt5XLDpW86k
+XyLmIdkN9AyOd+UKGfqO7FJ8iNFiwSbYsqFDpwvbZfReFdLxxlS2oDknumiYqOj6muHXqkJYHnhz
+t6kHhIBSRZRadauy7GsYMZF8vJri5ifULpJ7s5RK2/eGCVX9hwGARuFtqpna1rpRIUy+/yR8aJZn
+C7Is4KXlGkMq3J4HfirGFwRY/kJJCjZOhVIkFzNti/tJIDTIYTkfUeYmBuHjRgcDuPi/dS09IXvv
+D5t5PnADyRXtEgUv5AVz9WIkIWE1+BcV8yqoW5Kd/OQuTQf+PheJtKpYfEnEAxDbOZLU3lhhsU1u
+t9A/Nd1SkUE58A8V3CbuVlmLSPQ32YNFXEmprA1/JPu1LBZwKYwUUUfz09czriTGB1yP5iuJBZle
+Z4rnqeTBabIwc44ftBqKSEbD0Ufb7AXoKZqkRsmozAWNX8kaiqco2O5tEJXLEZkeDC13OW4vNTuW
+Uy4bZT/tKKeqW5vFwQ/peKRArOebLfq4QbGZ9l6OR37nJOwE3EyP6BaxWm4+LKTf8sAXURbJ/v2G
+9QBs1jzj6sa6sb1T39aeG7o2BLVXx3Y/f5zALCGrXSn+urJ1b+thKpVWezhB998a98fBIv+kKjUZ
+OFPkYJaBbF5twujgcA30c1SjbSeDGEr43IZ0Ojbwhxw4tkSnObvqqu944oW/SApbAP0uSnWFUot+
+nMM1+e/niOcB5Z0uqHVr2bECw3EeWns26zeTSX1lVPOkW/Z6+0eHJE+BQncIZ9YlJwIpF0vUpof/
+yLDeHLEPDwoxJPD3jc6n8pktmTmJOGrYzpbmNMPZHqGFAx/s2kqEI2qUCnc7y9QDdZcm2aKMSQZI
+CddaG3dKvOlnHZfsGB3BN7gbgeiiOvsSffF17zdYk6eKJAmPw61fxpuP/e/QXsXffMdM/Jna/t9N
+85S7DcDwvmxNf2wNJFayjPEcLIPwht9rR9ixDPNDKNTO3iuyP7PNCZHxz7S4jkBIkK/etRmounM8
+zmW2NEjowdJt4J57wVop09qvja01tqfLkjqzJGn0lDUWUw21jxB4cMM1Yb7yWRzPJLNBErB2wnME
+XjnIIdk4LZClsUCbyil+jIMlUOopBfPj1QELA+CUr9bIVJrrRdwcd7jH/OGT
+`pragma protect end_protected

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/c012/hdl/sc_switchboard_v1_0_vl_rfs.sv

@@ -0,0 +1,225 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+XGGMPfBY7p9xYNhQp5gx0kkbZqEYg1V6nNG1q0CVxqW04VNmW3dymOj4eRt13EVnnL9hcHtSZ5YR
+Lp0nwF9dvw==
+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+Owjnt0TbWxw68IVZ24aT/iH33VJwKjcNETvUQVpJLckJHlKfJ236RYKBSid21gg+nmUowqOjyW+L
+40etkBdHFqy2ihRMIlwtI0AJ4d20v/1f9fnv7EZw837rKKzKmfHttyXLqTjsoH5k7mq1vMSSCsUT
+ONmjO0W+aT4YMfI5p0E=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+L7guZ3hdg1adyNA5OAj7aD7kAB1r8cl2vZs3Jc5QbHgmPBznukiyoUjAg8LuCAkZhBLOTQkfcfeu
+2jHDKS/uW+GCrsK1A+8odP2EtEbO0AnovZL6UHxZkuZgIx2wqLU8L3yCnGVgGkMIGN4zJXyrIUxb
+4za0IPlTwmRV4qFA4vSl26II1lJh4SCnS68h8djencx5zkxkJ81PHyH3g3tlLacJ8svuOHLD28n9
+iiuXDaPzWuFJi6DfFOU3oH+iehVKPIT38Gfog5VIGVYFfKvtwNeJ8Mk+X9z3gnlLK3ps4+xr3LE6
+6PIpJUk+zXxghb41NyNuQsvbugqnUS4f7lky/g==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+uA7xlZu/H6pApXefuSSwrGerFZprFnd+WD9+hwvJF0Evfxq/4yJgulOmw3Yu2QzssPO6wo8CVf8d
+D+2fTS8KX8f8LXQDVc/ClfuRjlAsDJeKtI01udAAJ0DuuLAXwTJwMgFlOKvwoNXjqAOFHiePEvEB
+ZZ0dHX08Ba6e2kjHT85uNCqr1AeoND5undy52nS5r4UWKJ0KdMeLpKKNeALPeCWsUkTgvL+nzn3D
+ccWQXxCyVr4sMwCWW4PkuiVtvOPJUJ3+oxK66fVTpRPiR67qXe5APGhyayXYd2P8ZIG/c75f9F7F
+XZgfW3n9DC5Q61yw4+mhs0hdwHcevUCYLWWAoA==
+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+HY1TM5xb93l5+BPMqT4QuAdeBrmoIG5Mj6UpTerT2xwpF7LvTUPvbrIHZjnXoaiCEb4AXDGBNFA2
+IZGVw0pTxULttJZJpYcv6o2W30/79BKFywOSwoBLOkxg/uhGVpJLWe3vvMtuXy2uhb8yPna12qWO
+8Mp8gKrNyVoDeA7dgc2Qji8siTbSlfztqzaIqsh9lljQKyFqLoPJUAWlDHYM1aI53dL6VdXxs30D
++nzIdXLwRy7ycaZbQk2RnmUKnBo9/mxwzwNwgM4/hrTnlPahorn8Bu0uzlbxVU5UIGUJJTEs3Fed
+b6Rs2nFJCainMWq2aBgHFXrsfPtftV58y0OHrg==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+Gq7cl2fc5227azJ01MUxYywjk6K3uXhS9VtnszNgCyTlGQE6N8bQMl8/V0Qxn4CHxvqdjjkh+sPx
+r69w6/0hxZH5yx6dIseFVXSc3bOMfme0sB6q43+FaKuArw1lEQst+rRpZIsb0IOLGyMPXqW6PoN6
+YOQo+MqS1ymdaETmWsA=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+FqzXT+mv69HGhudZtRodwj78R9AzCaOdWnhLh+dviy7ph3TqkTkBZw6hbfTIpb6Il7KcCT5ca2dl
+HOdTrd/9OXTyPqNCPEUGzEB5VVzI897XizTzea5Ixh0IgsDGhg7Ep/DHjYTNBkKJKhj2dfK0BEkd
+rE0wQ1dOO9QvTgXT1Vka6YnK7EXoNb5L+ZBWXOtuy7j4WHIrQXvERBNjItRKXuKW7rZrSMNBhyE2
+y8X7nSI4ip24YFQ2xUUWvLIBdAAVjOEscT/m6CUXP9gjcMKPo7jhlWPZrLRjsKbAcenpw7TFMytQ
+joQw8eJONzVDF9bbEwgorW0StJ9X2pzhoSPZfw==
+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9136)
+`pragma protect data_block
+xIOfE9yOEV3SPiwkE+5JEoNWs9KiJHtFpBbDCRXVynCUb/lMzxtoINPUIJ1k066yHftNVSvN0aIL
+ojMndOwXLFkWHTXpJoAS0BvfSCsKlJfK00x/mZBzP1j1GVoBfbD/2XLDtgrUZfJQHYEvdUe3lUzv
+P1ihRBWt7QwOmIkBRU0OETZLsw9+9uvGtXHxzj2XQewGeN0sO6SKbOrE6mkNygclR8tvJ/P1hmGZ
+uC+nsmQIhBxHIaSpru5EtLU+oWzMxT2k7l2Ngu3qSHBn96yVRZdRBSzFTpwoTzx+GuIwNMACV9V/
+IazYGvyqmfg/wUNi0YJjgS41gb7yZOKu+xhyCdi4YxhYFgR6YnES89emIc3GCUoMiddBpWyfg7Mj
+GMsT8Wefw7aPNOGh6kugYmO6Q90jx0RgnUypll0ZomLDiBI1qTjQF9tnQPl5sRXeQcJrlVzUSJbY
+k71BDWkRHijKy7ohxGkV40Cw/ce3A3PNOgvz8g/8xGP3qwui8MsN0Vww2VhOEW4RpMsJsa2DflTP
+f3q0N/sMiyLnOJZu9/i8xTgltYYnCe3kRth3xlTay4pdiHB0aCsII26Yg23kl7Gl8icRS9g+cUCJ
+Dvk3FoxHaZXAi2n6D5APpNO5N6z9CVaiXNlQRxty5MyxsmNy1kJbs6Rng5fAOLCRYRAwS7Z1F/Du
+sTox2ChVbjAu+aUWrb6VNBET53xawxp2/uofYJ2LGbpZOm3P6jHODjlY4QlfkB9toYIJ4H1SVtkf
+KBx+ogS10u/tgVz9sJzOclrhTSn99jvfWNRJ+ceiloM4O3bk/2liswsGh+hMeYXWhGEwbSOPh++O
+jFV2Qwgl4+Q7sVCIr7QOS9KQWK3o4PZauHq5WPddSA2FfG4SCLhqMyEWsQ9vQ2msHHu5+bV02Bs6
+u7TKzhNnTFl+uKeRDORRGXFsbbQAoz0RCIK7P93gJrgl393CIPyt2KeNE8VvXnfTjzymZW+aCKgP
+GOkv4O+NEvrKEFhL9VDfOz2GW80Y86u83TbkA1I270+bEcsRSIung/sgSpaHiikfTZr7ijn7PvCV
+UFZa2mOtUzObPbiLFPilkvMZWRlxneMH3UW1aaPQkdge7QTISFTIYS03yMODpGVaD/AK0qZK5YO8
+wS7SrJceuoooT5835ODBw2n/KfnmmLbDy2Zd8UIonB/bpDpx7z6BsJHcO7Rvo4fLZqaGqMxBhaU+
+LjMH1P99qELiZRbexr7/rSoVr6RKjLl9KHtzOqdoLewM1B5GS85lOnuihAV4ZdnnHuegfigV0VH1
+s0QX8BjP5NHpbeqzzHJT/T40sKx02/HEhII3C9crqCN6oVjytMDBOC3s31q/fRoiolsF3gCsdSZt
+O19fEK34IMY8iPZntsfB1QHqXvtIk/GWKu0rY7fj7JKYChep1dvrctB3HSGRzBfPKaLwUPvQfwUG
+oAivMzzfr428JBXcZc/Ek8xzd9qjZ92ZjQbHto/kb8EYARr4pvBzb1tKnQaBN7GEYVnyrKWp/LKs
+PFSCNuo/VTR/pHmd3PI7amXxMAcSAadL9cyGCEWQAQ8qvkwomjlYJ0FmhVpjm8bd+pwnMkSuucWM
+K1v5DxxI8VRGP5FNTq5oUq8HBOVGe4d0ErXLpWImeg57zxmPNrGwBsvb49cGNPv46T6bYL/lqmTN
+LGqL37o5FFC7+EvuxQbWw4W5W8+rzKsGPn4ZuSABRcUaPuoAitXq/ZBQg5GEwVZ//ihFUzC5w9UB
+5Q4m/ijtflX5t+/acJtGF5moY14m+vFLvyWenVdifJFwQIE7GjLToELkabcPx1CU6MwCRzzLOnXu
+ypP56CmBFJB4Mog6xNc81WVpKmDmXmHuaBt1Sx8nR99qA3USG1i4tob/yqfUdq3Y/BetK8wZoXCr
+wGj9O03aOtQQCx6HRhD1vhoEdZyXvWu85Yz8WVKP1T9Th2LSSGsl3mZnx6HczbpKXOqK6Ru7m24R
+N/EHOJv1qPrgWMFeGwQkJmejIsC0YMgJC1pMkMFSI5qyEs3uSqvv3ams8zPEwrQsqi+Wi/AIx6Qe
+hXvBzFN780zIrHVjGHTuAIGotstbCMIOVqs+oCjwa8/auwS4GuZ/o/+VEHCQPL3d/17FowxzKDZ6
+bM4IMRLDYpNv9N05vycA0ZNFv54JR5/azsYILzjxjSZ6c9Xd5r8kL4jldOhhdExk/WwDm75cI1OW
+myIWv86otwYlG/CNphz+pYm1E5Po6AcO8G1yC0ykfwcIAlvatJHc1v2Wm1L6grLtz7NgPPrBMust
+epD/0DwvLcMOXjC4812j8ARFv5yTZx8I1rm8Tq99FZFGTk6D3lJzwRhT0AdoLY9wStd1bwiwsccP
+eNFyi4t7PcyRxSlnKt65MLRzN03UTSUXhvpC/yj9nNS1m8oFHPI+ecSYXpVz3wu6R+dToxxZmf79
+U5z6NLujTZXXPECNibO3G7/IGBYyhY9e79cQcpiKeT/jajc12dHBb0tYMROYMsOfdCHefsRW41CI
+XapFISweAu9nhw3WN+k9GaFap9k/uPdabZXuztN9EE1GHa3Pe0LQQMsAZJxwl4/4so195dWUdYlC
++/7AuhF0tHMoJw5RSEm3yhRwED6Nok/2hk+ZCgJ9Hd55hZvQZMz7C46wV+4+ahMMbg7YJWUsvXI6
+Ph6Asg1rZHlIg3S2YS02lUgkFHL2z0cWPVV2fx5PrsCQ79XPEYv6U9bj3oiQb6P7mcVxKeqEZryE
+HSueOXPffNaiARWLsK6EV9P62Yl30Ll6dkmUV/FeLqF4NcZ+zEvijli+3CJ9zrKS0nBNuzFE+Dhq
+/NzyiApYurCIqpYuBJlEFTn54xVpycXsQPHojAAZxY+5jJBD66NdLT8ERuHYWXJQ2Ly9yIvQ6Giq
+fvhqoj6gyhTZ00zyMHQne4xo5tZ1cEsgNecSBLy6ZlY5xV1cF6z44sOgMoQtC0bYhZxcSVe4SQKr
+CWQGr3UGkeJpytDncsJXYHlSyp0xn8YqyLdFLDtAH1H6a5sd6XaNqq7XSqxwCeX0QRBxOMiCCH7D
++FUPsd9YnN6RxWntzQCKevd1MeD/lxJwaThqhIeFFqC6tjQdYjW2w5uqqOB1HeJryEDYyno2fNbm
+rL2jv0qJTzejxBAy4Ibdru2o3zxCjd/e0VQoFsGndFvqjc9nr7gYcEjH9vqltCRPTuLU5gINLLaz
+4DZ2StcXJweMIrdCESfahYIE5BYG7aACqF8+U2mjutmTTNaesjjZWcJ+It9FbUxAc0dYKMZ5DFKG
+rio3rkagbOOLsctyZrMLiXnfToLugZt4YuabvVwTAXbMJgL4/PAD8AoRY57wvMpGMgZXpkvRThyY
+x1sgjTsjJc84oArUZ96ismV9bm1CYdZpPfX6yGsEpg/FcF+sJYBCMzeWqmzLREbqETCB4C+NZdUm
+/CHnxkYU/5jJ//TLi/q7TZMn6voKq1STd4XSpn3hSNPiX7wjI7sNcBeyng2y/e3iKYRG3hoyB8Jz
+aUQTeA9TDhqJB3XZ12Bxql2LrbN9oIrtWot+Crts43xrpv+6jaaCNNI6As9K+Cah3CKuayxw7sHR
+vey5qsVswvsuGgVc+U1vf15jMRuczF+HoF+APjXSbqGYq1zV0xZ8h2WFVBaFKsEB4PSDP5KJ4Ys7
+ZIRVv87Z329DB4dD8sqQyKWhIdFuDDDkwTQ6a+vnP0DDlSZ0Wr+sBCx/kZeTss8piWNJtjPA+ZHx
+3ZXDhzF79SYcOO5spWjX5pCNodZqUjC71syUrZXoTqqrAvgoo1tpU2NI3opPHj/UCQbp2WWaHVDL
+WYYQYZPN2mLvJqvw2gI94F629asWkIlb6ZnKTAg2pqUTEg3delEGaI4r/oj/TOFJG9cm2/6d59kb
+YGT/k8JmCCMCRTN+xpQCtT6mINbvZn2PbJgvUK1M4JQrQCtDBAbQe6JNMUHZWCiuCQnEjn/ohMsP
+daWVo2YRAiRVC7Pd7E+eJD7cLoZ1kmat4gkiWF0P4ECDihh+Ba9lyHd09lE5qeW56HybsbMeHJik
+wsMv93RZ8ITIKyfO5lLVw0hrhFyiAZBAbj1KVMnnoGN02usKPC2GZ5SVu41kJmYm/Qkyov3HWWlt
+vy/A0kRuSGmuKZFutehbLsZkJ1zsU5dqbHLdFU8VTJtOuKgd0Gh6zncZHAfgXmV4cL0T7gzivXS9
+ukuVTjhPmsVxwIxHVMSWr//EP/FEePr2XUEgqPUZebx1ngcP8DIRXEhnV7QAAF2VrCJGyHMfiGTH
+B9YN/5eVGundh6Gzk+muCLc4tjubHtVrdoLfq7L89QmZwE6byjikJDvFZ3Xv0bYdFvQQt+AmGyHD
+m/nlHfgFZlvwz8B2oGLQtnSd5q1RatxhdqgL1Z3ydgaoXOmjV4ptjjXtbW/Mg2mObLaRwm9CZxU7
+tZ7EvAJdnAV07Q9/mRULhxNaTxhBOwCJFL5PSWPUUwqSS9U+yfcbzXpyPa6D5HaPpQCQWOlek0ln
+H+cZdamQmLoZsqfG8/HNGd1Vz/ehZH5Ir0g5PSXLNmbzvldGqYwXOLIIUAa+r89mlE18a++1usxq
+YNy1EQc9tm8Q0orCZ4kmRNDj6clnk+dHqnEfBe+Ind7X+BR3kT2Wd1SoxAx+gzPl6kUZvpeTcO71
+ZaXEE+0c+Ednu5afDzgQqBdqu/W6WEE9ruY8aen8oJwH2K8lOce1XcJxtBv8GSUaoW7Lj5Qadkxt
+cHhz0pUxoAxQ096o3/RtIOFM/2LUtpsAXUl5Be1/EvDD9smAgeg+aBW20g6JpeVg0H5cv0v+Sd6x
+GoDd2YYAuUvrJv+X19wV6XyIjDxPJmjZPRlg+m88cP3KODZckpTPlpsMAwuAOlMTpRLb5Og4UCwU
+tDrNutRNAP+hKgsq6D0b/SCF3TNoa/BbOr+YVZYZC4rcAr5v0V1n6QYQFBvyrA9prNsSZXSnBLv4
+guleh3PkSaBlb/L6M5u5WSpVDwQybOjDsLbVoWV8Q8XIV6GRVFw4Rbi3CdZtasbMBBdQHRn9wVq4
+ofOSaHQHdP/8Xu0j1AoWmh0wnW9j0UJexPBIrw5/hkcWYxnOTvjfFR3i3yK13hlfJFOF9/T8CPmx
+PAOuiXfDhhFdQgyfOpgAVFpYThdaDWEAJFBoGjB9npkDaTP1SkhzW5GlnoJxcfuyhhPlBwfDHTa0
+rT6kxRoswlZY2CbVYtBnzS+P+HzIyUF1Rh+frmH7c1n3IIbxVKc7A0fr4PS3+u/kQX5zZTmdvsxA
+D8yvtHQ+KguzKVvUpqcST+I+R7gXBGm97N0yXc+DLwxIjFR05Jq1ZuMXIEAJ8vsNiLXunEhJTQQd
+FBszCU490uxoXYn4YEEt+dBBc1jMup/tpZ4+VLHOMek0S4gBJWffECaWLGXhlknJS+vP33tmKW8o
+eEq6lFUxXIe8Pq7wq9Zr66jnPiMzwI9QKyXF+MyrokerBzbk1D4vOi4GQuuM+QwTBrdqiT3SdXPD
+9lxcNjA+7ozBTb7INs6xyp2U5LChNJBhE+rFTo/5UFIeGBuHZK5VjRhqTsE/ecjO/FdBGCmwFpa5
+Ok5ynpuCU1BecuvNQzGEpiymyckZfw2Z8QqLxtnRnMB9EppRg6FIASDB0Xqi7bKE4h703sgDg55L
+oL0VnPuIyPUzz+ykPloP3kwOBVSaXQWYlg3z7XHWbHcGygYjEzwvVIytTwDfTlPPpRY15BORF9dv
+SZ8AXJ4nFV1/nQAEh65Yk4TLxFEcSn4TQsoe4YbQCo69RsdiOIiv7A7/ORSkkrWelYo0At4QWqXe
+CPRvnuxJydLewxxNiPPwSdAiDmKn3QRxZcN5jk654RsBCJIq25hU9MrQN2DhSRe5FeB+g+Xpk4aK
+5QBa+WgQPdsTKOaMtLKuZTkvUmmUInrkC3MgPK5+F+S6Y4KkBE06j1eghhQUoisvkp2Mcrq6MA/B
+AgwOG6TfxiMfazboPvHhfl3zK/sLU1n8uY1vm9HD/sMX4QoP4qHRcewT+Y9v458QTWepqLrUDiQW
+72F9biq7DD5uxIl7hZ5+ToSS4nVL0hTm7mnM/ov1nDBQVdATiT6uaaHDySlzztCgEfEBS4GZNfru
+V5eEIjkp/T/kV/+QpaYI5x+cNWGS2MhMz3+4lhGkwT7N/arGKZ17xG3tMLOxnDG2WicG+opkxR5e
+HPm4G8g1v/51BCQaa8sFTXxYlCtZMSAJhEFYTVgLeLi47/N4gzAoCrS8E/Cm5CV/gJnZchGLQ5PU
+gC5hipUw67i714sdzQwE1O0YAjzSGZdPZYzxbMA/y5Ly+Mp5a/II6R8nYLZMgH9QhfmKLYlxNQs7
+3RMIcKoDlHihvuMvxvz6FEzMY0hUCXjpJ7DDhmcIF+hlZVMUnJIttWsc3EVzguFYlRpPL6o169UV
+NHHoLSeehuB4XbDynKiRboRk4OzRsGvVp20jfuy+kmgzpniKvgnUsn1zqLN6st4Nyh8HfWz5o5oZ
+ghELUYIZ98iPpNfqXaOqx2qkXPAa34qod8XEJlytbvQ6TeqF7IR/ANUQEtrSryG4A1MVDQ/g84N3
+6GgjFPkujOLd5K6+YhFyPKGTEqJSfd2AXISrWwbQBHiqjmIPJiHG12Yxr/ENmc1UKx7UCBVq+W+W
+2PNymc8m170ksoK8mm/IS8/QUnxyWBRfDgaLjFGABEIiY3oRfvGwkSAJgyIicDnAlNOZJJQfviNC
+8mxdW/ZlA2Bbo58cFOHt49bmDM9r1s5ev49QDAY5VVHDWZGORwNa5Cba0BgvSunO4DA09tW9jzyj
+TqPTdo/b0Wlju3jFb6q7EwUhC8VYGuSPneVFmSQeciiWPmjwP5OZ18iLRhCtiXMtG9aiwmKmwP3c
+ymL32meJfFXL3MhhJffx6GAmS9h5mk/B606jNlrLTWYJrSc1QPcnU/2zExSmmwsaus4iNtQWig+4
+IvJlnjXY5aHboQGXfGXS+gtHd4mbrjWChRv9E9/JIMzeovFX7VpmO/SPclvZe/OigyPBqm2VbqQb
+55b3kflDMn71TAV/ofKldIDP+WfXKQCPpxfRAwU2i5LTAwMQ6JUZzYkA5tAlEi3TWfsTShueyvLR
+uHXIiU40YO4Uztpofb38zn6XeZ/wVzM3AaYRT14qG26X73KxQzkYhU8MoqpGO7hHbWAUmCgqySTQ
+qF6iwNt3xzHAAW5chz2vUYdmRQCSwWnk14OP17WCUQoyCMfShqNACno2mf5Dpf/0JpgajadcVOaB
+tQKC8oBF2Ud39bXrd5mdx7axksMBKMvMZk6crSRzXqoFqJiM1j1zzO5/VReeMYP4iN9aBKIXaCr4
+8AGhtNnrs/xCgP6sxxlYjAiT6xNJlkOvMDKDaePOFf/Qwf7RHTkjx8nfLmuUrt/+UT6WUqBMWvYY
+I7TpLgPaCBBqxU9lsclBTVh5Jw+Tx4MLCq61FyeT+lTOS4cLWSdzXHpAMM4Npll6feXG0Da+eRNx
+gDDxjDOVoNRMS90aQYClGPyCmXLDpeoP8Yn7ZkcJMagohlQBbXSCOal1JQKrIm0Lnope++nZS136
+s5kJqmodL29SlUsCtxZgzGa4rJ4t4VAi1MMACPGf34MNvAh39aFXIGS8jJD3vz8o0CUp1nyGlj7S
+RcV3oanMLmksDOkVrnuj0P1R/3K8C5xJEbRQdLB7K1GYaI3Tku2qw0riCfVaw4ufhGZ3oF9GbTdC
+5cirZkRI+o7VLG5b35WNQEsiKkW3gI9L1KKR16ys7y5pCmk0oMhfARXnMcG5wdome+Tp9jRFz9zD
+J/6uEpPlhsI5LV+k67YC1bAO049l2uOfl7L8IIDUT22kGS8SBQR9+EXjBleNoc6H14PZ++k+mEBb
+yVo9dwOzQo+7oH8xcEAR5ABKL/F7azxioT73kN0Pr9WIe8OQX0vQrG0vzYzzSwVbCs9wr3YZrrtL
+IBIycK+TLl7ugycY3GL94ofOJFFoxZ4Bv65GrHOZ2dedr6FcnZyBd4iKLXSGCwYYATYoOHZ5UOmP
+0BzO+krlBNzCw1lVEpy3YXJqguR0FSMsGcD0zGPxPse5gSOgiZfgj9X8tolsFerEhlc4wtiRzDow
+DJd3EfGd2U81RlDhxbYffiO/dKdQ30IgpfH3inef1Hr6oUsJEcc6Tqs87/u0KydT8X4dcB1idiPd
+0JcojSMJzD94mog0dBY/O/2l/TRPQkefofj0xqpdT4bHQorwUT+oTlUSeKMd/qA6lwaqqvdY49dF
+fzOrElP4fZRGr3nQY4SYckNZwNSTL9ope/TgGni9tzgA96xJiwts+y0j7W8ldt4LRi9jxmLAdP/i
+X3f66qjQuZUliwXEK7INn2S64/D8dHcIUIEGMg9+oG+bxxztLNk8O150h+HSGAuvgeuX9PRkcpqc
+gpFW8Z0kRlnUO9DCQjcURWs0aHgHz/cVeFZQmOY0IBcMSGbBzjaM5GYOx3ksdgOalOkmlrJGV7/Z
+46y+6EAdN4ooiKz+hc2ruxmdNy5hlayB36FzM4gSSBFVYnUdHXcE4qJ0pFxdYqs9DHaxBiec5d6L
+H0H53rrF2B4e7LXXiPzUicF0MkhZHF87s/NDzXtAlxHwhVX7K+83NjBJDOgyYHpZtt8K+Mu1ofT1
+DQieyhZjsGw+n5ps8FtoTgJqJtttALbM6b/FwE180wisaT4jln3P0elpnykwtFBn4rpAK1MS7Qxo
+B8ucMWb2jLvIYhe6dIwwCBlAI7WLtwiQAjGrnMkOmisw4oSFv01STNt78kOWOlv+aocZG/vkVPsi
+knUD5YqagzAOtlYLAd6dlCQ2/0Nk0Kqb8//25qVdLBogGW0CKnr9K127ct9+n7UXRspee37tRC62
+V69MW6I8AjRE+P2pqbvfgxz0sBZ7A6PwtunGC3nxQd4cWixWr/BHIpSxBgiKcn9tHLcj8erVRw4P
+P0/xVq/BnsgXoxMhk8vTWgu6OTFsn+0ZWfahj59SG2cWtPe8QfD9rK6mvXHoVWzkoEDS3YmXw8k/
+7kLN3NLrMT4nDS75MRAkOsxGiejOBPA/FK4X70GLRniqThhOavo9vYw/AtbeaAqrDyufG205gyUs
+iQC4Kluw7IYSIdj2VdlX396PJqqUhPJB3ByACDxvbkRLpg9769j/KcPQG1LCJafGa1TwaevEpT+0
++GqBcuV9+2IhIKfRA/uXR7y9a5w9Ie/jiTbYK8HnQjWpgo2vFn1Qe2+48ETuddd18cbpbQjGONmu
+ZhNNXJdP+eX2P8UslzH3sab6Oov2IM+HpiathsxnVUuNzbhusuezp2oREJOY6xfOjSAKfNv1EM06
+EGRMa2xGGVmpBj6lf/mo2DF4CXopXB+BWpmEXsASuKfSeLp0myxkpkZtVQisRtxLuGCtaluIs1fw
+KWA+u+zuf5S+j6FbH7lw86bkThCYagT5bOElmfCZ05FoI++pl9Kg05ujhR2jRcARL+lUGVocdDlG
+ajjVLpIxoXoT/kkjpT8EsOpQkBlfqjKZBR/Vftuyx4S/imXFfT4I8lzx9lDAQeVl8WBPRMkCPkvf
+TIQompwhNk/zHo6qXt/jhegIz3XiJ0jRIsS/+J+o8EHf/rhEyKT5Uz0cyHZXx2syoJguEMNmc3il
+q/sG6niE8tKLvFEbuXyKSMKuqhvfC5WCXgBrGHebSuHAy/DojQ4AgIEnlfJ5fnXSU6gFZAdcjeSb
+iHoFeVG41XimR8zu6cecIlMw0umfVd3tVvdh0DpKS+qitMQK0AbCKPMd0EV4NcA63J83kfzE0Cpn
+LDCoXfZWrnLFtjzv6bO/HxgscJJRjAB2cWXtkOROoF/IkcDXO7o/Lw8QQHGZoGKgHoB6rPF40Bxw
+L6flO6y+u82+3aTm2Sv+H+qk9kcmzi0KLA+TxgIkImX4lJMZrrhIT24No6q6ps+CvQylHTUCTbkx
+2Qo1bHQwZlnHC8wuDAK+xOuL/z2+L9jXGySeBsjtGlmyKAeziZwLzQRFcdy5x0vVpwBG+ext42Hq
+iAuKTeD2WXGjiJ15bxruDcTCvYIl1GBiRaoGMtCA67dcrhuN3Irzwtv7squnFzNqboFQQYQ/FAA5
+b6fLubnOIZ5cq2XWQeoE8HL6byU9D6oop1SeqszV9nIMGkZjw0CBoP6xpmjZvN+qkTbiscjh9I75
+OEzkyzRWLKm947YMJqb0onE7TtSt2F5XDxfg0bxmfcCh983qZo+o8f+idmTeyIS+LHy4Ttf9AWqe
+H/NmIeDcryubfXnRjPJpzFMkznGxthHNqM81Wf1Yy0Y1LwYlF0rF/AHUlu9zjR7c0geXXuirvKvc
+Z/i4g0H1/DDvDqP2G+3q7nubVptKcnXn7asA06q3Q5pILwnt7CmOB6HFfUsCWHUbn64uPEZYCZ4I
+iFbS1EIlSjlN7rf7XI/d3AKB8m4FepZoZ9WmwdESEj2BhuNYQ1BAqXKNq+jvkErpBbKEmXrdJIZw
+G+9VUi8hDIDVg9rK0IWXKrbVvIDxKa+92auGpAd4adJhvw4MqNFcKiL6fBO/G6eUWxFKSfA1L6KX
+BbhA0pHBsuMl+QYUx5aMV5z+Nqddez210QYIq7ukwdLszJrZiUU9P4sm/M4iTa7QpS9SDUktOh4x
+ZniwIGWJzPRpRJHpdAA5DTzko6MCwPPx0kZLu0jcC3KCkKDkWpwwP0vEsEk8zoWVxm1UNIDZvA14
+eZnVDGzoLtxJNaDYU14ggoc1TdhO7tbc2A3vizf5uM977zr/XUtYUZu4c+O2poygf5z0i/9vbGEL
+YYr1G9vo9h1hFUVJD21L5Z7WnTiAkVXmjmLNFmctV+36QnkIwjVsDUgoXa0y8EkPrksyswZ01Q9L
+OTeW8zGffqY58OQyxe2+E3jE7ZyoLkJ5OMggRAAuHhdOZuIHDIZU5+iqHvs+Egd2XMt9YtFE7/Z7
+IbQOYZp3f2c4vxbLQdFakdR36GRfiVOaJxVU2BVal8yaNuuGov6wRb5wnqWqqbkuRUhlSvX5X2kh
+7s+Kkpu5vErnDDfGnS/2dLuA+FH5P2YUxKqSZdybajTnM4nQy+aPp63bMaGtdfoWKJuoXzm0BMsZ
+iOAab/zr3qj34WxLCT3vYopzWcd5cHFcqrAKdhAZN7bhvdd5HL5DVzk6fPPnYnNp1GO1dgxqXjbw
+wG3FxjIIjyMHp5K4DWezvyWuR4seBp3uSzf+FjT7Ss10iXR3/NmwO48Z3oiBrixAZBeIYILPwEJR
+eU88xPQDb+vGf2E/Blxxa4qOLx+ZV53PLtY6AkRa46BHATekvJ0a1Fswv6BJzJLJFPr6VB/qCA8I
+AOfKf8tIieMb93eRVI3p8iALt1Hi4tRRa8pxqxJsRgNYO6zmQudXLOkkRxLDjlEqOjRtWEE/WmCI
+IyRL5TggrSBZCmVYltyh3YINKc+K2HSpx2Vw21hRGclVRQlLAH/3+G1kIpLD/fozMQCjO51g49rz
+v11I3RQuY4iUWK9KJtVAzBKSzpEjSFoEDN3Rwr7bO3luY8w4fsFs0GoJiVaMq+HPmQPcSn+7qY5f
+ZSgn6mg03wnfUJ/Tl/Pr7+zdHuyGD1agUdZy6H30m659O0YL7BOo/4Rol7aszg0jUgzspsSGwdIl
+rWp8I6DxgVWQ3a4R1d25hW4Z90oYFo0SAqejrOfGLVFVYQwW1epfKOZC4nwKfs84nxahpdczCIQ9
+kP0noqzKuLMNKKzYng1dgZ+c6P4UwrsiZPfWWyg3WXZwTRMH5MRXL/PaouoNo3pYYmKp/oJRiTaH
+fd34aiAu5Rn1xKTWozGTbTltQHfLqIJ6y954XGyQWMpGFNbWnKmE1bZfxaszBecs3z2NPN7r/71o
+40OM1cGPZ2w71UZEfgVnHc7S6RJ+QyLUL2O32oTOWDbWFJbgYyILhSNYihlyGT18T5ROkJlNTVB2
+X3Q+Rm4ih5hI4Vkxz+2F6JltKBZpsh9cxPle7qgtlCuidJqjCDsPdwhC4SrubVLyKvmYmb4jecBm
+NSPqVis7nWXfBFV1PRAS6iAp1/JgR5FKxyBffGEZVDZCrlcnoHRLQgzYOXqn1Lolk22kU1LqehM5
+/Qt9Im+c6G2HaaULd+d13q4LKxLV8gV+HK4gadmLEPYSgo62urLzR8gMF9keYpvwA92BbqsMRhHU
+A4/vxocWCtH2c26IqsAibyJgRgqDpXKofypJpjWXWQTGH/mg8VcCkqNed2WUOEwQ97RDkBfEKmhD
+By2/AKb28s1h+UoFzSSTEw==
+`pragma protect end_protected

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/d4a8/hdl/axi_vip_v1_1_vl_rfs.sv

@@ -0,0 +1,633 @@
+//  (c) Copyright 2016 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// AXI VIP wrapper
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+// Structure:
+//   axi_vip
+//
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_vip_v1_1_5_top #
+  (
+   parameter C_AXI_PROTOCOL                      = 0,
+   parameter C_AXI_INTERFACE_MODE                = 1,  //master, slave and bypass
+   parameter integer C_AXI_ADDR_WIDTH            = 32,
+   parameter integer C_AXI_WDATA_WIDTH           = 32,
+   parameter integer C_AXI_RDATA_WIDTH           = 32,
+   parameter integer C_AXI_WID_WIDTH             = 0,
+   parameter integer C_AXI_RID_WIDTH             = 0,
+   parameter integer C_AXI_AWUSER_WIDTH          = 0,
+   parameter integer C_AXI_ARUSER_WIDTH          = 0,
+   parameter integer C_AXI_WUSER_WIDTH           = 0,
+   parameter integer C_AXI_RUSER_WIDTH           = 0,
+   parameter integer C_AXI_BUSER_WIDTH           = 0,
+   parameter integer C_AXI_SUPPORTS_NARROW       = 1,
+   parameter integer C_AXI_HAS_BURST             = 1,
+   parameter integer C_AXI_HAS_LOCK              = 1,
+   parameter integer C_AXI_HAS_CACHE             = 1,
+   parameter integer C_AXI_HAS_REGION            = 1,
+   parameter integer C_AXI_HAS_PROT              = 1,
+   parameter integer C_AXI_HAS_QOS               = 1,
+   parameter integer C_AXI_HAS_WSTRB             = 1,
+   parameter integer C_AXI_HAS_BRESP             = 1,
+   parameter integer C_AXI_HAS_RRESP             = 1,
+   parameter integer C_AXI_HAS_ARESETN           = 1
+   )
+  (
+   //NOTE:  C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
+   //Please refer xgui tcl and coreinfo.yml
+   
+   // System Signals
+   input wire aclk,
+   input wire aclken,
+   input wire aresetn,
+
+   // Slave Interface Write Address Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_awid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]                              s_axi_awaddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               s_axi_awlen,
+   input  wire [3-1:0]                                             s_axi_awsize,
+   input  wire [2-1:0]                                             s_axi_awburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               s_axi_awlock,
+   input  wire [4-1:0]                                             s_axi_awcache,
+   input  wire [3-1:0]                                             s_axi_awprot,
+   input  wire [4-1:0]                                             s_axi_awregion,
+   input  wire [4-1:0]                                             s_axi_awqos,
+   input  wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0]    s_axi_awuser,
+   input  wire                                                     s_axi_awvalid,
+   output wire                                                     s_axi_awready,
+
+   // Slave Interface Write Data Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_wid,
+   input  wire [C_AXI_WDATA_WIDTH-1:0]                             s_axi_wdata,
+   input  wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
+   input  wire                                                     s_axi_wlast,
+   input  wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0]      s_axi_wuser,
+   input  wire                                                     s_axi_wvalid,
+   output wire                                                     s_axi_wready,
+
+   // Slave Interface Write Response Ports
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          s_axi_bid,
+   output wire [2-1:0]                                             s_axi_bresp,
+   output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0]      s_axi_buser,
+   output wire                                                     s_axi_bvalid,
+   input  wire                                                     s_axi_bready,
+
+   // Slave Interface Read Address Ports
+   input  wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          s_axi_arid,
+   input  wire [C_AXI_ADDR_WIDTH-1:0]                              s_axi_araddr,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               s_axi_arlen,
+   input  wire [3-1:0]                                             s_axi_arsize,
+   input  wire [2-1:0]                                             s_axi_arburst,
+   input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               s_axi_arlock,
+   input  wire [4-1:0]                                             s_axi_arcache,
+   input  wire [3-1:0]                                             s_axi_arprot,
+   input  wire [4-1:0]                                             s_axi_arregion,
+   input  wire [4-1:0]                                             s_axi_arqos,
+   input  wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0]    s_axi_aruser,
+   input  wire                                                     s_axi_arvalid,
+   output wire                                                     s_axi_arready,
+
+   // Slave Interface Read Data Ports
+   output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          s_axi_rid,
+   output wire [C_AXI_RDATA_WIDTH-1:0]                             s_axi_rdata,
+   output wire [2-1:0]                                             s_axi_rresp,
+   output wire                                                     s_axi_rlast,
+   output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0]      s_axi_ruser,
+   output wire                                                     s_axi_rvalid,
+   input  wire                                                     s_axi_rready,
+   
+   // Master Interface Write Address Port
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_awid,
+   output wire [C_AXI_ADDR_WIDTH-1:0]                              m_axi_awaddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               m_axi_awlen,
+   output wire [3-1:0]                                             m_axi_awsize,
+   output wire [2-1:0]                                             m_axi_awburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               m_axi_awlock,
+   output wire [4-1:0]                                             m_axi_awcache,
+   output wire [3-1:0]                                             m_axi_awprot,
+   output wire [4-1:0]                                             m_axi_awregion,
+   output wire [4-1:0]                                             m_axi_awqos,
+   output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0]    m_axi_awuser,
+   output wire                                                     m_axi_awvalid,
+   input  wire                                                     m_axi_awready,
+   
+   // Master Interface Write Data Ports
+   output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_wid,
+   output wire [C_AXI_WDATA_WIDTH-1:0]                             m_axi_wdata,
+   output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
+   output wire                                                     m_axi_wlast,
+   output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0]      m_axi_wuser,
+   output wire                                                     m_axi_wvalid,
+   input  wire                                                     m_axi_wready,
+   
+   // Master Interface Write Response Ports
+   input  wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0]          m_axi_bid,
+   input  wire [2-1:0]                                             m_axi_bresp,
+   input  wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0]      m_axi_buser,
+   input  wire                                                     m_axi_bvalid,
+   output wire                                                     m_axi_bready,
+   
+   // Master Interface Read Address Port
+   output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          m_axi_arid,
+   output wire [ C_AXI_ADDR_WIDTH-1:0]                             m_axi_araddr,
+   output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]               m_axi_arlen,
+   output wire [3-1:0]                                             m_axi_arsize,
+   output wire [2-1:0]                                             m_axi_arburst,
+   output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]               m_axi_arlock,
+   output wire [4-1:0]                                             m_axi_arcache,
+   output wire [3-1:0]                                             m_axi_arprot,
+   output wire [4-1:0]                                             m_axi_arregion,
+   output wire [4-1:0]                                             m_axi_arqos,
+   output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0]    m_axi_aruser,
+   output wire                                                     m_axi_arvalid,
+   input  wire                                                     m_axi_arready,
+   
+   // Master Interface Read Data Ports
+   input  wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0]          m_axi_rid,
+   input  wire [C_AXI_RDATA_WIDTH-1:0]                             m_axi_rdata,
+   input  wire [2-1:0]                                             m_axi_rresp,
+   input  wire                                                     m_axi_rlast,
+   input  wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0]      m_axi_ruser,
+   input  wire                                                     m_axi_rvalid,
+   output wire                                                     m_axi_rready
+  );
+   
+  /**********************************************************************************************
+  * NOTE:  
+  *   C_AXI_INTERFACE_MODE =0 -- MASTER MODE, 
+  *   C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE 
+  *   C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
+  *   Please refer xgui tcl and coreinfo.yml
+  *   User can change PASS_THROUGH VIP to run time master mode or run time slave mode during 
+  *   the simulation 
+  *********************************************************************************************/
+
+  /**********************************************************************************************
+  * Master_mode means that either the dut is statically being configured to be in master mode
+  * or it statically being configured to be pass-through mode and switched to be in master mode
+  * in run time. 
+   
+  * Slave mode means that either the dut is statically being configured to be in slave mode
+  * or it statically being configured to be pass-through mode and switched to be in slave mode
+  * in run time. 
+
+   * Pass-through mode means that either the dut is statically being configured to be in
+   * pass-through mode or it statically being configured to be pass-through mode and switched
+   * to be in master/slave mode and then switch back to be in pass-through mode in run time
+  *********************************************************************************************/
+
+  logic runtime_master =0;
+  logic runtime_slave =0;
+
+  wire run_slave_mode;
+  wire run_master_mode;
+  wire run_passth_mode;
+  wire compile_master_mode;
+  wire compile_slave_mode;
+  wire master_mode;
+  wire slave_mode;
+
+  assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
+  assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
+  assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
+
+  assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;   
+  assign compile_slave_mode  = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
+
+  assign master_mode = compile_master_mode || run_master_mode; 
+  assign slave_mode = compile_slave_mode || run_slave_mode;
+
+  // Slave Interface Write Address Ports Internal
+  assign IF.AWID        = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.AWADDR      = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
+  assign IF.AWLEN       = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
+  assign IF.AWSIZE      = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
+  assign IF.AWBURST     = slave_mode? s_axi_awburst : {2{1'bz}};
+  assign IF.AWLOCK      = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
+  assign IF.AWCACHE     = slave_mode? s_axi_awcache : {4{1'bz}};
+  assign IF.AWPROT      = slave_mode? s_axi_awprot : {3{1'bz}};
+  assign IF.AWREGION    = slave_mode? s_axi_awregion : {4{1'bz}};
+  assign IF.AWQOS       = slave_mode? s_axi_awqos : {4{1'bz}};
+  assign IF.AWUSER      = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
+  assign IF.AWVALID     = slave_mode? s_axi_awvalid : {1'bz};
+  assign s_axi_awready  = slave_mode? IF.AWREADY : {1'b0};
+
+  // Slave Interface Write Data Ports  
+  assign IF.WID         = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.WDATA       = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
+  assign IF.WSTRB       = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
+  assign IF.WLAST       = slave_mode? s_axi_wlast: {1'bz};
+  assign IF.WUSER       = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
+  assign IF.WVALID      = slave_mode? s_axi_wvalid : {1'bz}; 
+  assign s_axi_wready   = slave_mode? IF.WREADY : {1'b0};
+
+  // Slave Interface Write Response Ports
+  assign s_axi_bid      = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign s_axi_bresp    = slave_mode? IF.BRESP : {2{1'b0}};
+  assign s_axi_buser    = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
+  assign s_axi_bvalid   = slave_mode? IF.BVALID : {1{1'b0}};
+  assign IF.BREADY      = slave_mode? s_axi_bready :{1{1'bz}};
+
+  // Slave Interface Read Address Ports 
+  assign IF.ARID        = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
+  assign IF.ARADDR      = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
+  assign IF.ARLEN       = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
+  assign IF.ARSIZE      = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
+  assign IF.ARBURST     = slave_mode? s_axi_arburst : {2{1'bz}};
+  assign IF.ARLOCK      = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
+  assign IF.ARCACHE     = slave_mode? s_axi_arcache : {4{1'bz}};
+  assign IF.ARPROT      = slave_mode? s_axi_arprot : {3{1'bz}};
+  assign IF.ARREGION    = slave_mode? s_axi_arregion :{4{1'bz}} ;
+  assign IF.ARQOS       = slave_mode? s_axi_arqos : {4{1'bz}};
+  assign IF.ARUSER      = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
+  assign IF.ARVALID     = slave_mode? s_axi_arvalid : {1'bz};
+  assign s_axi_arready  = slave_mode? IF.ARREADY : {1'b0};
+
+  //Slave Interface Read Data Ports 
+  assign s_axi_rid      = slave_mode?  IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
+  assign s_axi_rdata    = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
+  assign s_axi_rresp    = slave_mode? IF.RRESP : {2{1'b0}};
+  assign s_axi_rlast    = slave_mode? IF.RLAST : {{1'b0}};
+  assign s_axi_ruser    = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
+  assign s_axi_rvalid   = slave_mode? IF.RVALID : {{1'b0}};
+  assign IF.RREADY      = slave_mode? s_axi_rready:{{1'bz}};
+
+  // Master Interface Write Address Port 
+  assign m_axi_awid     = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign m_axi_awaddr   = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
+  assign m_axi_awlen    = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
+  assign m_axi_awsize   = master_mode? IF.AWSIZE : {3{1'b0}};
+  assign m_axi_awburst  = master_mode? IF.AWBURST : {2{1'b0}};
+  assign m_axi_awlock   = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
+  assign m_axi_awcache  = master_mode? IF.AWCACHE : {4{1'b0}};
+  assign m_axi_awprot   = master_mode? IF.AWPROT : {3{1'b0}};
+  assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
+  assign m_axi_awqos    = master_mode? IF.AWQOS : {4{1'b0}};
+  assign m_axi_awuser   = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
+  assign m_axi_awvalid  = master_mode? IF.AWVALID :{1'b0};
+  assign IF.AWREADY     = master_mode? m_axi_awready :{1'bz};
+
+  // Master Interface Write Data Ports Internal
+  assign m_axi_wid      = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
+  assign m_axi_wdata    = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
+  assign m_axi_wstrb    = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
+  assign m_axi_wlast    = master_mode? IF.WLAST : {1'b0};
+  assign m_axi_wuser    = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
+  assign m_axi_wvalid   = master_mode? IF.WVALID : {1'b0};
+  assign IF.WREADY      = master_mode? m_axi_wready : {1'bz};
+
+  // Master Interface Write Response Ports Internal
+  assign IF.BID        = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
+  assign IF.BRESP      = master_mode? m_axi_bresp : {2{1'bz}};
+  assign IF.BUSER      = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
+  assign IF.BVALID     = master_mode? m_axi_bvalid : 1'bz;
+  assign m_axi_bready  = master_mode? IF.BREADY : 1'b0;
+
+  // Master Interface Read Address Port Internal
+  assign m_axi_arid     = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
+  assign m_axi_araddr   = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
+  assign m_axi_arlen    = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
+  assign m_axi_arsize   = master_mode? IF.ARSIZE : {3{1'b0}};
+  assign m_axi_arburst  = master_mode? IF.ARBURST : {2{1'b0}};
+  assign m_axi_arlock   = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
+  assign m_axi_arcache  = master_mode?IF.ARCACHE : {4{1'b0}};
+  assign m_axi_arprot   = master_mode? IF.ARPROT : {3{1'b0}};
+  assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
+  assign m_axi_arqos    = master_mode? IF.ARQOS : {4{1'b0}};
+  assign m_axi_aruser   = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
+  assign m_axi_arvalid  = master_mode? IF.ARVALID :{1'b0};
+  assign IF.ARREADY     = master_mode? m_axi_arready : {1{1'bz}};
+
+  // Master Interface Read Data Ports Internal
+  assign IF.RID        = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
+  assign IF.RDATA      = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
+  assign IF.RRESP      = master_mode? m_axi_rresp : {2{1'bz}};
+  assign IF.RLAST      = master_mode? m_axi_rlast : {1{1'bz}};
+  assign IF.RUSER      = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
+  assign IF.RVALID     = master_mode? m_axi_rvalid : {1{1'bz}};
+  assign m_axi_rready  = master_mode? IF.RREADY : {1{1'b0}};
+
+  axi_vip_if #(
+    .C_AXI_PROTOCOL(C_AXI_PROTOCOL),
+    .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
+    .C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
+    .C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
+    .C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
+    .C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ), 
+    .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ), 
+    .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
+    .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
+    .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
+    .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
+    .C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
+    .C_AXI_HAS_BURST(C_AXI_HAS_BURST),
+    .C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
+    .C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
+    .C_AXI_HAS_REGION(C_AXI_HAS_REGION),
+    .C_AXI_HAS_PROT(C_AXI_HAS_PROT),
+    .C_AXI_HAS_QOS(C_AXI_HAS_QOS),
+    .C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
+    .C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
+    .C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
+    .C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
+  ) IF (
+    .ACLK(aclk),
+    .ARESET_N(aresetn),
+    .ACLKEN(aclken)
+  );  
+
+
+  //synthesis translate_off
+  initial begin
+    $display("XilinxAXIVIP: Found at Path: %m");
+  end
+
+  //set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode  
+  generate
+    initial begin
+      if(C_AXI_INTERFACE_MODE ==0) begin
+        IF.set_intf_master;
+      end else if(C_AXI_INTERFACE_MODE ==2) begin
+        IF.set_intf_slave;
+      end else if(C_AXI_INTERFACE_MODE ==1) begin
+        $display("This AXI VIP is in passthrough mode");
+      end else begin
+        $fatal(0,"This AXI VIP's mode is out of range");
+      end
+    end  
+  endgenerate
+
+  /*
+   Function: set_passthrough_mode
+   Sets AXI VIP passthrough into run time passthrough mode
+  */
+  function void set_passthrough_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 0;
+      runtime_slave = 0;
+      IF.set_intf_monitor();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
+    end
+  endfunction: set_passthrough_mode
+
+  /*
+   Function: set_master_mode
+   Sets AXI VIP passthrough into run time master mode
+  */
+  function void set_master_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 1;
+      runtime_slave = 0;
+      IF.set_intf_master();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
+    end
+  endfunction : set_master_mode
+
+  /*
+   Function: set_slave_mode
+   Sets AXI VIP passthrough into run time slave mode
+  */
+  function void set_slave_mode();
+    if (C_AXI_INTERFACE_MODE == 1) begin
+      runtime_master = 0;
+      runtime_slave = 1;
+      IF.set_intf_slave();
+    end else begin
+      $fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete  non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
+    end
+  endfunction : set_slave_mode
+
+  /*
+  Function: set_xilinx_slave_ready_check
+  Sets xilinx_slave_ready_check_enable of IF to be 1
+  */
+  function void set_xilinx_slave_ready_check();
+    IF.xilinx_slave_ready_check_enable = 1;
+  endfunction
+
+  /*
+   Function: clr_xilinx_slave_ready_check
+   Sets xilinx_slave_ready_check_enable of IF to be 0
+  */
+  function void clr_xilinx_slave_ready_check();
+    IF.xilinx_slave_ready_check_enable = 0;
+  endfunction
+
+  /*
+   Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
+   Sets max_aw_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_aw_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_aw_wait_cycles = new_num;
+  endfunction : set_max_aw_wait_cycles
+
+  /*
+   Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
+   Sets max_ar_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_ar_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_ar_wait_cycles = new_num;
+  endfunction : set_max_ar_wait_cycles
+
+  /*
+   Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
+   Sets max_r_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_r_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_r_wait_cycles = new_num;
+  endfunction : set_max_r_wait_cycles
+
+  /*
+   Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
+   Sets max_b_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_b_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_b_wait_cycles = new_num;
+  endfunction : set_max_b_wait_cycles
+
+  /*
+   Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
+   Sets max_w_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_w_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_w_wait_cycles = new_num;
+  endfunction : set_max_w_wait_cycles
+
+  /*
+   Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wlast_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
+  endfunction : set_max_wlast_wait_cycles
+
+  /*
+   Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
+   Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_rtransfers_wait_cycles = new_num;
+  endfunction : set_max_rtransfers_wait_cycles
+
+  /*
+   Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wtransfers_wait_cycles = new_num;
+  endfunction : set_max_wtransfers_wait_cycles
+
+  /*
+   Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
+   Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
+    IF.PC.max_wlcmd_wait_cycles = new_num;
+  endfunction : set_max_wlcmd_wait_cycles
+
+  /*
+   Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
+   Returns max_aw_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_aw_wait_cycles();
+    return(IF.PC.max_aw_wait_cycles);
+  endfunction : get_max_aw_wait_cycles
+
+  /*
+   Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
+   Returns max_ar_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_ar_wait_cycles();
+    return(IF.PC.max_ar_wait_cycles);
+  endfunction : get_max_ar_wait_cycles
+
+  /*
+   Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
+   Returns max_r_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_r_wait_cycles();
+    return(IF.PC.max_r_wait_cycles);
+  endfunction : get_max_r_wait_cycles
+
+  /*
+   Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
+   Returns max_b_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_b_wait_cycles();
+    return(IF.PC.max_b_wait_cycles);
+  endfunction : get_max_b_wait_cycles
+
+  /*
+   Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
+   Returns max_w_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_w_wait_cycles();
+    return(IF.PC.max_w_wait_cycles);
+  endfunction :get_max_w_wait_cycles
+
+  /*
+   Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wlast_wait_cycles();
+    return(IF.PC.max_wlast_to_awvalid_wait_cycles);
+  endfunction :get_max_wlast_wait_cycles
+
+  /*
+   Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
+   Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_rtransfers_wait_cycles();
+    return(IF.PC.max_rtransfers_wait_cycles);
+  endfunction :get_max_rtransfers_wait_cycles
+
+  /*
+   Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wtransfers_wait_cycles();
+    return(IF.PC.max_wtransfers_wait_cycles);
+  endfunction :get_max_wtransfers_wait_cycles
+
+  /*
+   Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
+   Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker) 
+  */
+  function integer unsigned get_max_wlcmd_wait_cycles();
+    return(IF.PC.max_wlcmd_wait_cycles);
+  endfunction :get_max_wlcmd_wait_cycles
+
+  /*
+   Function:  set_fatal_to_warnings (not available in VIVADO Simulator)
+   Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
+  */
+  function void set_fatal_to_warnings();
+    IF.PC.fatal_to_warnings = 1;
+  endfunction : set_fatal_to_warnings
+
+  /*
+   Function:   clr_fatal_to_warnings (not available in VIVADO Simulator)
+   Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
+  */
+  function void clr_fatal_to_warnings();
+    IF.PC.fatal_to_warnings = 0;
+  endfunction : clr_fatal_to_warnings
+  //synthesis translate_on
+
+endmodule // axi_vip_v1_1_5_top
+
+

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/e1b1/hdl/axis_data_fifo_v2_0_vl_rfs.v

@@ -0,0 +1,667 @@
+// (c) Copyright 2012-2013, 2018 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+`default_nettype none
+
+module axis_data_fifo_v2_0_1_top #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter         C_FAMILY           = "virtex7",
+  parameter integer C_AXIS_TDATA_WIDTH = 8,
+  parameter integer C_AXIS_TID_WIDTH   = 1,
+  parameter integer C_AXIS_TDEST_WIDTH = 1,
+  parameter integer C_AXIS_TUSER_WIDTH = 1,
+  parameter [31:0]  C_AXIS_SIGNAL_SET  = 32'h03,
+  // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
+  //   [0] => TREADY present
+  //   [1] => TDATA present
+  //   [2] => TSTRB present, TDATA must be present
+  //   [3] => TKEEP present, TDATA must be present
+  //   [4] => TLAST present
+  //   [5] => TID present
+  //   [6] => TDEST present
+  //   [7] => TUSER present
+  parameter integer C_FIFO_DEPTH       = 1024,
+  //  Valid values 16,32,64,128,256,512,1024,2048,4096,...
+  parameter integer C_FIFO_MODE  = 1,
+  // Values:
+  //   0 == N0 FIFO
+  //   1 == Regular FIFO
+  //   2 == Store and Forward FIFO (Packet Mode). Requires TLAST.
+  parameter integer C_IS_ACLK_ASYNC    = 0,
+  //  Enables async clock cross when 1.
+  parameter integer C_SYNCHRONIZER_STAGE = 2,
+  // Specifies the number of synchronization stages to implement
+  parameter integer C_ACLKEN_CONV_MODE  = 0,
+  // C_ACLKEN_CONV_MODE: Determines how to handle the clock enable pins during
+  // clock conversion
+  // 0 -- Clock enables not converted
+  // 1 -- S_AXIS_ACLKEN can toggle,  M_AXIS_ACLKEN always high.
+  // 2 -- S_AXIS_ACLKEN always high, M_AXIS_ACLKEN can toggle.
+  // 3 -- S_AXIS_ACLKEN can toggle,  M_AXIS_ACLKEN can toggle.
+  parameter         C_ECC_MODE         = 0, // 0 - no_ecc, 1 - en_ecc
+  parameter         C_FIFO_MEMORY_TYPE = "auto",
+  parameter         C_USE_ADV_FEATURES = "1000",
+  parameter integer C_PROG_EMPTY_THRESH = 5,
+  parameter integer C_PROG_FULL_THRESH = 11
+  )
+  (
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave side
+  input  wire                            s_axis_aclk,
+  input wire                             s_axis_aresetn,
+  input  wire                            s_axis_aclken,
+  input  wire                            s_axis_tvalid,
+  output wire                            s_axis_tready,
+  input  wire [C_AXIS_TDATA_WIDTH-1:0]   s_axis_tdata,
+  input  wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
+  input  wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
+  input  wire                            s_axis_tlast,
+  input  wire [C_AXIS_TID_WIDTH-1:0]     s_axis_tid,
+  input  wire [C_AXIS_TDEST_WIDTH-1:0]   s_axis_tdest,
+  input  wire [C_AXIS_TUSER_WIDTH-1:0]   s_axis_tuser,
+  output wire                            almost_full,
+  output wire                            prog_full,
+  output wire [31:0]                     axis_wr_data_count,
+  input  wire                            injectsbiterr ,
+  input  wire                            injectdbiterr ,
+
+  // Master side
+  input  wire                            m_axis_aclk,
+  input  wire                            m_axis_aclken,
+  output wire                            m_axis_tvalid,
+  input  wire                            m_axis_tready,
+  output wire [C_AXIS_TDATA_WIDTH-1:0]   m_axis_tdata,
+  output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb,
+  output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep,
+  output wire                            m_axis_tlast,
+  output wire [C_AXIS_TID_WIDTH-1:0]     m_axis_tid,
+  output wire [C_AXIS_TDEST_WIDTH-1:0]   m_axis_tdest,
+  output wire [C_AXIS_TUSER_WIDTH-1:0]   m_axis_tuser,
+  output wire                            almost_empty,
+  output wire                            prog_empty,
+  output wire [31:0]                     axis_rd_data_count,
+
+  output wire                            sbiterr  ,
+  output wire                            dbiterr
+  );
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axis_infrastructure_v1_1_0.vh"
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+// +---------------------------------------------------------------------------------------------------------------------+
+// | Parameter name       | Data type          | Restrictions, if applicable                                             |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Description                                                                                                         |
+// +---------------------------------------------------------------------------------------------------------------------+
+// +---------------------------------------------------------------------------------------------------------------------+
+// | CDC_SYNC_STAGES      | Integer            | Range: 2 - 8. Default value = 2.                                        |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Specifies the number of synchronization stages on the CDC path.                                                     |
+// | Applicable only if CLOCKING_MODE = "independent_clock"                                                              |
+localparam integer LP_CDC_SYNC_STAGES = C_SYNCHRONIZER_STAGE;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | CLOCKING_MODE        | String             | Allowed values: common_clock, independent_clock. Default value = common_clock.|
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Designate whether AXI Stream FIFO is clocked with a common clock or with independent clocks-                        |
+// |                                                                                                                     |
+// |  "common_clock"- Common clocking; clock both write and read domain s_aclk                                           |
+// |   "independent_clock"- Independent clocking; clock write domain with s_aclk and read domain with m_aclk             |
+localparam LP_CLOCKING_MODE = C_IS_ACLK_ASYNC ? "independent_clock" : "common_clock"; 
+// +---------------------------------------------------------------------------------------------------------------------+
+// | ECC_MODE             | String             | Allowed values: no_ecc, en_ecc. Default value = no_ecc.                 |
+// |---------------------------------------------------------------------------------------------------------------------|
+// |                                                                                                                     |
+// |  "no_ecc" - Disables ECC                                                                                            |
+// |   "en_ecc" - Enables both ECC Encoder and Decoder                                                                   |
+localparam LP_ECC_MODE = C_ECC_MODE ? "en_ecc" : "no_ecc";
+// +---------------------------------------------------------------------------------------------------------------------+
+// | FIFO_DEPTH           | Integer            | Range: 16 - 4194304. Default value = 2048.                              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Defines the AXI Stream FIFO Write Depth, must be power of two                                                       |
+// TODO: GUI Range
+localparam integer LP_FIFO_DEPTH = C_FIFO_DEPTH;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | FIFO_MEMORY_TYPE     | String             | Allowed values: auto, block, distributed. Default value = auto.         |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Designate the fifo memory primitive (resource type) to use-                                                         |
+// |                                                                                                                     |
+// |  "auto"- Allow Vivado Synthesis to choose                                                                           |
+// |   "block"- Block RAM FIFO                                                                                           |
+// |   "distributed"- Distributed RAM FIFO                                                                               |
+// |   "ultra"- URAM FIFO                                                                                                |
+// TODO: new option?
+localparam LP_FIFO_MEMORY_TYPE = C_FIFO_MEMORY_TYPE;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | PACKET_FIFO          | String             | Allowed values: false, true. Default value = false.                     |
+// |---------------------------------------------------------------------------------------------------------------------|
+// |                                                                                                                     |
+// |  "true"- Enables Packet FIFO mode                                                                                   |
+// |   "false"- Disables Packet FIFO mode                                                                                |
+localparam LP_PACKET_FIFO = C_FIFO_MODE == 2 ? "true" : "false";
+// +---------------------------------------------------------------------------------------------------------------------+
+// | PROG_EMPTY_THRESH    | Integer            | Range: 5 - 4194301. Default value = 10.                                 |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted.                    |
+// |                                                                                                                     |
+// |  Min_Value = 5                                                                                                      |
+// |   Max_Value = FIFO_WRITE_DEPTH - 5                                                                                  |
+// |                                                                                                                     |
+// | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is      |
+// | changed, ensure the threshold value is within the valid range though the programmable flags are not used.           |
+localparam integer LP_PROG_EMPTY_THRESH = C_PROG_EMPTY_THRESH;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | PROG_FULL_THRESH     | Integer            | Range: 5 - 4194301. Default value = 10.                                 |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted.                    |
+// |                                                                                                                     |
+// |  Min_Value = 5 + CDC_SYNC_STAGES                                                                                    |
+// |   Max_Value = FIFO_WRITE_DEPTH - 5                                                                                  |
+// |                                                                                                                     |
+// | NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is      |
+// | changed, ensure the threshold value is within the valid range though the programmable flags are not used.           |
+localparam integer LP_PROG_FULL_THRESH = C_PROG_FULL_THRESH;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | RD_DATA_COUNT_WIDTH  | Integer            | Range: 1 - 23. Default value = 1.                                       |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Specifies the width of rd_data_count_axis                                                                           |
+localparam integer LP_RD_DATA_COUNT_WIDTH = $clog2(C_FIFO_DEPTH+1);
+// +---------------------------------------------------------------------------------------------------------------------+
+// | RELATED_CLOCKS       | Integer            | Range: 0 - 1. Default value = 0.                                        |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Specifies if the s_aclk and m_aclk are related having the same source but different clock ratios                    |
+// | Applicable only if CLOCKING_MODE = "independent_clock"                                                              |
+// TODO: Add Support?
+localparam integer LP_RELATED_CLOCKS   = 0;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | TDATA_WIDTH          | Integer            | Range: 8 - 2048. Default value = 32.                                    |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Defines the width of the TDATA port, s_axis_tdata and m_axis_tdata                                                  |
+localparam integer LP_TDATA_WIDTH = C_AXIS_TDATA_WIDTH;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | TDEST_WIDTH          | Integer            | Range: 1 - 32. Default value = 1.                                       |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Defines the width of the TDEST port, s_axis_tdest and m_axis_tdest                                                  |
+localparam integer LP_TDEST_WIDTH = C_AXIS_TDEST_WIDTH;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | TID_WIDTH            | Integer            | Range: 1 - 32. Default value = 1.                                       |
+localparam integer LP_TID_WIDTH = C_AXIS_TID_WIDTH;
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Defines the width of the ID port, s_axis_tid and m_axis_tid                                                         |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | TUSER_WIDTH          | Integer            | Range: 1 - 4086. Default value = 1.                                     |
+localparam integer LP_TUSER_WIDTH = C_AXIS_TUSER_WIDTH;
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Defines the width of the TUSER port, s_axis_tuser and m_axis_tuser                                                  |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | USE_ADV_FEATURES     | String             | Default value = 1000.                                                   |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Enables almost_empty_axis, rd_data_count_axis, prog_empty_axis, almost_full_axis, wr_data_count_axis,               |
+// | prog_full_axis sideband signals.                                                                                    |
+// |                                                                                                                     |
+// |  Setting USE_ADV_FEATURES[1]  to 1 enables prog_full flag;    Default value of this bit is 0                        |
+// |   Setting USE_ADV_FEATURES[2]  to 1 enables wr_data_count;     Default value of this bit is 0                       |
+// |   Setting USE_ADV_FEATURES[3]  to 1 enables almost_full flag;  Default value of this bit is 0                       |
+// |   Setting USE_ADV_FEATURES[9]  to 1 enables prog_empty flag;   Default value of this bit is 0                       |
+// |   Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count;     Default value of this bit is 0                       |
+// |   Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0                       |
+// |                                                                                                                     |
+// | CAUTION: DO NOT change the default value of USE_ADV_FEATURES[12].                                                   |
+localparam LP_USE_ADV_FEATURES = C_USE_ADV_FEATURES;
+// +---------------------------------------------------------------------------------------------------------------------+
+// | WR_DATA_COUNT_WIDTH  | Integer            | Range: 1 - 23. Default value = 1.                                       |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Specifies the width of wr_data_count_axis                                                                           |
+// +---------------------------------------------------------------------------------------------------------------------+
+localparam integer LP_WR_DATA_COUNT_WIDTH = $clog2(C_FIFO_DEPTH+1);
+
+// Packet mode only valid if tlast is enabled.  Force to 0 if no TLAST
+// present.
+localparam integer LP_S_ACLKEN_CAN_TOGGLE = (C_ACLKEN_CONV_MODE == 1) || (C_ACLKEN_CONV_MODE == 3);
+localparam integer LP_M_ACLKEN_CAN_TOGGLE = (C_ACLKEN_CONV_MODE == 2) || (C_ACLKEN_CONV_MODE == 3);
+
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+wire                            d1_tvalid;
+wire                            d1_tready;
+wire [C_AXIS_TDATA_WIDTH-1:0]   d1_tdata;
+wire [C_AXIS_TDATA_WIDTH/8-1:0] d1_tstrb;
+wire [C_AXIS_TDATA_WIDTH/8-1:0] d1_tkeep;
+wire                            d1_tlast;
+wire [C_AXIS_TID_WIDTH-1:0]     d1_tid  ;
+wire [C_AXIS_TDEST_WIDTH-1:0]   d1_tdest;
+wire [C_AXIS_TUSER_WIDTH-1:0]   d1_tuser;
+
+wire                            d2_tvalid;
+wire                            d2_tready;
+wire [C_AXIS_TDATA_WIDTH-1:0]   d2_tdata;
+wire [C_AXIS_TDATA_WIDTH/8-1:0] d2_tstrb;
+wire [C_AXIS_TDATA_WIDTH/8-1:0] d2_tkeep;
+wire                            d2_tlast;
+wire [C_AXIS_TID_WIDTH-1:0]     d2_tid  ;
+wire [C_AXIS_TDEST_WIDTH-1:0]   d2_tdest;
+wire [C_AXIS_TUSER_WIDTH-1:0]   d2_tuser;
+wire                            m_aclk = C_IS_ACLK_ASYNC ? m_axis_aclk : s_axis_aclk;
+wire                            m_aresetn;
+wire [LP_WR_DATA_COUNT_WIDTH-1:0] wr_data_count;
+wire [LP_RD_DATA_COUNT_WIDTH-1:0] rd_data_count;
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+generate
+  if (C_IS_ACLK_ASYNC == 1 && LP_M_ACLKEN_CAN_TOGGLE) begin : gen_async_clock_and_reset
+
+    reg s_aresetn_r = 1'b1;
+
+    xpm_cdc_sync_rst #(
+      .DEST_SYNC_FF    ( C_SYNCHRONIZER_STAGE ) 
+    )
+    inst_xpm_cdc_sync_rst (
+      .src_rst  ( s_aresetn_r ) ,
+      .dest_rst ( m_aresetn   ) ,
+      .dest_clk ( m_axis_aclk ) 
+    );
+
+    always @(posedge s_axis_aclk) begin 
+      s_aresetn_r <= s_axis_aresetn;
+    end
+
+  end else begin : gen_no_async_clock_and_reset
+    assign m_aresetn          = s_axis_aresetn;
+  end
+
+  if (C_FIFO_MODE > 0) begin : gen_fifo
+
+   axis_infrastructure_v1_1_0_util_aclken_converter_wrapper #(
+     .C_TDATA_WIDTH         ( C_AXIS_TDATA_WIDTH     ) ,
+     .C_TID_WIDTH           ( C_AXIS_TID_WIDTH       ) ,
+     .C_TDEST_WIDTH         ( C_AXIS_TDEST_WIDTH     ) ,
+     .C_TUSER_WIDTH         ( C_AXIS_TUSER_WIDTH     ) ,
+     .C_S_ACLKEN_CAN_TOGGLE ( LP_S_ACLKEN_CAN_TOGGLE ) ,
+     .C_M_ACLKEN_CAN_TOGGLE ( 0                      )
+   )
+   s_util_aclken_converter_wrapper_0 (
+     .ACLK     ( s_axis_aclk    ) ,
+     .ARESETN  ( s_axis_aresetn ) ,
+     .S_ACLKEN ( s_axis_aclken  ) ,
+     .S_VALID  ( s_axis_tvalid  ) ,
+     .S_READY  ( s_axis_tready  ) ,
+     .S_TDATA  ( s_axis_tdata   ) ,
+     .S_TSTRB  ( s_axis_tstrb   ) ,
+     .S_TKEEP  ( s_axis_tkeep   ) ,
+     .S_TLAST  ( s_axis_tlast   ) ,
+     .S_TID    ( s_axis_tid     ) ,
+     .S_TDEST  ( s_axis_tdest   ) ,
+     .S_TUSER  ( s_axis_tuser   ) ,
+     .M_ACLKEN ( 1'b1           ) ,
+     .M_VALID  ( d1_tvalid      ) ,
+     .M_READY  ( d1_tready      ) ,
+     .M_TDATA  ( d1_tdata       ) ,
+     .M_TSTRB  ( d1_tstrb       ) ,
+     .M_TKEEP  ( d1_tkeep       ) ,
+     .M_TLAST  ( d1_tlast       ) ,
+     .M_TID    ( d1_tid         ) ,
+     .M_TDEST  ( d1_tdest       ) ,
+     .M_TUSER  ( d1_tuser       )
+   );
+
+
+// XPM_FIFO instantiation template for AXI Stream FIFO configurations (2018.3)
+// Refer to the targeted device family architecture libraries guide for XPM_FIFO documentation
+// =======================================================================================================================
+// Port usage table, organized as follows:
+// +---------------------------------------------------------------------------------------------------------------------+
+// | Port name      | Direction | Size, in bits                         | Domain  | Sense       | Handling if unused     |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Description                                                                                                         |
+// +---------------------------------------------------------------------------------------------------------------------+
+// +---------------------------------------------------------------------------------------------------------------------+
+// | almost_empty_axis| Output    | 1                                     | m_aclk  | Active-high | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to|
+// | empty.                                                                                                              |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | almost_full_axis| Output    | 1                                     | s_aclk  | Active-high | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.|
+// +---------------------------------------------------------------------------------------------------------------------+
+// | dbiterr_axis   | Output    | 1                                     | m_aclk  | Active-high | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Double Bit Error- Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.|
+// +---------------------------------------------------------------------------------------------------------------------+
+// | injectdbiterr_axis| Input     | 1                                     | s_aclk  | Active-high | Tie to 1'b0            |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Double Bit Error Injection- Injects a double bit error if the ECC feature is used.                                  |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | injectsbiterr_axis| Input     | 1                                     | s_aclk  | Active-high | Tie to 1'b0            |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Single Bit Error Injection- Injects a single bit error if the ECC feature is used.                                  |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_aclk         | Input     | 1                                     | NA      | Rising edge | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Master Interface Clock: All signals on master interface are sampled on the rising edge of this clock.               |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tdata   | Output    | TDATA_WIDTH                           | m_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TDATA: The primary payload that is used to provide the data that is passing across the interface. The width         |
+// | of the data payload is an integer number of bytes.                                                                  |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tdest   | Output    | TDEST_WIDTH                           | m_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TDEST: Provides routing information for the data stream.                                                            |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tid     | Output    | TID_WIDTH                             | m_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TID: The data stream identifier that indicates different streams of data.                                           |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tkeep   | Output    | TDATA_WIDTH                           | m_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed           |
+// | as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes           |
+// | and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte         |
+// | on DATA, and bit 7 corresponds to the most significant byte. For example:                                           |
+// |                                                                                                                     |
+// |  KEEP[0] = 1b, DATA[7:0] is not a NULL byte                                                                         |
+// |   KEEP[7] = 0b, DATA[63:56] is a NULL byte                                                                          |
+// | .                                                                                                                   |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tlast   | Output    | 1                                     | m_aclk  | Active-high | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TLAST: Indicates the boundary of a packet.                                                                          |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tready  | Input     | 1                                     | m_aclk  | Active-high | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TREADY: Indicates that the slave can accept a transfer in the current cycle.                                        |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tstrb   | Output    | TDATA_WIDTH                           | m_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed           |
+// | as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on            |
+// | DATA, and bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant    |
+// | byte. For example:                                                                                                  |
+// |                                                                                                                     |
+// |  STROBE[0] = 1b, DATA[7:0] is valid                                                                                 |
+// |   STROBE[7] = 0b, DATA[63:56] is not valid                                                                          |
+// | .                                                                                                                   |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tuser   | Output    | TUSER_WIDTH                           | m_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TUSER: The user-defined sideband information that can be transmitted alongside the data stream.                     |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | m_axis_tvalid  | Output    | 1                                     | m_aclk  | Active-high | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TVALID: Indicates that the master is driving a valid transfer.                                                      |
+// |                                                                                                                     |
+// |  A transfer takes place when both TVALID and TREADY are asserted                                                    |
+// | .                                                                                                                   |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | prog_empty_axis| Output    | 1                                     | m_aclk  | Active-high | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Programmable Empty- This signal is asserted when the number of words in the FIFO is less than or equal              |
+// | to the programmable empty threshold value.                                                                          |
+// | It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value.              |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | prog_full_axis | Output    | 1                                     | s_aclk  | Active-high | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal            |
+// | to the programmable full threshold value.                                                                           |
+// | It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value.          |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | rd_data_count_axis| Output    | RD_DATA_COUNT_WIDTH                   | m_aclk  | NA          | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Read Data Count- This bus indicates the number of words available for reading in the FIFO.                          |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_aclk         | Input     | 1                                     | NA      | Rising edge | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Slave Interface Clock: All signals on slave interface are sampled on the rising edge of this clock.                 |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_aresetn      | Input     | 1                                     | NA      | Active-low  | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Active low asynchronous reset.                                                                                      |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tdata   | Input     | TDATA_WIDTH                           | s_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TDATA: The primary payload that is used to provide the data that is passing across the interface. The width         |
+// | of the data payload is an integer number of bytes.                                                                  |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tdest   | Input     | TDEST_WIDTH                           | s_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TDEST: Provides routing information for the data stream.                                                            |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tid     | Input     | TID_WIDTH                             | s_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TID: The data stream identifier that indicates different streams of data.                                           |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tkeep   | Input     | TDATA_WIDTH                           | s_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed           |
+// | as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes           |
+// | and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte         |
+// | on DATA, and bit 7 corresponds to the most significant byte. For example:                                           |
+// |                                                                                                                     |
+// |  KEEP[0] = 1b, DATA[7:0] is not a NULL byte                                                                         |
+// |   KEEP[7] = 0b, DATA[63:56] is a NULL byte                                                                          |
+// | .                                                                                                                   |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tlast   | Input     | 1                                     | s_aclk  | Active-high | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TLAST: Indicates the boundary of a packet.                                                                          |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tready  | Output    | 1                                     | s_aclk  | Active-high | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TREADY: Indicates that the slave can accept a transfer in the current cycle.                                        |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tstrb   | Input     | TDATA_WIDTH                           | s_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed           |
+// | as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on            |
+// | DATA, and bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant    |
+// | byte. For example:                                                                                                  |
+// |                                                                                                                     |
+// |  STROBE[0] = 1b, DATA[7:0] is valid                                                                                 |
+// |   STROBE[7] = 0b, DATA[63:56] is not valid                                                                          |
+// | .                                                                                                                   |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tuser   | Input     | TUSER_WIDTH                           | s_aclk  | NA          | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TUSER: The user-defined sideband information that can be transmitted alongside the data stream.                     |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | s_axis_tvalid  | Input     | 1                                     | s_aclk  | Active-high | Required               |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | TVALID: Indicates that the master is driving a valid transfer.                                                      |
+// |                                                                                                                     |
+// |  A transfer takes place when both TVALID and TREADY are asserted                                                    |
+// | .                                                                                                                   |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | sbiterr_axis   | Output    | 1                                     | m_aclk  | Active-high | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Single Bit Error- Indicates that the ECC decoder detected and fixed a single-bit error.                             |
+// +---------------------------------------------------------------------------------------------------------------------+
+// | wr_data_count_axis| Output    | WR_DATA_COUNT_WIDTH                   | s_aclk  | NA          | DoNotCare              |
+// |---------------------------------------------------------------------------------------------------------------------|
+// | Write Data Count: This bus indicates the number of words written into the FIFO.                                     |
+// +---------------------------------------------------------------------------------------------------------------------+
+  // xpm_fifo_axis: AXI Stream FIFO
+  // Xilinx Parameterized Macro, version 2018.3
+
+  xpm_fifo_axis #(
+     .CDC_SYNC_STAGES     ( LP_CDC_SYNC_STAGES     ) , // DECIMAL
+     .CLOCKING_MODE       ( LP_CLOCKING_MODE       ) , // String
+     .ECC_MODE            ( LP_ECC_MODE            ) , // String
+     .FIFO_DEPTH          ( LP_FIFO_DEPTH          ) , // DECIMAL
+     .FIFO_MEMORY_TYPE    ( LP_FIFO_MEMORY_TYPE    ) , // String
+     .PACKET_FIFO         ( LP_PACKET_FIFO         ) , // String
+     .PROG_EMPTY_THRESH   ( LP_PROG_EMPTY_THRESH   ) , // DECIMAL
+     .PROG_FULL_THRESH    ( LP_PROG_FULL_THRESH    ) , // DECIMAL
+     .RD_DATA_COUNT_WIDTH ( LP_RD_DATA_COUNT_WIDTH ) , // DECIMAL
+     .RELATED_CLOCKS      ( LP_RELATED_CLOCKS      ) , // DECIMAL
+     .TDATA_WIDTH         ( LP_TDATA_WIDTH         ) , // DECIMAL
+     .TDEST_WIDTH         ( LP_TDEST_WIDTH         ) , // DECIMAL
+     .TID_WIDTH           ( LP_TID_WIDTH           ) , // DECIMAL
+     .TUSER_WIDTH         ( LP_TUSER_WIDTH         ) , // DECIMAL
+     .USE_ADV_FEATURES    ( LP_USE_ADV_FEATURES    ) , // String
+     .WR_DATA_COUNT_WIDTH ( LP_WR_DATA_COUNT_WIDTH )   // DECIMAL
+  )
+  xpm_fifo_axis_inst (
+    // s_axis_aclk domain
+     .s_aclk               ( s_axis_aclk    ) ,
+     .s_aresetn            ( s_axis_aresetn ) ,
+     .s_axis_tvalid        ( d1_tvalid      ) ,
+     .s_axis_tready        ( d1_tready      ) ,
+     // These signals have explicit tie-offs to 0 to allow synthesis tool to optimize unused bits in FIFO.
+     .s_axis_tdata         ( C_AXIS_SIGNAL_SET[1] ? d1_tdata : {LP_TDATA_WIDTH{1'b0}}   ) ,
+     .s_axis_tstrb         ( C_AXIS_SIGNAL_SET[2] ? d1_tstrb : {LP_TDATA_WIDTH/8{1'b0}} ) ,
+     .s_axis_tkeep         ( C_AXIS_SIGNAL_SET[3] ? d1_tkeep : {LP_TDATA_WIDTH/8{1'b0}} ) ,
+     .s_axis_tlast         ( C_AXIS_SIGNAL_SET[4] ? d1_tlast : 1'b0                     ) ,
+     .s_axis_tid           ( C_AXIS_SIGNAL_SET[5] ? d1_tid   : {LP_TID_WIDTH{1'b0}}     ) ,
+     .s_axis_tdest         ( C_AXIS_SIGNAL_SET[6] ? d1_tdest : {LP_TDEST_WIDTH{1'b0}}   ) ,
+     .s_axis_tuser         ( C_AXIS_SIGNAL_SET[7] ? d1_tuser : {LP_TUSER_WIDTH{1'b0}}   ) ,
+     .almost_full_axis     ( almost_full    ) ,
+     .prog_full_axis       ( prog_full      ) ,
+     .wr_data_count_axis   ( wr_data_count  ) ,
+     .injectdbiterr_axis   ( injectdbiterr  ) ,
+     .injectsbiterr_axis   ( injectsbiterr  ) ,
+     // m_axis_aclk domain
+     .m_aclk               ( m_aclk         ) ,
+     .m_axis_tvalid        ( d2_tvalid      ) ,
+     .m_axis_tready        ( d2_tready      ) ,
+     .m_axis_tdata         ( d2_tdata       ) ,
+     .m_axis_tstrb         ( d2_tstrb       ) ,
+     .m_axis_tkeep         ( d2_tkeep       ) ,
+     .m_axis_tlast         ( d2_tlast       ) ,
+     .m_axis_tid           ( d2_tid         ) ,
+     .m_axis_tdest         ( d2_tdest       ) ,
+     .m_axis_tuser         ( d2_tuser       ) ,
+     .almost_empty_axis    ( almost_empty   ) ,
+     .prog_empty_axis      ( prog_empty     ) ,
+     .rd_data_count_axis   ( rd_data_count  ) ,
+     .sbiterr_axis         ( sbiterr        ) ,
+     .dbiterr_axis         ( dbiterr        ) 
+  );
+
+  assign axis_wr_data_count = wr_data_count | 32'h0;
+  assign axis_rd_data_count = rd_data_count | 32'h0;
+
+  // End of xpm_fifo_axis_inst instantiation
+   axis_infrastructure_v1_1_0_util_aclken_converter_wrapper #(
+     .C_TDATA_WIDTH         ( C_AXIS_TDATA_WIDTH     ) ,
+     .C_TID_WIDTH           ( C_AXIS_TID_WIDTH       ) ,
+     .C_TDEST_WIDTH         ( C_AXIS_TDEST_WIDTH     ) ,
+     .C_TUSER_WIDTH         ( C_AXIS_TUSER_WIDTH     ) ,
+     .C_S_ACLKEN_CAN_TOGGLE (                      0 ) ,
+     .C_M_ACLKEN_CAN_TOGGLE ( LP_M_ACLKEN_CAN_TOGGLE )
+   )
+   m_util_aclken_converter_wrapper_0 (
+     .ACLK     ( m_aclk        ) ,
+     .ARESETN  ( m_aresetn     ) ,
+     .S_ACLKEN ( 1'b1          ) ,
+     .S_VALID  ( d2_tvalid     ) ,
+     .S_READY  ( d2_tready     ) ,
+     // Restore default tieoffs here if necessary
+     .S_TDATA  ( C_AXIS_SIGNAL_SET[1] ? d2_tdata : {LP_TDATA_WIDTH{1'b0}}   ) ,
+     .S_TSTRB  ( C_AXIS_SIGNAL_SET[2] ? d2_tstrb : {LP_TDATA_WIDTH/8{1'b1}} ) ,
+     .S_TKEEP  ( C_AXIS_SIGNAL_SET[3] ? d2_tkeep : {LP_TDATA_WIDTH/8{1'b1}} ) ,
+     .S_TLAST  ( C_AXIS_SIGNAL_SET[4] ? d2_tlast : 1'b1                     ) ,
+     .S_TID    ( C_AXIS_SIGNAL_SET[5] ? d2_tid   : {LP_TID_WIDTH{1'b0}}     ) ,
+     .S_TDEST  ( C_AXIS_SIGNAL_SET[6] ? d2_tdest : {LP_TDEST_WIDTH{1'b0}}   ) ,
+     .S_TUSER  ( C_AXIS_SIGNAL_SET[7] ? d2_tuser : {LP_TUSER_WIDTH{1'b0}}   ) ,
+     .M_ACLKEN ( m_axis_aclken ) ,
+     .M_VALID  ( m_axis_tvalid ) ,
+     .M_READY  ( (C_AXIS_SIGNAL_SET[0] == 0) ? 1'b1 : m_axis_tready  ) ,
+     .M_TDATA  ( m_axis_tdata  ) ,
+     .M_TSTRB  ( m_axis_tstrb  ) ,
+     .M_TKEEP  ( m_axis_tkeep  ) ,
+     .M_TLAST  ( m_axis_tlast  ) ,
+     .M_TID    ( m_axis_tid    ) ,
+     .M_TDEST  ( m_axis_tdest  ) ,
+     .M_TUSER  ( m_axis_tuser  ) 
+   );
+  end
+  else begin : gen_fifo_passthru
+   assign s_axis_tready   = (C_AXIS_SIGNAL_SET[0] == 0) ? 1'b1 : m_axis_tready ;
+   assign m_axis_tvalid   = s_axis_tvalid ;
+   assign m_axis_tdata    = s_axis_tdata  ;
+   assign m_axis_tstrb    = s_axis_tstrb  ;
+   assign m_axis_tkeep    = s_axis_tkeep  ;
+   assign m_axis_tlast    = s_axis_tlast  ;
+   assign m_axis_tid      = s_axis_tid    ;
+   assign m_axis_tdest    = s_axis_tdest  ;
+   assign m_axis_tuser    = s_axis_tuser  ;
+   assign almost_full     = 1'b0;
+   assign prog_full       = 1'b0;
+   assign almost_empty     = 1'b0;
+   assign prog_empty       = 1'b0;
+   assign axis_wr_data_count = 32'b0;
+   assign axis_rd_data_count = 32'b0;
+   assign sbiterr = 1'b0;
+   assign dbiterr = 1'b0;
+  end
+endgenerate
+
+endmodule // axis_data_fifo
+
+`default_nettype wire
+
+

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh

@@ -0,0 +1,138 @@
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXI Infrastructure Modules
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+//
+// Tasks:
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+localparam G_AXI_AWADDR_INDEX   = 0;
+localparam G_AXI_AWADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_AWPROT_INDEX   = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
+localparam G_AXI_AWPROT_WIDTH   = 3;
+localparam G_AXI_AWSIZE_INDEX   = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
+localparam G_AXI_AWSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_AWBURST_INDEX  = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
+localparam G_AXI_AWBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_AWCACHE_INDEX  = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
+localparam G_AXI_AWCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWLEN_INDEX    = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
+localparam G_AXI_AWLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_AWLOCK_INDEX   = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
+localparam G_AXI_AWLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_AWID_INDEX     = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
+localparam G_AXI_AWID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_AWQOS_INDEX    = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
+localparam G_AXI_AWQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
+localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_AWUSER_INDEX   = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
+localparam G_AXI_AWUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
+localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
+localparam G_AXI_ARADDR_INDEX   = 0;
+localparam G_AXI_ARADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_ARPROT_INDEX   = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
+localparam G_AXI_ARPROT_WIDTH   = 3;
+localparam G_AXI_ARSIZE_INDEX   = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
+localparam G_AXI_ARSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_ARBURST_INDEX  = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
+localparam G_AXI_ARBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_ARCACHE_INDEX  = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
+localparam G_AXI_ARCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARLEN_INDEX    = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
+localparam G_AXI_ARLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_ARLOCK_INDEX   = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
+localparam G_AXI_ARLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_ARID_INDEX     = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
+localparam G_AXI_ARID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_ARQOS_INDEX    = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
+localparam G_AXI_ARQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
+localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_ARUSER_INDEX   = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
+localparam G_AXI_ARUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
+localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
+// Write channel widths
+localparam G_AXI_WDATA_INDEX    = 0;
+localparam G_AXI_WDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_WSTRB_INDEX    = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
+localparam G_AXI_WSTRB_WIDTH    = C_AXI_DATA_WIDTH / 8;
+localparam G_AXI_WLAST_INDEX    = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
+localparam G_AXI_WLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_WID_INDEX      = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
+localparam G_AXI_WID_WIDTH      = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_WUSER_INDEX    = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
+localparam G_AXI_WUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
+localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
+// Write Response channel Widths
+localparam G_AXI_BRESP_INDEX    = 0;
+localparam G_AXI_BRESP_WIDTH    = 2;
+localparam G_AXI_BID_INDEX      = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
+localparam G_AXI_BID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_BUSER_INDEX    = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
+localparam G_AXI_BUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
+localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
+// Read channel widths
+localparam G_AXI_RDATA_INDEX    = 0;
+localparam G_AXI_RDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_RRESP_INDEX    = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
+localparam G_AXI_RRESP_WIDTH    = 2;
+localparam G_AXI_RLAST_INDEX    = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
+localparam G_AXI_RLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_RID_INDEX      = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
+localparam G_AXI_RID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_RUSER_INDEX    = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
+localparam G_AXI_RUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
+localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;

projects/datalink_814/dl814_z7/ipi-bds/system_bd/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v

@@ -0,0 +1,670 @@
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axis to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_axi2vector #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_awid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_awaddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
+  input  wire [3-1:0]                               s_axi_awsize,
+  input  wire [2-1:0]                               s_axi_awburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
+  input  wire [4-1:0]                               s_axi_awcache,
+  input  wire [3-1:0]                               s_axi_awprot,
+  input  wire [4-1:0]                               s_axi_awregion,
+  input  wire [4-1:0]                               s_axi_awqos,
+  input  wire [C_AXI_AWUSER_WIDTH-1:0]              s_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_wid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                s_axi_wdata,
+  input  wire [C_AXI_DATA_WIDTH/8-1:0]              s_axi_wstrb,
+  input  wire                                       s_axi_wlast,
+  input  wire [C_AXI_WUSER_WIDTH-1:0]               s_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_bid,
+  output wire [2-1:0]                               s_axi_bresp,
+  output wire [C_AXI_BUSER_WIDTH-1:0]               s_axi_buser,
+
+   // Slave Interface Read Address Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  s_axi_arid,
+  input  wire [C_AXI_ADDR_WIDTH-1:0]                s_axi_araddr,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
+  input  wire [3-1:0]                               s_axi_arsize,
+  input  wire [2-1:0]                               s_axi_arburst,
+  input  wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
+  input  wire [4-1:0]                               s_axi_arcache,
+  input  wire [3-1:0]                               s_axi_arprot,
+  input  wire [4-1:0]                               s_axi_arregion,
+  input  wire [4-1:0]                               s_axi_arqos,
+  input  wire [C_AXI_ARUSER_WIDTH-1:0]              s_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  s_axi_rid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                s_axi_rdata,
+  output wire [2-1:0]                               s_axi_rresp,
+  output wire                                       s_axi_rlast,
+  output wire [C_AXI_RUSER_WIDTH-1:0]               s_axi_ruser,
+
+  // payloads
+  output wire [C_AWPAYLOAD_WIDTH-1:0]               s_awpayload,
+  output wire [C_WPAYLOAD_WIDTH-1:0]                s_wpayload,
+  input  wire [C_BPAYLOAD_WIDTH-1:0]                s_bpayload,
+  output wire [C_ARPAYLOAD_WIDTH-1:0]               s_arpayload,
+  input  wire [C_RPAYLOAD_WIDTH-1:0]                s_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axi_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
+assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
+
+assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
+assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
+
+assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
+
+assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
+assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
+
+assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
+assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]   = s_axi_awsize;
+    assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
+    assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
+    assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]     = s_axi_awlen;
+    assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]   = s_axi_awlock;
+    assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]       = s_axi_awid;
+    assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]     = s_axi_awqos;
+
+    assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]      = s_axi_wlast;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]        = s_axi_wid;
+    end
+    else begin : gen_no_axi3_wid_packing
+    end
+
+    assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
+
+    assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]   = s_axi_arsize;
+    assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
+    assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
+    assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]     = s_axi_arlen;
+    assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]   = s_axi_arlock;
+    assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]       = s_axi_arid;
+    assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]     = s_axi_arqos;
+
+    assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
+    assign s_axi_rid   = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
+      assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
+    end 
+    else begin : gen_no_region_signals
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
+      assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]    = s_axi_wuser;
+      assign s_axi_buser                                       = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
+      assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
+      assign s_axi_ruser                                       = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
+    end 
+    else begin : gen_no_user_signals
+      assign s_axi_buser = 'b0;
+      assign s_axi_ruser = 'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign s_axi_bid = 'b0;
+    assign s_axi_buser = 'b0;
+
+    assign s_axi_rlast = 1'b1;
+    assign s_axi_rid   = 'b0;
+    assign s_axi_ruser = 'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+// Description: SRL based FIFO for AXIS/AXI Channels.
+//--------------------------------------------------------------------------
+
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_axic_srl_fifo #(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter         C_FAMILY     = "virtex7",
+  parameter integer C_PAYLOAD_WIDTH = 1,
+  parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  input  wire                        aclk,    // Clock
+  input  wire                        aresetn,  // Reset
+  input  wire [C_PAYLOAD_WIDTH-1:0]  s_payload,  // Input data
+  input  wire                        s_valid, // Input data valid
+  output reg                         s_ready, // Input data ready
+  output wire [C_PAYLOAD_WIDTH-1:0]  m_payload,  // Output data
+  output reg                         m_valid, // Output data valid
+  input  wire                        m_ready  // Output data ready
+);
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+// ceiling logb2
+function integer f_clogb2 (input integer size);
+  integer s;
+  begin
+    s = size;
+    s = s - 1;
+    for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
+          s = s >> 1;
+  end
+endfunction // clogb2
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+reg  [LP_LOG_FIFO_DEPTH-1:0]        fifo_index;
+wire [4-1:0]                        fifo_addr;
+wire                                push;
+wire                                pop ;
+reg                                 areset_r1;
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+always @(posedge aclk) begin 
+  areset_r1 <= ~aresetn;
+end
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin
+    fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
+  end
+  else begin
+    fifo_index <= push & ~pop ? fifo_index + 1'b1 :
+                  ~push & pop ? fifo_index - 1'b1 : 
+                  fifo_index;
+  end
+end
+
+assign push = s_valid & s_ready;
+
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    s_ready <= 1'b0;
+  end
+  else begin 
+    s_ready <= areset_r1 ? 1'b1 : 
+               push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
+               ~push & pop ? 1'b1 : 
+               s_ready;
+  end
+end
+
+assign pop = m_valid & m_ready;
+               
+always @(posedge aclk) begin 
+  if (~aresetn) begin 
+    m_valid <= 1'b0;
+  end
+  else begin 
+    m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
+               push & ~pop ? 1'b1 : 
+               m_valid;
+  end
+end
+
+generate 
+  if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
+    assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+    assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
+  end
+  else begin : gen_fifo_addr
+    assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
+  end
+endgenerate
+
+
+generate
+  genvar i;
+  for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
+    SRL16E 
+    u_srl_fifo(
+      .Q   ( m_payload[i] ) ,
+      .A0  ( fifo_addr[0]     ) ,
+      .A1  ( fifo_addr[1]     ) ,
+      .A2  ( fifo_addr[2]     ) ,
+      .A3  ( fifo_addr[3]     ) ,
+      .CE  ( push              ) ,
+      .CLK ( aclk              ) ,
+      .D   ( s_payload[i] ) 
+    );
+  end
+endgenerate
+
+endmodule
+
+`default_nettype wire
+
+
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// axi to vector
+//   A generic module to merge all axi signals into one signal called payload.
+//   This is strictly wires, so no clk, reset, aclken, valid/ready are required.
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+//
+
+`timescale 1ps/1ps
+`default_nettype none
+
+(* DowngradeIPIdentifiedWarnings="yes" *) 
+module axi_infrastructure_v1_1_0_vector2axi #
+(
+///////////////////////////////////////////////////////////////////////////////
+// Parameter Definitions
+///////////////////////////////////////////////////////////////////////////////
+  parameter integer C_AXI_PROTOCOL                = 0,
+  parameter integer C_AXI_ID_WIDTH                = 4,
+  parameter integer C_AXI_ADDR_WIDTH              = 32,
+  parameter integer C_AXI_DATA_WIDTH              = 32,
+  parameter integer C_AXI_SUPPORTS_USER_SIGNALS   = 0,
+  parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
+  parameter integer C_AXI_AWUSER_WIDTH            = 1,
+  parameter integer C_AXI_WUSER_WIDTH             = 1,
+  parameter integer C_AXI_BUSER_WIDTH             = 1,
+  parameter integer C_AXI_ARUSER_WIDTH            = 1,
+  parameter integer C_AXI_RUSER_WIDTH             = 1,
+  parameter integer C_AWPAYLOAD_WIDTH             = 61,
+  parameter integer C_WPAYLOAD_WIDTH              = 73,
+  parameter integer C_BPAYLOAD_WIDTH              = 6,
+  parameter integer C_ARPAYLOAD_WIDTH             = 61,
+  parameter integer C_RPAYLOAD_WIDTH              = 69
+)
+(
+///////////////////////////////////////////////////////////////////////////////
+// Port Declarations
+///////////////////////////////////////////////////////////////////////////////
+  // Slave Interface Write Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_awid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_awaddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
+  output wire [3-1:0]                               m_axi_awsize,
+  output wire [2-1:0]                               m_axi_awburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
+  output wire [4-1:0]                               m_axi_awcache,
+  output wire [3-1:0]                               m_axi_awprot,
+  output wire [4-1:0]                               m_axi_awregion,
+  output wire [4-1:0]                               m_axi_awqos,
+  output wire [C_AXI_AWUSER_WIDTH-1:0]              m_axi_awuser,
+
+  // Slave Interface Write Data Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_wid,
+  output wire [C_AXI_DATA_WIDTH-1:0]                m_axi_wdata,
+  output wire [C_AXI_DATA_WIDTH/8-1:0]              m_axi_wstrb,
+  output wire                                       m_axi_wlast,
+  output wire [C_AXI_WUSER_WIDTH-1:0]               m_axi_wuser,
+
+  // Slave Interface Write Response Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_bid,
+  input  wire [2-1:0]                               m_axi_bresp,
+  input  wire [C_AXI_BUSER_WIDTH-1:0]               m_axi_buser,
+
+   // Slave Interface Read Address Ports
+  output wire [C_AXI_ID_WIDTH-1:0]                  m_axi_arid,
+  output wire [C_AXI_ADDR_WIDTH-1:0]                m_axi_araddr,
+  output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
+  output wire [3-1:0]                               m_axi_arsize,
+  output wire [2-1:0]                               m_axi_arburst,
+  output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
+  output wire [4-1:0]                               m_axi_arcache,
+  output wire [3-1:0]                               m_axi_arprot,
+  output wire [4-1:0]                               m_axi_arregion,
+  output wire [4-1:0]                               m_axi_arqos,
+  output wire [C_AXI_ARUSER_WIDTH-1:0]              m_axi_aruser,
+
+  // Slave Interface Read Data Ports
+  input  wire [C_AXI_ID_WIDTH-1:0]                  m_axi_rid,
+  input  wire [C_AXI_DATA_WIDTH-1:0]                m_axi_rdata,
+  input  wire [2-1:0]                               m_axi_rresp,
+  input  wire                                       m_axi_rlast,
+  input  wire [C_AXI_RUSER_WIDTH-1:0]               m_axi_ruser,
+
+  // payloads
+  input  wire [C_AWPAYLOAD_WIDTH-1:0]               m_awpayload,
+  input  wire [C_WPAYLOAD_WIDTH-1:0]                m_wpayload,
+  output wire [C_BPAYLOAD_WIDTH-1:0]                m_bpayload,
+  input  wire [C_ARPAYLOAD_WIDTH-1:0]               m_arpayload,
+  output wire [C_RPAYLOAD_WIDTH-1:0]                m_rpayload
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+////////////////////////////////////////////////////////////////////////////////
+`include "axi_infrastructure_v1_1_0.vh"
+
+////////////////////////////////////////////////////////////////////////////////
+// Local parameters
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Wires/Reg declarations
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// BEGIN RTL
+////////////////////////////////////////////////////////////////////////////////
+
+// AXI4, AXI4LITE, AXI3 packing
+assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
+assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
+
+assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
+assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
+
+assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
+
+assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
+assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
+
+assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
+assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
+
+generate
+  if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
+    assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH]  ;
+    assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
+    assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
+    assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH]    ;
+    assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH]  ;
+    assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH]      ;
+    assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH]    ;
+
+    assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH]     ;
+    if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
+      assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH]       ;
+    end
+    else begin : gen_no_axi3_wid_packing
+      assign m_axi_wid = 1'b0;
+    end
+
+    assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
+
+    assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH]  ;
+    assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
+    assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
+    assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH]    ;
+    assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH]  ;
+    assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH]      ;
+    assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH]    ;
+
+    assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
+    assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid  ;
+
+    if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
+      assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
+      assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
+    end 
+    else begin : gen_no_region_signals
+      assign m_axi_awregion = 'b0;
+      assign m_axi_arregion = 'b0;
+    end
+    if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
+      assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
+      assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH]   ;
+      assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser                                      ;
+      assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
+      assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser                                      ;
+    end 
+    else begin : gen_no_user_signals
+      assign m_axi_awuser = 'b0;
+      assign m_axi_wuser = 'b0;
+      assign m_axi_aruser = 'b0;
+    end
+  end
+  else begin : gen_axi4lite_packing
+    assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
+    assign m_axi_awburst = 'b0;
+    assign m_axi_awcache = 'b0;
+    assign m_axi_awlen = 'b0;
+    assign m_axi_awlock = 'b0;
+    assign m_axi_awid = 'b0;
+    assign m_axi_awqos = 'b0;
+
+    assign m_axi_wlast = 1'b1;
+    assign m_axi_wid = 'b0;
+
+
+    assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
+    assign m_axi_arburst = 'b0;
+    assign m_axi_arcache = 'b0;
+    assign m_axi_arlen = 'b0;
+    assign m_axi_arlock = 'b0;
+    assign m_axi_arid = 'b0;
+    assign m_axi_arqos = 'b0;
+
+    assign m_axi_awregion = 'b0;
+    assign m_axi_arregion = 'b0;
+
+    assign m_axi_awuser = 'b0;
+    assign m_axi_wuser = 'b0;
+    assign m_axi_aruser = 'b0;
+  end
+endgenerate
+endmodule 
+
+`default_nettype wire
+
+