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Update gitignore, add dl814_z7 project
gitignore structure is updated to work with single and multi project situation under a single project directory
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2022/08/27 15:30:06
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// Design Name:
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// Module Name: glink_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module glink_top(
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// glink gt reference clock
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input glink_refclk_p , // generated by oscillator, 125mhz
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input glink_refclk_n ,
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// glink pk clock
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input glink_logic_clk , // generated by oscillator, 25mhz
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input pl_rst ,
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input rx_datain_p_ch_a ,
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input rx_datain_n_ch_a ,
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input rx_datain_p_ch_b ,
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input rx_datain_n_ch_b ,
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output tx_dataout_p_ch_a ,
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output tx_dataout_n_ch_a ,
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output tx_dataout_p_ch_b ,
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output tx_dataout_n_ch_b ,
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//glink_ctrl
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output [31:0] glink_gpio_i_0 ,
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output [31:0] glink_gpio_i_1 ,
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input [31:0] glink_gpio_o_0 ,
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input [31:0] glink_gpio_o_1 ,
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//DMA_send_fifo
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input [15:0] glink_tx_fifo_tdata ,
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input glink_tx_fifo_tlast ,
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output glink_tx_fifo_tready,
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input glink_tx_fifo_tvalid,
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//DMA_recv_fifo
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output [15:0] glink_rx_fifo_tdata ,
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output glink_rx_fifo_tlast ,
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input glink_rx_fifo_tready,
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output glink_rx_fifo_tvalid,
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output glink_ip_clk
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);
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wire glink_pll_inclk;
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IBUFDS_GTE2 IBUFDS_GTE2_CLK1(
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.I (glink_refclk_p ),
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.IB (glink_refclk_n ),
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.CEB (1'b0 ),
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.O (glink_pll_inclk),
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.ODIV2 ( )
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);
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wire glink_rst;
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glink_rst_create u_glink_rst_create(
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.glink_logic_clk(glink_logic_clk ),
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.i_reset_p (pl_rst ),
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.reset_p (glink_rst )
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);
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wire [11:0] i_node_id ;
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wire i_node_id_par ;
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wire [15:0] i_smartnc_2nd_cfg ;
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wire [15:0] i_smartnc_3rd_cfg ;
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wire [15:0] i_smartnt_cfg ;
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wire smartnc_trans_trig ;
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wire smartnc_trans_reset ;
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wire smartnc_trans_idle ;
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wire smartnc_trans_err ;
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wire [15:0] smartnc_intf_tx_fifo_wdata ;
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wire smartnc_intf_tx_fifo_wr_en ;
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wire smartnc_intf_tx_fifo_afull ;
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wire smartnc_intf_rx_fifo_empty ;
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wire [15:0] smartnc_intf_rx_fifo_rdata ;
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wire smartnc_intf_rx_fifo_rd_en ;
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wire smartnt_intf_cmd_proc_req ;
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wire smartnt_intf_cmd_proc_ack ;
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wire smartnt_intf_rx_fifo_empty ;
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wire [15:0] smartnt_intf_rx_fifo_rdata ;
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wire smartnt_intf_rx_fifo_rd_en ;
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wire [15:0] smartnt_intf_tx_fifo_wdata ;
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wire smartnt_intf_tx_fifo_wr_en ;
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wire glink_ip_rst_n ;
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ebey_glink_top_wrapper_k7_smartncnt u_ebey_glink_top_wrapper_k7_smartncnt
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( .clk_reconfig (glink_logic_clk ),
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.pll_inclk (glink_pll_inclk ),
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.i_reset_p (glink_rst ),
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.i_node_id (i_node_id ),//�ڵ� ID12'h003
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.i_node_id_par (i_node_id_par ),//��żУ�� 1'b1
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.i_smartnc_2nd_cfg (i_smartnc_2nd_cfg ),//SMARTNC���䳬ʱΪ128us 16'h0003
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.i_smartnc_3rd_cfg (i_smartnc_3rd_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h0400
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.i_smartnt_cfg (i_smartnt_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h4000
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.i_select_n (1'b1 ),
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.i_strbd_n (1'b1 ),
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.i_mem_access (1'b0 ),
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.i_rd_access (1'b0 ),
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.o_ready_n ( ),
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.i_cpu_addr (18'b0 ),
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.o_cpu_rdata ( ),
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.o_cpu_rdata_oe ( ),
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.i_cpu_wdata (16'b0 ),
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.smartnc_trans_trig (smartnc_trans_trig ),
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.smartnc_trans_reset (smartnc_trans_reset ),
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.smartnc_trans_idle (smartnc_trans_idle ),
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.smartnc_trans_err (smartnc_trans_err ),
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.smartnc_intf_tx_fifo_wdata (smartnc_intf_tx_fifo_wdata ),
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.smartnc_intf_tx_fifo_wr_en (smartnc_intf_tx_fifo_wr_en ),
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.smartnc_intf_tx_fifo_afull (smartnc_intf_tx_fifo_afull ),
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.smartnc_intf_rx_fifo_empty (smartnc_intf_rx_fifo_empty ),
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.smartnc_intf_rx_fifo_rdata (smartnc_intf_rx_fifo_rdata ),
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.smartnc_intf_rx_fifo_rd_en (smartnc_intf_rx_fifo_rd_en ),
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.smartnt_intf_cmd_proc_req (smartnt_intf_cmd_proc_req ),
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.smartnt_intf_cmd_proc_ack (smartnt_intf_cmd_proc_ack ),
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.smartnt_intf_rx_fifo_empty (smartnt_intf_rx_fifo_empty ),
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.smartnt_intf_rx_fifo_rdata (smartnt_intf_rx_fifo_rdata ),
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.smartnt_intf_rx_fifo_rd_en (smartnt_intf_rx_fifo_rd_en ),
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.smartnt_intf_tx_fifo_wdata (smartnt_intf_tx_fifo_wdata ),
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.smartnt_intf_tx_fifo_wr_en (smartnt_intf_tx_fifo_wr_en ),
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.rx_datain_p_ch_a (rx_datain_p_ch_a ),
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.rx_datain_n_ch_a (rx_datain_n_ch_a ),
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.rx_datain_p_ch_b (rx_datain_p_ch_b ),
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.rx_datain_n_ch_b (rx_datain_n_ch_b ),
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.tx_dataout_p_ch_a (tx_dataout_p_ch_a ),
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.tx_dataout_n_ch_a (tx_dataout_n_ch_a ),
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.tx_dataout_p_ch_b (tx_dataout_p_ch_b ),
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.tx_dataout_n_ch_b (tx_dataout_n_ch_b ),
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.clk_ip (glink_ip_clk ),
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.o_reset_n (glink_ip_rst_n )
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);
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glink_smartncnt_intf u_glink_smartncnt_intf(
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.clk (glink_ip_clk ),
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.rst_n (glink_ip_rst_n ),
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.glink_gpio_i_0 (glink_gpio_i_0 ), // PS <- Glink
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.glink_gpio_i_1 (glink_gpio_i_1 ), // PS <- Glink
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.glink_gpio_o_0 (glink_gpio_o_0 ), // PS -> Glink
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.glink_gpio_o_1 (glink_gpio_o_1 ), // PS -> Glink
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.i_node_id (i_node_id ),//�ڵ� ID12'h003
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.i_node_id_par (i_node_id_par ),//��żУ�� 1'b1
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.i_smartnc_2nd_cfg (i_smartnc_2nd_cfg ),//SMARTNC���䳬ʱΪ128us 16'h0003
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.i_smartnc_3rd_cfg (i_smartnc_3rd_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h0400
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.i_smartnt_cfg (i_smartnt_cfg ),//����Ϊ�̱��Ĺ���ģʽ 16'h4000
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.smartnc_trans_trig (smartnc_trans_trig ),//gpio control
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.smartnc_trans_reset (smartnc_trans_reset ),//gpio control
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.smartnc_trans_idle (smartnc_trans_idle ),
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.smartnc_trans_err (smartnc_trans_err ),//gpio control
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.smartnc_intf_tx_fifo_wdata (smartnc_intf_tx_fifo_wdata ),
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.smartnc_intf_tx_fifo_wr_en (smartnc_intf_tx_fifo_wr_en ),
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.smartnc_intf_tx_fifo_afull (smartnc_intf_tx_fifo_afull ),
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.smartnc_intf_rx_fifo_empty (smartnc_intf_rx_fifo_empty ),
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.smartnc_intf_rx_fifo_rdata (smartnc_intf_rx_fifo_rdata ),
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.smartnc_intf_rx_fifo_rd_en (smartnc_intf_rx_fifo_rd_en ),
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.smartnt_intf_cmd_proc_req (smartnt_intf_cmd_proc_req ),
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.smartnt_intf_cmd_proc_ack (smartnt_intf_cmd_proc_ack ),
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.smartnt_intf_rx_fifo_empty (smartnt_intf_rx_fifo_empty ),
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.smartnt_intf_rx_fifo_rdata (smartnt_intf_rx_fifo_rdata ),
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.smartnt_intf_rx_fifo_rd_en (smartnt_intf_rx_fifo_rd_en ),
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.smartnt_intf_tx_fifo_wdata (smartnt_intf_tx_fifo_wdata ),
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.smartnt_intf_tx_fifo_wr_en (smartnt_intf_tx_fifo_wr_en ),
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.glink_tx_fifo_tdata (glink_tx_fifo_tdata[15:0] ),
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.glink_tx_fifo_tlast (glink_tx_fifo_tlast ),
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.glink_tx_fifo_tready (glink_tx_fifo_tready ),
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.glink_tx_fifo_tvalid (glink_tx_fifo_tvalid ),
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.glink_rx_fifo_tdata (glink_rx_fifo_tdata[15:0] ),
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.glink_rx_fifo_tlast (glink_rx_fifo_tlast ),
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.glink_rx_fifo_tready (glink_rx_fifo_tready ),
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.glink_rx_fifo_tvalid (glink_rx_fifo_tvalid )
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);
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endmodule
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