Update gitignore, add dl814_z7 project

gitignore structure is updated to work with single and multi project situation under a single project directory

projects/datalink_814/dl814_z7/rtl/reset_pls_extend.vhd

@@ -0,0 +1,130 @@
+-------------------------------------------------------------------------------
+-- Title      : reset_pls_extend
+-- Project    : 
+-------------------------------------------------------------------------------
+-- File       : reset_pls_extend.vhd
+-- Author     :   <zhanghb@ZHANGHONGBO>
+-- Company    : 
+-- Created    : 2012-06-13
+-- Last update: 2012-06-13
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: extend pulse width of reset signal
+-- parameter : 1.  polarity of input reset signal
+--             2.  polarity of output reset signal
+--             3.  pulse width of output reset signal, measured by clk.
+--             4.  bit width of counter
+-- To avoid problem when initiating reset_pls_extend module in verilog file,
+--    IN_POLARITY and OUT_POLARITY are defined as integer type.
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2012-06-13  1.0      zhanghb	Created
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity reset_pls_extend is
+  
+  generic (
+    IN_POLARITY : integer := 0;
+    OUT_POLARITY : integer := 0;    
+    EXTEND_WIDTH : integer := 8);
+  port (
+    clk     : in  std_logic;
+    i_reset : in  std_logic;
+    o_reset : out std_logic);
+end entity reset_pls_extend;
+
+architecture rtl of reset_pls_extend is
+
+  signal counter : integer range 0 to EXTEND_WIDTH;
+    
+  signal reset_reg : std_logic;         -- drive o_reset
+
+begin  -- architecture rtl
+
+  polarity_00 : if IN_POLARITY = 0 and OUT_POLARITY = 0 generate  
+  process (clk, i_reset) is
+  begin  -- process
+    if i_reset = '0' then  -- asynchronous reset
+      counter   <= 0;
+      reset_reg <= '0';
+    elsif clk'event and clk = '1' then   -- rising clock edge
+      if counter < EXTEND_WIDTH then
+        counter   <= counter + 1;
+        reset_reg <= '0';
+      else
+        counter   <= counter;
+        reset_reg <= '1';
+      end if;
+    end if;
+  end process;
+  end generate polarity_00;
+
+  polarity_01 : if IN_POLARITY = 0 and OUT_POLARITY = 1 generate  
+  process (clk, i_reset) is
+  begin  -- process
+    if i_reset = '0' then  -- asynchronous reset
+      counter   <= 0;
+      reset_reg <= '1';
+    elsif clk'event and clk = '1' then   -- rising clock edge
+      if counter < EXTEND_WIDTH then
+        counter   <= counter + 1;
+        reset_reg <= '1';
+      else
+        counter   <= counter;
+        reset_reg <= '0';
+      end if;
+    end if;
+  end process;
+  end generate polarity_01;
+
+  polarity_10 : if IN_POLARITY = 1 and OUT_POLARITY = 0 generate  
+  process (clk, i_reset) is
+  begin  -- process
+    if i_reset = '1' then  -- asynchronous reset
+      counter   <= 0;
+      reset_reg <= '0';
+    elsif clk'event and clk = '1' then   -- rising clock edge
+      if counter < EXTEND_WIDTH then
+        counter   <= counter + 1;
+        reset_reg <= '0';
+      else
+        counter   <= counter;
+        reset_reg <= '1';
+      end if;
+    end if;
+  end process;
+  end generate polarity_10;
+
+  polarity_11 : if IN_POLARITY = 1 and OUT_POLARITY = 1 generate  
+  process (clk, i_reset) is
+  begin  -- process
+    if i_reset = '1' then  -- asynchronous reset
+      counter   <= 0;
+      reset_reg <= '1';
+    elsif clk'event and clk = '1' then   -- rising clock edge
+      if counter < EXTEND_WIDTH then
+        counter   <= counter + 1;
+        reset_reg <= '1';
+      else
+        counter   <= counter;
+        reset_reg <= '0';
+      end if;
+    end if;
+  end process;
+  end generate polarity_11;    
+  
+  o_reset <= reset_reg;
+
+end architecture rtl;