Update gitignore, add dl814_z7 project

gitignore structure is updated to work with single and multi project situation under a single project directory
2023-03-29 10:42:01 +08:00
parent b000e2702e
commit cd256a8cd6
2246 changed files with 7838223 additions and 86 deletions
@@ -0,0 +1,49 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Mon Sep 12 16:54:54 2022
+// Host        : Ksling-PC running 64-bit major release  (build 9200)
+// Command     : write_verilog -mode synth_stub ttop_S_005X.v
+// Design      : ttop_S
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z045ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module ttop_S_005X(clock100, clkdv, clk50, n_rst, LED0, LED1, CLK, DATA, EN, 
+  DARY, TR, CLK_TR, DATA_TR, SYN_TR, SEL_TR, SEL4_TR, SEL3_TR, SEL2_TR, SEL1_TR, TR_TR, T_DLY, R_DLY, test1, 
+  test2, test3, test4, test5, test6, test7, test8)
+/* synthesis syn_black_box black_box_pad_pin="clock100,clkdv,clk50,n_rst,LED0,LED1,CLK,DATA,EN,DARY,TR,CLK_TR[3:0],DATA_TR[3:0],SYN_TR[3:0],SEL_TR[3:0],SEL4_TR[3:0],SEL3_TR[3:0],SEL2_TR[3:0],SEL1_TR[3:0],TR_TR[3:0],T_DLY,R_DLY,test1,test2,test3,test4,test5,test6,test7,test8" */;
+  input clock100;
+  input clkdv;
+  input clk50;
+  input n_rst;
+  output LED0;
+  output LED1;
+  input CLK;
+  input DATA;
+  input EN;
+  input DARY;
+  input TR;
+  output [3:0]CLK_TR;
+  output [3:0]DATA_TR;
+  output [3:0]SYN_TR;
+  output [3:0]SEL_TR;
+  output [3:0]SEL4_TR;
+  output [3:0]SEL3_TR;
+  output [3:0]SEL2_TR;
+  output [3:0]SEL1_TR;
+  output [3:0]TR_TR;
+  output T_DLY;
+  output R_DLY;
+  output test1;
+  output test2;
+  output test3;
+  output test4;
+  output test5;
+  output test6;
+  output test7;
+  output test8;
+endmodule