update dl814_k7_coarse; add ad9361 noise data

in dl814_k7_cal_coarse, change ant_clk to clk_96m, add rx_pre_test to verify nulling algorithm, with the ability to switch rx data between ad9361 data and test data

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.veo

@@ -0,0 +1,67 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 3
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+rom_hop_data your_instance_name (
+  .clka(clka),    // input wire clka
+  .addra(addra),  // input wire [13 : 0] addra
+  .douta(douta)  // output wire [95 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file rom_hop_data.v when simulating
+// the core, rom_hop_data. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.vho

@@ -0,0 +1,79 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 3
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT rom_hop_data
+  PORT (
+    clka : IN STD_LOGIC;
+    addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : rom_hop_data
+  PORT MAP (
+    clka => clka,
+    addra => addra,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file rom_hop_data.vhd when simulating
+-- the core, rom_hop_data. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data/rom_hop_data_stub.v

@@ -0,0 +1,22 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Mon Apr  3 20:43:37 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v
+// Design      : rom_hop_data
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
+module rom_hop_data(clka, addra, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,addra[13:0],douta[95:0]" */;
+  input clka;
+  input [13:0]addra;
+  output [95:0]douta;
+endmodule

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data/rom_hop_data_stub.vhdl

@@ -0,0 +1,32 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Mon Apr  3 20:43:37 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl
+-- Design      : rom_hop_data
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity rom_hop_data is
+  Port ( 
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 95 downto 0 )
+  );
+
+end rom_hop_data;
+
+architecture stub of rom_hop_data is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,addra[13:0],douta[95:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
+begin
+end;

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/rom_hop_data/sim/rom_hop_data.v

@@ -0,0 +1,211 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 3
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module rom_hop_data (
+  clka,
+  addra,
+  douta
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
+input wire clka;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
+input wire [13 : 0] addra;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
+output wire [95 : 0] douta;
+
+  blk_mem_gen_v8_4_3 #(
+    .C_FAMILY("kintex7"),
+    .C_XDEVICEFAMILY("kintex7"),
+    .C_ELABORATION_DIR("./"),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_USE_BRAM_BLOCK(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_CTRL_ECC_ALGO("NONE"),
+    .C_HAS_AXI_ID(0),
+    .C_AXI_ID_WIDTH(4),
+    .C_MEM_TYPE(3),
+    .C_BYTE_SIZE(9),
+    .C_ALGORITHM(1),
+    .C_PRIM_TYPE(1),
+    .C_LOAD_INIT_FILE(1),
+    .C_INIT_FILE_NAME("rom_hop_data.mif"),
+    .C_INIT_FILE("rom_hop_data.mem"),
+    .C_USE_DEFAULT_DATA(0),
+    .C_DEFAULT_DATA("0"),
+    .C_HAS_RSTA(0),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RSTRAM_A(0),
+    .C_INITA_VAL("0"),
+    .C_HAS_ENA(0),
+    .C_HAS_REGCEA(0),
+    .C_USE_BYTE_WEA(0),
+    .C_WEA_WIDTH(1),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(96),
+    .C_READ_WIDTH_A(96),
+    .C_WRITE_DEPTH_A(9600),
+    .C_READ_DEPTH_A(9600),
+    .C_ADDRA_WIDTH(14),
+    .C_HAS_RSTB(0),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RSTRAM_B(0),
+    .C_INITB_VAL("0"),
+    .C_HAS_ENB(0),
+    .C_HAS_REGCEB(0),
+    .C_USE_BYTE_WEB(0),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_B(96),
+    .C_READ_WIDTH_B(96),
+    .C_WRITE_DEPTH_B(9600),
+    .C_READ_DEPTH_B(9600),
+    .C_ADDRB_WIDTH(14),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_USE_SOFTECC(0),
+    .C_USE_ECC(0),
+    .C_EN_ECC_PIPE(0),
+    .C_READ_LATENCY_A(1),
+    .C_READ_LATENCY_B(1),
+    .C_HAS_INJECTERR(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_COMMON_CLK(0),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_EN_SLEEP_PIN(0),
+    .C_USE_URAM(0),
+    .C_EN_RDADDRA_CHG(0),
+    .C_EN_RDADDRB_CHG(0),
+    .C_EN_DEEPSLEEP_PIN(0),
+    .C_EN_SHUTDOWN_PIN(0),
+    .C_EN_SAFETY_CKT(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_COUNT_36K_BRAM("26"),
+    .C_COUNT_18K_BRAM("1"),
+    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     23.399606 mW")
+  ) inst (
+    .clka(clka),
+    .rsta(1'D0),
+    .ena(1'D0),
+    .regcea(1'D0),
+    .wea(1'B0),
+    .addra(addra),
+    .dina(96'B0),
+    .douta(douta),
+    .clkb(1'D0),
+    .rstb(1'D0),
+    .enb(1'D0),
+    .regceb(1'D0),
+    .web(1'B0),
+    .addrb(14'B0),
+    .dinb(96'B0),
+    .doutb(),
+    .injectsbiterr(1'D0),
+    .injectdbiterr(1'D0),
+    .eccpipece(1'D0),
+    .sbiterr(),
+    .dbiterr(),
+    .rdaddrecc(),
+    .sleep(1'D0),
+    .deepsleep(1'D0),
+    .shutdown(1'D0),
+    .rsta_busy(),
+    .rstb_busy(),
+    .s_aclk(1'H0),
+    .s_aresetn(1'D0),
+    .s_axi_awid(4'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wdata(96'B0),
+    .s_axi_wstrb(1'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .s_axi_arid(4'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .s_axi_injectsbiterr(1'D0),
+    .s_axi_injectdbiterr(1'D0),
+    .s_axi_sbiterr(),
+    .s_axi_dbiterr(),
+    .s_axi_rdaddrecc()
+  );
+endmodule

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/hdl/vio_v3_0_20_vio_include.v

@@ -1,283 +0,0 @@
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-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect data_method = "AES128-CBC"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
-`pragma protect data_block
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-`pragma protect end_protected

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v

@@ -53,7 +53,8 @@ probe_out0,
 probe_out1,
 probe_out2,
 probe_out3,
-probe_out4
+probe_out4,
+probe_out5
 );
 
 input clk;
@@ -63,6 +64,7 @@ output reg [0 : 0] probe_out1 = 'h0 ;
 output reg [31 : 0] probe_out2 = 'h00000000 ;
 output reg [1 : 0] probe_out3 = 'h3 ;
 output reg [3 : 0] probe_out4 = 'h0 ;
+output reg [0 : 0] probe_out5 = 'h0 ;
 
 
 endmodule

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo

@@ -60,7 +60,8 @@ vio_manual_ctrl your_instance_name (
   .probe_out1(probe_out1),  // output wire [0 : 0] probe_out1
   .probe_out2(probe_out2),  // output wire [31 : 0] probe_out2
   .probe_out3(probe_out3),  // output wire [1 : 0] probe_out3
-  .probe_out4(probe_out4)  // output wire [3 : 0] probe_out4
+  .probe_out4(probe_out4),  // output wire [3 : 0] probe_out4
+  .probe_out5(probe_out5)  // output wire [0 : 0] probe_out5
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------
 

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho

@@ -59,7 +59,8 @@ COMPONENT vio_manual_ctrl
     probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
     probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-    probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+    probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
   );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -75,7 +76,8 @@ your_instance_name : vio_manual_ctrl
     probe_out1 => probe_out1,
     probe_out2 => probe_out2,
     probe_out3 => probe_out3,
-    probe_out4 => probe_out4
+    probe_out4 => probe_out4,
+    probe_out5 => probe_out5
   );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------
 

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
--- Date        : Tue Mar 21 22:54:43 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Mon Apr  3 20:47:45 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode funcsim
---               D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl
+--               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl
 -- Design      : vio_manual_ctrl
 -- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
 --               synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -116,17 +116,15 @@ begin
   in0 <= \^in0\;
   internal_cnt_rst <= \^internal_cnt_rst\;
   s_den_o_INST_0 <= \^s_den_o_inst_0\;
-\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6
+\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT4
     generic map(
-      INIT => X"FFFF444E0000444E"
+      INIT => X"A0AC"
     )
         port map (
-      I0 => xsdb_addr_2_0_p2(0),
+      I0 => Q(0),
       I1 => \Bus_data_out[0]_i_2_n_0\,
-      I2 => xsdb_addr_2_0_p2(2),
-      I3 => xsdb_addr_2_0_p2(1),
-      I4 => xsdb_addr_8_p2,
-      I5 => Q(0),
+      I2 => xsdb_addr_8_p2,
+      I3 => xsdb_addr_2_0_p2(0),
       O => \Bus_data_out[0]_i_1_n_0\
     );
 \Bus_data_out[0]_i_2\: unisim.vcomponents.LUT5
@@ -219,15 +217,17 @@ begin
       I5 => xsdb_addr_2_0_p2(2),
       O => \Bus_data_out[15]_i_1_n_0\
     );
-\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT4
+\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT6
     generic map(
-      INIT => X"A0AC"
+      INIT => X"FFFF444E0000444E"
     )
         port map (
-      I0 => Q(1),
+      I0 => xsdb_addr_2_0_p2(0),
       I1 => \Bus_data_out[1]_i_2_n_0\,
-      I2 => xsdb_addr_8_p2,
-      I3 => xsdb_addr_2_0_p2(0),
+      I2 => xsdb_addr_2_0_p2(2),
+      I3 => xsdb_addr_2_0_p2(1),
+      I4 => xsdb_addr_8_p2,
+      I5 => Q(1),
       O => \Bus_data_out[1]_i_1_n_0\
     );
 \Bus_data_out[1]_i_2\: unisim.vcomponents.LUT5
@@ -921,7 +921,7 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_out_one is
     D : out STD_LOGIC_VECTOR ( 1 downto 0 );
     SR : in STD_LOGIC_VECTOR ( 0 to 0 );
     Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
-    wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+    \G_PROBE_OUT[0].wr_probe_out_reg\ : in STD_LOGIC;
     \out\ : in STD_LOGIC;
     E : in STD_LOGIC_VECTOR ( 0 to 0 );
     clk : in STD_LOGIC
@@ -964,7 +964,7 @@ begin
     )
         port map (
       I0 => Q(0),
-      I1 => wr_probe_out(0),
+      I1 => \G_PROBE_OUT[0].wr_probe_out_reg\,
       I2 => \^d\(0),
       O => \data_int[0]_i_1_n_0\
     );
@@ -974,7 +974,7 @@ begin
     )
         port map (
       I0 => Q(1),
-      I1 => wr_probe_out(0),
+      I1 => \G_PROBE_OUT[0].wr_probe_out_reg\,
       I2 => \^d\(1),
       O => \data_int[1]_i_1_n_0\
     );
@@ -1008,7 +1008,7 @@ entity \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0\ is
     clk : in STD_LOGIC;
     \out\ : in STD_LOGIC;
     Q : in STD_LOGIC_VECTOR ( 0 to 0 );
-    wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 )
+    \G_PROBE_OUT[1].wr_probe_out_reg\ : in STD_LOGIC
   );
   attribute ORIG_REF_NAME : string;
   attribute ORIG_REF_NAME of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0\ : entity is "vio_v3_0_20_probe_out_one";
@@ -1037,7 +1037,7 @@ begin
     )
         port map (
       I0 => Q(0),
-      I1 => wr_probe_out(0),
+      I1 => \G_PROBE_OUT[1].wr_probe_out_reg\,
       I2 => \^data_int_reg[0]_0\,
       O => \data_int[0]_i_1_n_0\
     );
@@ -1054,6 +1054,61 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 library UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
+entity \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0_0\ is
+  port (
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    \data_int_reg[0]_0\ : out STD_LOGIC;
+    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
+    \out\ : in STD_LOGIC;
+    clk : in STD_LOGIC;
+    \data_int_reg[0]_1\ : in STD_LOGIC;
+    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
+    \G_PROBE_OUT[5].wr_probe_out_reg\ : in STD_LOGIC
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0_0\ : entity is "vio_v3_0_20_probe_out_one";
+end \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0_0\;
+
+architecture STRUCTURE of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0_0\ is
+  signal \data_int[0]_i_1__0_n_0\ : STD_LOGIC;
+  signal \^data_int_reg[0]_0\ : STD_LOGIC;
+  attribute DONT_TOUCH : boolean;
+  attribute DONT_TOUCH of \Probe_out_reg[0]\ : label is std.standard.true;
+  attribute KEEP : string;
+  attribute KEEP of \Probe_out_reg[0]\ : label is "yes";
+begin
+  \data_int_reg[0]_0\ <= \^data_int_reg[0]_0\;
+\Probe_out_reg[0]\: unisim.vcomponents.FDRE
+     port map (
+      C => clk,
+      CE => \out\,
+      D => \^data_int_reg[0]_0\,
+      Q => probe_out5(0),
+      R => SR(0)
+    );
+\data_int[0]_i_1__0\: unisim.vcomponents.LUT3
+    generic map(
+      INIT => X"B8"
+    )
+        port map (
+      I0 => Q(0),
+      I1 => \G_PROBE_OUT[5].wr_probe_out_reg\,
+      I2 => \^data_int_reg[0]_0\,
+      O => \data_int[0]_i_1__0_n_0\
+    );
+\data_int_reg[0]\: unisim.vcomponents.FDRE
+     port map (
+      C => \data_int_reg[0]_1\,
+      CE => '1',
+      D => \data_int[0]_i_1__0_n_0\,
+      Q => \^data_int_reg[0]_0\,
+      R => SR(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
 entity \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1\ is
   port (
     probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -1067,7 +1122,7 @@ entity \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1\ is
     \out\ : in STD_LOGIC;
     E : in STD_LOGIC_VECTOR ( 0 to 0 );
     Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
-    \Probe_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+    \Probe_out_reg[31]_0\ : in STD_LOGIC;
     clk : in STD_LOGIC
   );
   attribute ORIG_REF_NAME : string;
@@ -1098,7 +1153,7 @@ architecture STRUCTURE of \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameteri
   signal \addr_count[1]_i_4_n_0\ : STD_LOGIC;
   signal \^addr_count[1]_i_5_0\ : STD_LOGIC;
   signal \mem_probe_out[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
-  signal rd_probe_out : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal rd_probe_out : STD_LOGIC;
   attribute SOFT_HLUTNM : string;
   attribute SOFT_HLUTNM of \Bus_Data_out_int[0]_i_1\ : label is "soft_lutpair21";
   attribute SOFT_HLUTNM of \Bus_Data_out_int[10]_i_1\ : label is "soft_lutpair16";
@@ -1606,7 +1661,7 @@ begin
 \Probe_out_reg[0]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(0),
       Q => probe_out2(0),
       R => SR(0)
@@ -1614,7 +1669,7 @@ begin
 \Probe_out_reg[10]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(10),
       Q => probe_out2(10),
       R => SR(0)
@@ -1622,7 +1677,7 @@ begin
 \Probe_out_reg[11]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(11),
       Q => probe_out2(11),
       R => SR(0)
@@ -1630,7 +1685,7 @@ begin
 \Probe_out_reg[12]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(12),
       Q => probe_out2(12),
       R => SR(0)
@@ -1638,7 +1693,7 @@ begin
 \Probe_out_reg[13]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(13),
       Q => probe_out2(13),
       R => SR(0)
@@ -1646,7 +1701,7 @@ begin
 \Probe_out_reg[14]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(14),
       Q => probe_out2(14),
       R => SR(0)
@@ -1654,7 +1709,7 @@ begin
 \Probe_out_reg[15]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(15),
       Q => probe_out2(15),
       R => SR(0)
@@ -1662,7 +1717,7 @@ begin
 \Probe_out_reg[16]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(16),
       Q => probe_out2(16),
       R => SR(0)
@@ -1670,7 +1725,7 @@ begin
 \Probe_out_reg[17]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(17),
       Q => probe_out2(17),
       R => SR(0)
@@ -1678,7 +1733,7 @@ begin
 \Probe_out_reg[18]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(18),
       Q => probe_out2(18),
       R => SR(0)
@@ -1686,7 +1741,7 @@ begin
 \Probe_out_reg[19]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(19),
       Q => probe_out2(19),
       R => SR(0)
@@ -1694,7 +1749,7 @@ begin
 \Probe_out_reg[1]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(1),
       Q => probe_out2(1),
       R => SR(0)
@@ -1702,7 +1757,7 @@ begin
 \Probe_out_reg[20]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(20),
       Q => probe_out2(20),
       R => SR(0)
@@ -1710,7 +1765,7 @@ begin
 \Probe_out_reg[21]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(21),
       Q => probe_out2(21),
       R => SR(0)
@@ -1718,7 +1773,7 @@ begin
 \Probe_out_reg[22]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(22),
       Q => probe_out2(22),
       R => SR(0)
@@ -1726,7 +1781,7 @@ begin
 \Probe_out_reg[23]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(23),
       Q => probe_out2(23),
       R => SR(0)
@@ -1734,7 +1789,7 @@ begin
 \Probe_out_reg[24]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(24),
       Q => probe_out2(24),
       R => SR(0)
@@ -1742,7 +1797,7 @@ begin
 \Probe_out_reg[25]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(25),
       Q => probe_out2(25),
       R => SR(0)
@@ -1750,7 +1805,7 @@ begin
 \Probe_out_reg[26]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(26),
       Q => probe_out2(26),
       R => SR(0)
@@ -1758,7 +1813,7 @@ begin
 \Probe_out_reg[27]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(27),
       Q => probe_out2(27),
       R => SR(0)
@@ -1766,7 +1821,7 @@ begin
 \Probe_out_reg[28]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(28),
       Q => probe_out2(28),
       R => SR(0)
@@ -1774,7 +1829,7 @@ begin
 \Probe_out_reg[29]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(29),
       Q => probe_out2(29),
       R => SR(0)
@@ -1782,7 +1837,7 @@ begin
 \Probe_out_reg[2]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(2),
       Q => probe_out2(2),
       R => SR(0)
@@ -1790,7 +1845,7 @@ begin
 \Probe_out_reg[30]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(30),
       Q => probe_out2(30),
       R => SR(0)
@@ -1798,7 +1853,7 @@ begin
 \Probe_out_reg[31]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(31),
       Q => probe_out2(31),
       R => SR(0)
@@ -1806,7 +1861,7 @@ begin
 \Probe_out_reg[3]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(3),
       Q => probe_out2(3),
       R => SR(0)
@@ -1814,7 +1869,7 @@ begin
 \Probe_out_reg[4]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(4),
       Q => probe_out2(4),
       R => SR(0)
@@ -1822,7 +1877,7 @@ begin
 \Probe_out_reg[5]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(5),
       Q => probe_out2(5),
       R => SR(0)
@@ -1830,7 +1885,7 @@ begin
 \Probe_out_reg[6]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(6),
       Q => probe_out2(6),
       R => SR(0)
@@ -1838,7 +1893,7 @@ begin
 \Probe_out_reg[7]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(7),
       Q => probe_out2(7),
       R => SR(0)
@@ -1846,7 +1901,7 @@ begin
 \Probe_out_reg[8]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(8),
       Q => probe_out2(8),
       R => SR(0)
@@ -1854,7 +1909,7 @@ begin
 \Probe_out_reg[9]\: unisim.vcomponents.FDRE
      port map (
       C => clk,
-      CE => \Probe_out_reg[31]_0\(0),
+      CE => \Probe_out_reg[31]_0\,
       D => \mem_probe_out[0]\(9),
       Q => probe_out2(9),
       R => SR(0)
@@ -1867,7 +1922,7 @@ begin
       I0 => addr_count(0),
       I1 => internal_cnt_rst,
       I2 => addr_count(0),
-      I3 => rd_probe_out(2),
+      I3 => rd_probe_out,
       O => \addr_count[0]_i_1_n_0\
     );
 \addr_count[1]_i_1\: unisim.vcomponents.LUT5
@@ -1879,7 +1934,7 @@ begin
       I1 => internal_cnt_rst,
       I2 => addr_count(1),
       I3 => addr_count(0),
-      I4 => rd_probe_out(2),
+      I4 => rd_probe_out,
       O => \addr_count[1]_i_1_n_0\
     );
 \addr_count[1]_i_2\: unisim.vcomponents.LUT6
@@ -1893,7 +1948,7 @@ begin
       I3 => s_daddr_o(8),
       I4 => s_daddr_o(6),
       I5 => s_daddr_o(7),
-      O => rd_probe_out(2)
+      O => rd_probe_out
     );
 \addr_count[1]_i_3\: unisim.vcomponents.LUT6
     generic map(
@@ -2087,7 +2142,7 @@ entity \vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized2\ is
     D : out STD_LOGIC_VECTOR ( 1 downto 0 );
     SR : in STD_LOGIC_VECTOR ( 0 to 0 );
     Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
-    wr_probe_out : in STD_LOGIC_VECTOR ( 0 to 0 );
+    \G_PROBE_OUT[3].wr_probe_out_reg\ : in STD_LOGIC;
     \out\ : in STD_LOGIC;
     \Probe_out_reg[1]_0\ : in STD_LOGIC;
     clk : in STD_LOGIC
@@ -2133,7 +2188,7 @@ begin
     )
         port map (
       I0 => Q(0),
-      I1 => wr_probe_out(0),
+      I1 => \G_PROBE_OUT[3].wr_probe_out_reg\,
       I2 => \^d\(0),
       O => \data_int[0]_i_1_n_0\
     );
@@ -2143,7 +2198,7 @@ begin
     )
         port map (
       I0 => Q(1),
-      I1 => wr_probe_out(0),
+      I1 => \G_PROBE_OUT[3].wr_probe_out_reg\,
       I2 => \^d\(1),
       O => \data_int[1]_i_1_n_0\
     );
@@ -2272,7 +2327,7 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_width is
     rd_probe_out_width : in STD_LOGIC;
     s_rst_o : in STD_LOGIC;
     internal_cnt_rst : in STD_LOGIC;
-    \out\ : in STD_LOGIC
+    CLK : in STD_LOGIC
   );
   attribute ORIG_REF_NAME : string;
   attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_probe_width : entity is "vio_v3_0_20_probe_width";
@@ -2284,10 +2339,10 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_width is
   signal \addr_count[1]_i_1_n_0\ : STD_LOGIC;
   signal probe_width_mem : STD_LOGIC_VECTOR ( 8 downto 0 );
   attribute SOFT_HLUTNM : string;
-  attribute SOFT_HLUTNM of \addr_count[0]_i_1\ : label is "soft_lutpair30";
-  attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair30";
-  attribute SOFT_HLUTNM of \probe_width_int[1]_i_1\ : label is "soft_lutpair31";
-  attribute SOFT_HLUTNM of \probe_width_int[8]_i_1\ : label is "soft_lutpair31";
+  attribute SOFT_HLUTNM of \addr_count[0]_i_1\ : label is "soft_lutpair29";
+  attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair29";
+  attribute SOFT_HLUTNM of \probe_width_int[1]_i_1\ : label is "soft_lutpair30";
+  attribute SOFT_HLUTNM of \probe_width_int[8]_i_1\ : label is "soft_lutpair30";
 begin
 \addr_count[0]_i_1\: unisim.vcomponents.LUT5
     generic map(
@@ -2315,7 +2370,7 @@ begin
     );
 \addr_count_reg[0]\: unisim.vcomponents.FDRE
      port map (
-      C => \out\,
+      C => CLK,
       CE => '1',
       D => \addr_count[0]_i_1_n_0\,
       Q => addr_count(0),
@@ -2323,7 +2378,7 @@ begin
     );
 \addr_count_reg[1]\: unisim.vcomponents.FDRE
      port map (
-      C => \out\,
+      C => CLK,
       CE => '1',
       D => \addr_count[1]_i_1_n_0\,
       Q => addr_count(1),
@@ -2358,7 +2413,7 @@ begin
     );
 \probe_width_int_reg[0]\: unisim.vcomponents.FDRE
      port map (
-      C => \out\,
+      C => CLK,
       CE => '1',
       D => probe_width_mem(0),
       Q => Q(0),
@@ -2366,7 +2421,7 @@ begin
     );
 \probe_width_int_reg[1]\: unisim.vcomponents.FDRE
      port map (
-      C => \out\,
+      C => CLK,
       CE => '1',
       D => probe_width_mem(1),
       Q => Q(1),
@@ -2374,7 +2429,7 @@ begin
     );
 \probe_width_int_reg[8]\: unisim.vcomponents.FDRE
      port map (
-      C => \out\,
+      C => CLK,
       CE => '1',
       D => probe_width_mem(8),
       Q => Q(2),
@@ -5384,6 +5439,7 @@ entity vio_manual_ctrl_vio_v3_0_20_probe_out_all is
     probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
     probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
     probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
     \addr_count[1]_i_5\ : out STD_LOGIC;
     \addr_p1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
     \Probe_out_reg_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
@@ -5428,20 +5484,27 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is
   signal \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\ : STD_LOGIC;
   signal \G_PROBE_OUT[0].wr_probe_out[0]_i_2_n_0\ : STD_LOGIC;
   signal \G_PROBE_OUT[0].wr_probe_out[0]_i_6_n_0\ : STD_LOGIC;
+  signal \G_PROBE_OUT[0].wr_probe_out_reg\ : STD_LOGIC;
   signal \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\ : STD_LOGIC;
   signal \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\ : STD_LOGIC;
   signal \G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0\ : STD_LOGIC;
+  signal \G_PROBE_OUT[1].wr_probe_out_reg\ : STD_LOGIC;
   signal \G_PROBE_OUT[2].PROBE_OUT0_INST_n_32\ : STD_LOGIC;
   signal \G_PROBE_OUT[2].wr_probe_out[2]_i_1_n_0\ : STD_LOGIC;
   signal \G_PROBE_OUT[2].wr_probe_out_reg\ : STD_LOGIC;
   signal \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2\ : STD_LOGIC;
   signal \G_PROBE_OUT[3].PROBE_OUT0_INST_n_3\ : STD_LOGIC;
   signal \G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0\ : STD_LOGIC;
+  signal \G_PROBE_OUT[3].wr_probe_out_reg\ : STD_LOGIC;
   signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_4\ : STD_LOGIC;
   signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\ : STD_LOGIC;
   signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_6\ : STD_LOGIC;
   signal \G_PROBE_OUT[4].PROBE_OUT0_INST_n_7\ : STD_LOGIC;
   signal \G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0\ : STD_LOGIC;
+  signal \G_PROBE_OUT[4].wr_probe_out_reg\ : STD_LOGIC;
+  signal \G_PROBE_OUT[5].PROBE_OUT0_INST_n_1\ : STD_LOGIC;
+  signal \G_PROBE_OUT[5].wr_probe_out[5]_i_1_n_0\ : STD_LOGIC;
+  signal \G_PROBE_OUT[5].wr_probe_out_reg\ : STD_LOGIC;
   signal \Probe_out_reg_int[0]_i_2_n_0\ : STD_LOGIC;
   signal \Probe_out_reg_int[10]_i_1_n_0\ : STD_LOGIC;
   signal \Probe_out_reg_int[11]_i_1_n_0\ : STD_LOGIC;
@@ -5459,7 +5522,6 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is
   signal \^addr_count[1]_i_5\ : STD_LOGIC;
   signal \^addr_p1_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
   signal probe_out_mem : STD_LOGIC_VECTOR ( 3 downto 0 );
-  signal wr_probe_out : STD_LOGIC_VECTOR ( 4 downto 0 );
   attribute ASYNC_REG_boolean : boolean;
   attribute ASYNC_REG_boolean of Committ_1_reg : label is std.standard.true;
   attribute KEEP : string;
@@ -5467,20 +5529,18 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_probe_out_all is
   attribute ASYNC_REG_boolean of Committ_2_reg : label is std.standard.true;
   attribute KEEP of Committ_2_reg : label is "yes";
   attribute SOFT_HLUTNM : string;
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[0]_i_1\ : label is "soft_lutpair23";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[10]_i_1\ : label is "soft_lutpair27";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[11]_i_1\ : label is "soft_lutpair26";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[12]_i_1\ : label is "soft_lutpair24";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[13]_i_1\ : label is "soft_lutpair25";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[14]_i_1\ : label is "soft_lutpair25";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[15]_i_1\ : label is "soft_lutpair24";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[1]_i_1\ : label is "soft_lutpair23";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[4]_i_1\ : label is "soft_lutpair29";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[5]_i_1\ : label is "soft_lutpair29";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[6]_i_1\ : label is "soft_lutpair28";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[7]_i_1\ : label is "soft_lutpair28";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[8]_i_1\ : label is "soft_lutpair27";
-  attribute SOFT_HLUTNM of \Probe_out_reg_int[9]_i_1\ : label is "soft_lutpair26";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[10]_i_1\ : label is "soft_lutpair26";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[11]_i_1\ : label is "soft_lutpair25";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[12]_i_1\ : label is "soft_lutpair23";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[13]_i_1\ : label is "soft_lutpair24";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[14]_i_1\ : label is "soft_lutpair24";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[15]_i_1\ : label is "soft_lutpair23";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[4]_i_1\ : label is "soft_lutpair28";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[5]_i_1\ : label is "soft_lutpair28";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[6]_i_1\ : label is "soft_lutpair27";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[7]_i_1\ : label is "soft_lutpair27";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[8]_i_1\ : label is "soft_lutpair26";
+  attribute SOFT_HLUTNM of \Probe_out_reg_int[9]_i_1\ : label is "soft_lutpair25";
 begin
   \addr_count[1]_i_5\ <= \^addr_count[1]_i_5\;
   \addr_p1_reg[2]_0\(2 downto 0) <= \^addr_p1_reg[2]_0\(2 downto 0);
@@ -5505,12 +5565,12 @@ Committ_2_reg: unisim.vcomponents.FDRE
       D(1) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_2\,
       D(0) => \G_PROBE_OUT[0].PROBE_OUT0_INST_n_3\,
       E(0) => Committ_2,
+      \G_PROBE_OUT[0].wr_probe_out_reg\ => \G_PROBE_OUT[0].wr_probe_out_reg\,
       Q(1 downto 0) => Q(1 downto 0),
       SR(0) => SR(0),
       clk => clk,
       \out\ => \out\,
-      probe_out0(1 downto 0) => probe_out0(1 downto 0),
-      wr_probe_out(0) => wr_probe_out(0)
+      probe_out0(1 downto 0) => probe_out0(1 downto 0)
     );
 \G_PROBE_OUT[0].wr_probe_out[0]_i_1\: unisim.vcomponents.LUT4
     generic map(
@@ -5550,19 +5610,19 @@ Committ_2_reg: unisim.vcomponents.FDRE
       C => \out\,
       CE => '1',
       D => \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0\,
-      Q => wr_probe_out(0),
+      Q => \G_PROBE_OUT[0].wr_probe_out_reg\,
       R => '0'
     );
 \G_PROBE_OUT[1].PROBE_OUT0_INST\: entity work.\vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0\
      port map (
       E(0) => Committ_2,
+      \G_PROBE_OUT[1].wr_probe_out_reg\ => \G_PROBE_OUT[1].wr_probe_out_reg\,
       Q(0) => Q(0),
       SR(0) => SR(0),
       clk => clk,
       \data_int_reg[0]_0\ => \G_PROBE_OUT[1].PROBE_OUT0_INST_n_1\,
       \out\ => \out\,
-      probe_out1(0) => probe_out1(0),
-      wr_probe_out(0) => wr_probe_out(1)
+      probe_out1(0) => probe_out1(0)
     );
 \G_PROBE_OUT[1].wr_probe_out[1]_i_1\: unisim.vcomponents.LUT4
     generic map(
@@ -5605,14 +5665,14 @@ Committ_2_reg: unisim.vcomponents.FDRE
       C => \out\,
       CE => '1',
       D => \G_PROBE_OUT[1].wr_probe_out[1]_i_2_n_0\,
-      Q => wr_probe_out(1),
+      Q => \G_PROBE_OUT[1].wr_probe_out_reg\,
       R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\
     );
 \G_PROBE_OUT[2].PROBE_OUT0_INST\: entity work.\vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized1\
      port map (
       \Bus_Data_out_int_reg[15]_0\(15 downto 0) => Bus_Data_out_int(15 downto 0),
       E(0) => \G_PROBE_OUT[2].wr_probe_out_reg\,
-      \Probe_out_reg[31]_0\(0) => Committ_2,
+      \Probe_out_reg[31]_0\ => Committ_2,
       Q(15 downto 0) => Q(15 downto 0),
       SR(0) => SR(0),
       \addr_count[1]_i_5_0\ => \G_PROBE_OUT[2].PROBE_OUT0_INST_n_32\,
@@ -5649,13 +5709,13 @@ Committ_2_reg: unisim.vcomponents.FDRE
      port map (
       D(1) => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_2\,
       D(0) => \G_PROBE_OUT[3].PROBE_OUT0_INST_n_3\,
+      \G_PROBE_OUT[3].wr_probe_out_reg\ => \G_PROBE_OUT[3].wr_probe_out_reg\,
       \Probe_out_reg[1]_0\ => Committ_2,
       Q(1 downto 0) => Q(1 downto 0),
       SR(0) => SR(0),
       clk => clk,
       \out\ => \out\,
-      probe_out3(1 downto 0) => probe_out3(1 downto 0),
-      wr_probe_out(0) => wr_probe_out(3)
+      probe_out3(1 downto 0) => probe_out3(1 downto 0)
     );
 \G_PROBE_OUT[3].wr_probe_out[3]_i_1\: unisim.vcomponents.LUT6
     generic map(
@@ -5675,12 +5735,12 @@ Committ_2_reg: unisim.vcomponents.FDRE
       C => \out\,
       CE => '1',
       D => \G_PROBE_OUT[3].wr_probe_out[3]_i_1_n_0\,
-      Q => wr_probe_out(3),
+      Q => \G_PROBE_OUT[3].wr_probe_out_reg\,
       R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\
     );
 \G_PROBE_OUT[4].PROBE_OUT0_INST\: entity work.\vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized3\
      port map (
-      E(0) => wr_probe_out(4),
+      E(0) => \G_PROBE_OUT[4].wr_probe_out_reg\,
       \Probe_out_reg[3]_0\ => Committ_2,
       Q(3) => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_4\,
       Q(2) => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\,
@@ -5710,17 +5770,51 @@ Committ_2_reg: unisim.vcomponents.FDRE
       C => \out\,
       CE => '1',
       D => \G_PROBE_OUT[4].wr_probe_out[4]_i_1_n_0\,
-      Q => wr_probe_out(4),
+      Q => \G_PROBE_OUT[4].wr_probe_out_reg\,
       R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\
     );
-\Probe_out_reg_int[0]_i_1\: unisim.vcomponents.LUT3
+\G_PROBE_OUT[5].PROBE_OUT0_INST\: entity work.\vio_manual_ctrl_vio_v3_0_20_probe_out_one__parameterized0_0\
+     port map (
+      \G_PROBE_OUT[5].wr_probe_out_reg\ => \G_PROBE_OUT[5].wr_probe_out_reg\,
+      Q(0) => Q(0),
+      SR(0) => SR(0),
+      clk => clk,
+      \data_int_reg[0]_0\ => \G_PROBE_OUT[5].PROBE_OUT0_INST_n_1\,
+      \data_int_reg[0]_1\ => \out\,
+      \out\ => Committ_2,
+      probe_out5(0) => probe_out5(0)
+    );
+\G_PROBE_OUT[5].wr_probe_out[5]_i_1\: unisim.vcomponents.LUT6
     generic map(
-      INIT => X"B8"
+      INIT => X"0000000008000000"
     )
         port map (
-      I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_7\,
-      I1 => \^addr_p1_reg[2]_0\(2),
-      I2 => \Probe_out_reg_int[0]_i_2_n_0\,
+      I0 => s_daddr_o(2),
+      I1 => s_daddr_o(0),
+      I2 => s_daddr_o(1),
+      I3 => s_dwe_o,
+      I4 => s_den_o,
+      I5 => s_daddr_o(16),
+      O => \G_PROBE_OUT[5].wr_probe_out[5]_i_1_n_0\
+    );
+\G_PROBE_OUT[5].wr_probe_out_reg[5]\: unisim.vcomponents.FDRE
+     port map (
+      C => \out\,
+      CE => '1',
+      D => \G_PROBE_OUT[5].wr_probe_out[5]_i_1_n_0\,
+      Q => \G_PROBE_OUT[5].wr_probe_out_reg\,
+      R => \G_PROBE_OUT[1].wr_probe_out[1]_i_1_n_0\
+    );
+\Probe_out_reg_int[0]_i_1\: unisim.vcomponents.LUT5
+    generic map(
+      INIT => X"B8FFB800"
+    )
+        port map (
+      I0 => \G_PROBE_OUT[5].PROBE_OUT0_INST_n_1\,
+      I1 => \^addr_p1_reg[2]_0\(0),
+      I2 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_7\,
+      I3 => \^addr_p1_reg[2]_0\(2),
+      I4 => \Probe_out_reg_int[0]_i_2_n_0\,
       O => probe_out_mem(0)
     );
 \Probe_out_reg_int[0]_i_2\: unisim.vcomponents.LUT6
@@ -5796,14 +5890,15 @@ Committ_2_reg: unisim.vcomponents.FDRE
       I2 => Bus_Data_out_int(15),
       O => \Probe_out_reg_int[15]_i_1_n_0\
     );
-\Probe_out_reg_int[1]_i_1\: unisim.vcomponents.LUT3
+\Probe_out_reg_int[1]_i_1\: unisim.vcomponents.LUT4
     generic map(
-      INIT => X"B8"
+      INIT => X"2F20"
     )
         port map (
       I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_6\,
-      I1 => \^addr_p1_reg[2]_0\(2),
-      I2 => \Probe_out_reg_int[1]_i_2_n_0\,
+      I1 => \^addr_p1_reg[2]_0\(0),
+      I2 => \^addr_p1_reg[2]_0\(2),
+      I3 => \Probe_out_reg_int[1]_i_2_n_0\,
       O => probe_out_mem(1)
     );
 \Probe_out_reg_int[1]_i_2\: unisim.vcomponents.LUT5
@@ -5820,7 +5915,7 @@ Committ_2_reg: unisim.vcomponents.FDRE
     );
 \Probe_out_reg_int[2]_i_1\: unisim.vcomponents.LUT5
     generic map(
-      INIT => X"88B88888"
+      INIT => X"00B80088"
     )
         port map (
       I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_5\,
@@ -5832,7 +5927,7 @@ Committ_2_reg: unisim.vcomponents.FDRE
     );
 \Probe_out_reg_int[3]_i_1\: unisim.vcomponents.LUT5
     generic map(
-      INIT => X"88B88888"
+      INIT => X"00B80088"
     )
         port map (
       I0 => \G_PROBE_OUT[4].PROBE_OUT0_INST_n_4\,
@@ -6614,7 +6709,7 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is
   attribute C_NUM_PROBE_IN : integer;
   attribute C_NUM_PROBE_IN of vio_manual_ctrl_vio_v3_0_20_vio : entity is 0;
   attribute C_NUM_PROBE_OUT : integer;
-  attribute C_NUM_PROBE_OUT of vio_manual_ctrl_vio_v3_0_20_vio : entity is 5;
+  attribute C_NUM_PROBE_OUT of vio_manual_ctrl_vio_v3_0_20_vio : entity is 6;
   attribute C_PIPE_IFACE : integer;
   attribute C_PIPE_IFACE of vio_manual_ctrl_vio_v3_0_20_vio : entity is 0;
   attribute C_PROBE_IN0_WIDTH : integer;
@@ -9200,7 +9295,7 @@ entity vio_manual_ctrl_vio_v3_0_20_vio is
   attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
   attribute LC_TOTAL_PROBE_IN_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 0;
   attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
-  attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 41;
+  attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_manual_ctrl_vio_v3_0_20_vio : entity is 42;
   attribute ORIG_REF_NAME : string;
   attribute ORIG_REF_NAME of vio_manual_ctrl_vio_v3_0_20_vio : entity is "vio_v3_0_20_vio";
   attribute dont_touch : string;
@@ -9212,8 +9307,7 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_vio is
   signal DECODER_INST_n_5 : STD_LOGIC;
   signal DECODER_INST_n_6 : STD_LOGIC;
   signal DECODER_INST_n_7 : STD_LOGIC;
-  signal PROBE_OUT_ALL_INST_n_41 : STD_LOGIC;
-  signal PROBE_OUT_ALL_INST_n_45 : STD_LOGIC;
+  signal PROBE_OUT_ALL_INST_n_42 : STD_LOGIC;
   signal PROBE_OUT_ALL_INST_n_46 : STD_LOGIC;
   signal PROBE_OUT_ALL_INST_n_47 : STD_LOGIC;
   signal PROBE_OUT_ALL_INST_n_48 : STD_LOGIC;
@@ -9229,6 +9323,7 @@ architecture STRUCTURE of vio_manual_ctrl_vio_v3_0_20_vio is
   signal PROBE_OUT_ALL_INST_n_58 : STD_LOGIC;
   signal PROBE_OUT_ALL_INST_n_59 : STD_LOGIC;
   signal PROBE_OUT_ALL_INST_n_60 : STD_LOGIC;
+  signal PROBE_OUT_ALL_INST_n_61 : STD_LOGIC;
   signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
   signal bus_clk : STD_LOGIC;
   attribute DONT_TOUCH_boolean : boolean;
@@ -9475,7 +9570,6 @@ begin
   probe_out47(0) <= \<const0>\;
   probe_out48(0) <= \<const0>\;
   probe_out49(0) <= \<const0>\;
-  probe_out5(0) <= \<const0>\;
   probe_out50(0) <= \<const0>\;
   probe_out51(0) <= \<const0>\;
   probe_out52(0) <= \<const0>\;
@@ -9532,27 +9626,27 @@ begin
   probe_out99(0) <= \<const0>\;
 DECODER_INST: entity work.vio_manual_ctrl_vio_v3_0_20_decoder
      port map (
-      \Bus_data_out_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54,
-      \Bus_data_out_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53,
-      \Bus_data_out_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52,
-      \Bus_data_out_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51,
-      \Bus_data_out_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50,
+      \Bus_data_out_reg[10]_0\ => PROBE_OUT_ALL_INST_n_55,
+      \Bus_data_out_reg[11]_0\ => PROBE_OUT_ALL_INST_n_54,
+      \Bus_data_out_reg[12]_0\ => PROBE_OUT_ALL_INST_n_53,
+      \Bus_data_out_reg[13]_0\ => PROBE_OUT_ALL_INST_n_52,
+      \Bus_data_out_reg[14]_0\ => PROBE_OUT_ALL_INST_n_51,
       \Bus_data_out_reg[15]_0\(15 downto 0) => bus_do(15 downto 0),
-      \Bus_data_out_reg[15]_1\ => PROBE_OUT_ALL_INST_n_49,
+      \Bus_data_out_reg[15]_1\ => PROBE_OUT_ALL_INST_n_50,
       \Bus_data_out_reg[3]_0\(2) => probe_width_int(8),
       \Bus_data_out_reg[3]_0\(1 downto 0) => probe_width_int(1 downto 0),
-      \Bus_data_out_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60,
-      \Bus_data_out_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59,
-      \Bus_data_out_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58,
-      \Bus_data_out_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57,
-      \Bus_data_out_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56,
-      \Bus_data_out_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55,
+      \Bus_data_out_reg[4]_0\ => PROBE_OUT_ALL_INST_n_61,
+      \Bus_data_out_reg[5]_0\ => PROBE_OUT_ALL_INST_n_60,
+      \Bus_data_out_reg[6]_0\ => PROBE_OUT_ALL_INST_n_59,
+      \Bus_data_out_reg[7]_0\ => PROBE_OUT_ALL_INST_n_58,
+      \Bus_data_out_reg[8]_0\ => PROBE_OUT_ALL_INST_n_57,
+      \Bus_data_out_reg[9]_0\ => PROBE_OUT_ALL_INST_n_56,
       \G_PROBE_OUT[0].wr_probe_out[0]_i_3_0\ => DECODER_INST_n_7,
       \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0\ => DECODER_INST_n_5,
-      Q(3) => PROBE_OUT_ALL_INST_n_45,
-      Q(2) => PROBE_OUT_ALL_INST_n_46,
-      Q(1) => PROBE_OUT_ALL_INST_n_47,
-      Q(0) => PROBE_OUT_ALL_INST_n_48,
+      Q(3) => PROBE_OUT_ALL_INST_n_46,
+      Q(2) => PROBE_OUT_ALL_INST_n_47,
+      Q(1) => PROBE_OUT_ALL_INST_n_48,
+      Q(0) => PROBE_OUT_ALL_INST_n_49,
       SR(0) => clear,
       in0 => committ,
       internal_cnt_rst => internal_cnt_rst,
@@ -9573,7 +9667,7 @@ DECODER_INST: entity work.vio_manual_ctrl_vio_v3_0_20_decoder
       \probe_out_modified_reg[15]_0\(2) => \bus_data_int_reg_n_0_[2]\,
       \probe_out_modified_reg[15]_0\(1) => p_0_in,
       \probe_out_modified_reg[15]_0\(0) => \bus_data_int_reg_n_0_[0]\,
-      \rd_en_reg[6]_0\ => PROBE_OUT_ALL_INST_n_41,
+      \rd_en_reg[6]_0\ => PROBE_OUT_ALL_INST_n_42,
       rd_probe_out_width => rd_probe_out_width,
       s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
       s_den_o => bus_den,
@@ -9592,22 +9686,22 @@ PROBE_OUT_ALL_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_all
       \G_PROBE_OUT[0].wr_probe_out_reg[0]_0\ => DECODER_INST_n_7,
       \G_PROBE_OUT[0].wr_probe_out_reg[0]_1\ => DECODER_INST_n_5,
       \G_PROBE_OUT[0].wr_probe_out_reg[0]_2\ => DECODER_INST_n_6,
-      \Probe_out_reg_int_reg[10]_0\ => PROBE_OUT_ALL_INST_n_54,
-      \Probe_out_reg_int_reg[11]_0\ => PROBE_OUT_ALL_INST_n_53,
-      \Probe_out_reg_int_reg[12]_0\ => PROBE_OUT_ALL_INST_n_52,
-      \Probe_out_reg_int_reg[13]_0\ => PROBE_OUT_ALL_INST_n_51,
-      \Probe_out_reg_int_reg[14]_0\ => PROBE_OUT_ALL_INST_n_50,
-      \Probe_out_reg_int_reg[15]_0\ => PROBE_OUT_ALL_INST_n_49,
-      \Probe_out_reg_int_reg[3]_0\(3) => PROBE_OUT_ALL_INST_n_45,
-      \Probe_out_reg_int_reg[3]_0\(2) => PROBE_OUT_ALL_INST_n_46,
-      \Probe_out_reg_int_reg[3]_0\(1) => PROBE_OUT_ALL_INST_n_47,
-      \Probe_out_reg_int_reg[3]_0\(0) => PROBE_OUT_ALL_INST_n_48,
-      \Probe_out_reg_int_reg[4]_0\ => PROBE_OUT_ALL_INST_n_60,
-      \Probe_out_reg_int_reg[5]_0\ => PROBE_OUT_ALL_INST_n_59,
-      \Probe_out_reg_int_reg[6]_0\ => PROBE_OUT_ALL_INST_n_58,
-      \Probe_out_reg_int_reg[7]_0\ => PROBE_OUT_ALL_INST_n_57,
-      \Probe_out_reg_int_reg[8]_0\ => PROBE_OUT_ALL_INST_n_56,
-      \Probe_out_reg_int_reg[9]_0\ => PROBE_OUT_ALL_INST_n_55,
+      \Probe_out_reg_int_reg[10]_0\ => PROBE_OUT_ALL_INST_n_55,
+      \Probe_out_reg_int_reg[11]_0\ => PROBE_OUT_ALL_INST_n_54,
+      \Probe_out_reg_int_reg[12]_0\ => PROBE_OUT_ALL_INST_n_53,
+      \Probe_out_reg_int_reg[13]_0\ => PROBE_OUT_ALL_INST_n_52,
+      \Probe_out_reg_int_reg[14]_0\ => PROBE_OUT_ALL_INST_n_51,
+      \Probe_out_reg_int_reg[15]_0\ => PROBE_OUT_ALL_INST_n_50,
+      \Probe_out_reg_int_reg[3]_0\(3) => PROBE_OUT_ALL_INST_n_46,
+      \Probe_out_reg_int_reg[3]_0\(2) => PROBE_OUT_ALL_INST_n_47,
+      \Probe_out_reg_int_reg[3]_0\(1) => PROBE_OUT_ALL_INST_n_48,
+      \Probe_out_reg_int_reg[3]_0\(0) => PROBE_OUT_ALL_INST_n_49,
+      \Probe_out_reg_int_reg[4]_0\ => PROBE_OUT_ALL_INST_n_61,
+      \Probe_out_reg_int_reg[5]_0\ => PROBE_OUT_ALL_INST_n_60,
+      \Probe_out_reg_int_reg[6]_0\ => PROBE_OUT_ALL_INST_n_59,
+      \Probe_out_reg_int_reg[7]_0\ => PROBE_OUT_ALL_INST_n_58,
+      \Probe_out_reg_int_reg[8]_0\ => PROBE_OUT_ALL_INST_n_57,
+      \Probe_out_reg_int_reg[9]_0\ => PROBE_OUT_ALL_INST_n_56,
       Q(15) => \bus_data_int_reg_n_0_[15]\,
       Q(14) => \bus_data_int_reg_n_0_[14]\,
       Q(13) => \bus_data_int_reg_n_0_[13]\,
@@ -9625,7 +9719,7 @@ PROBE_OUT_ALL_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_all
       Q(1) => p_0_in,
       Q(0) => \bus_data_int_reg_n_0_[0]\,
       SR(0) => clear,
-      \addr_count[1]_i_5\ => PROBE_OUT_ALL_INST_n_41,
+      \addr_count[1]_i_5\ => PROBE_OUT_ALL_INST_n_42,
       \addr_p1_reg[2]_0\(2 downto 0) => xsdb_addr_2_0_p1(2 downto 0),
       clk => clk,
       in0 => committ,
@@ -9636,16 +9730,17 @@ PROBE_OUT_ALL_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_out_all
       probe_out2(31 downto 0) => probe_out2(31 downto 0),
       probe_out3(1 downto 0) => probe_out3(1 downto 0),
       probe_out4(3 downto 0) => probe_out4(3 downto 0),
+      probe_out5(0) => probe_out5(0),
       s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
       s_den_o => bus_den,
       s_dwe_o => bus_dwe
     );
 PROBE_OUT_WIDTH_INST: entity work.vio_manual_ctrl_vio_v3_0_20_probe_width
      port map (
+      CLK => bus_clk,
       Q(2) => probe_width_int(8),
       Q(1 downto 0) => probe_width_int(1 downto 0),
       internal_cnt_rst => internal_cnt_rst,
-      \out\ => bus_clk,
       rd_probe_out_width => rd_probe_out_width,
       s_rst_o => bus_rst
     );
@@ -9802,7 +9897,8 @@ entity vio_manual_ctrl is
     probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
     probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
     probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
+    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
   );
   attribute NotValidForBitStream : boolean;
   attribute NotValidForBitStream of vio_manual_ctrl : entity is true;
@@ -10009,7 +10105,6 @@ architecture STRUCTURE of vio_manual_ctrl is
   signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
-  signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
@@ -10102,7 +10197,7 @@ architecture STRUCTURE of vio_manual_ctrl is
   attribute C_NUM_PROBE_IN : integer;
   attribute C_NUM_PROBE_IN of inst : label is 0;
   attribute C_NUM_PROBE_OUT : integer;
-  attribute C_NUM_PROBE_OUT of inst : label is 5;
+  attribute C_NUM_PROBE_OUT of inst : label is 6;
   attribute C_PIPE_IFACE : integer;
   attribute C_PIPE_IFACE of inst : label is 0;
   attribute C_PROBE_IN0_WIDTH : integer;
@@ -12690,7 +12785,7 @@ architecture STRUCTURE of vio_manual_ctrl is
   attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
   attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 0;
   attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
-  attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 41;
+  attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 42;
   attribute syn_noprune : string;
   attribute syn_noprune of inst : label is "1";
 begin
@@ -13154,7 +13249,7 @@ inst: entity work.vio_manual_ctrl_vio_v3_0_20_vio
       probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
       probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
       probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
-      probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
+      probe_out5(0) => probe_out5(0),
       probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
       probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
       probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
-// Date        : Tue Mar 21 22:54:43 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Mon Apr  3 20:47:45 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
+//               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
 // Design      : vio_manual_ctrl
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7k410tffg900-2
@@ -15,12 +15,13 @@
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
 module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, 
-  probe_out3, probe_out4)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
+  probe_out3, probe_out4, probe_out5)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]" */;
   input clk;
   output [1:0]probe_out0;
   output [0:0]probe_out1;
   output [31:0]probe_out2;
   output [1:0]probe_out3;
   output [3:0]probe_out4;
+  output [0:0]probe_out5;
 endmodule

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
--- Date        : Tue Mar 21 22:54:43 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Mon Apr  3 20:47:45 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
---               D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
+--               /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
 -- Design      : vio_manual_ctrl
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7k410tffg900-2
@@ -19,7 +19,8 @@ entity vio_manual_ctrl is
     probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
     probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
     probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
+    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
   );
 
 end vio_manual_ctrl;
@@ -28,7 +29,7 @@ architecture stub of vio_manual_ctrl is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/README.txt

@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/compile.do

@@ -0,0 +1,27 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+vlib activehdl/blk_mem_gen_v8_4_3
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_3  -v2k5 \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/file_info.txt

@@ -0,0 +1,6 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/rom_hop_data.sh

@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rom_hop_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+rom_hop_data -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_hop_data xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {rom_hop_data.udo}
+
+run -all
+
+endsim
+
+quit -force

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/ies/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/ies/file_info.txt

@@ -0,0 +1,6 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/ies/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/ies/rom_hop_data.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rom_hop_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.rom_hop_data \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/ies/run.f

@@ -0,0 +1,17 @@
+-makelib ies_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/blk_mem_gen_v8_4_3 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/compile.do

@@ -0,0 +1,27 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/blk_mem_gen_v8_4_3
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+vmap blk_mem_gen_v8_4_3 modelsim_lib/msim/blk_mem_gen_v8_4_3
+
+vlog -work xil_defaultlib -64 -incr -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_3 -64 -incr \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 -incr \
+"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/file_info.txt

@@ -0,0 +1,6 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/rom_hop_data.sh

@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rom_hop_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Mentor/CompLib/2019.1.3"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.rom_hop_data xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {rom_hop_data.udo}
+
+run -all
+
+quit -force

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/compile.do

@@ -0,0 +1,27 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/blk_mem_gen_v8_4_3
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3
+
+vlog -work xil_defaultlib -64 -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_3 -64 \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib -64 \
+"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/elaborate.do

@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rom_hop_data xil_defaultlib.glbl -o rom_hop_data_opt

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/file_info.txt

@@ -0,0 +1,6 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/rom_hop_data.sh

@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rom_hop_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib rom_hop_data_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {rom_hop_data.udo}
+
+run -all
+
+quit -force

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/questa/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/compile.do

@@ -0,0 +1,27 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+vlib riviera/blk_mem_gen_v8_4_3
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work blk_mem_gen_v8_4_3  -v2k5 \
+"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/file_info.txt

@@ -0,0 +1,6 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/rom_hop_data.sh

@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rom_hop_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+rom_hop_data -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_hop_data xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {rom_hop_data.udo}
+
+run -all
+
+endsim
+
+quit -force

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/file_info.txt

@@ -0,0 +1,6 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/rom_hop_data.sh

@@ -0,0 +1,234 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rom_hop_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vlogan -work blk_mem_gen_v8_4_3 $vlogan_opts +v2k \
+    "$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+  2>&1 | tee -a vlogan.log
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    "$ref_dir/../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.rom_hop_data xil_defaultlib.glbl -o rom_hop_data_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./rom_hop_data_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/vcs"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key rom_hop_data_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rom_hop_data_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/simulate.do

@@ -0,0 +1,2 @@
+run
+quit

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/file_info.txt

@@ -0,0 +1,6 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/rom_hop_data.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'rom_hop_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.rom_hop_data \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/run.f

@@ -0,0 +1,17 @@
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/blk_mem_gen_v8_4_3 \
+  "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Apr 03 20:42:37 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./rom_hop_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './rom_hop_data.sh' script.
+
+./rom_hop_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./rom_hop_data.sh -noclean_files
+
+For more information on the script, please type './rom_hop_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/cmd.tcl

@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/file_info.txt

@@ -0,0 +1,2 @@
+rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/rom_hop_data.sh

@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : rom_hop_data.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Apr 03 20:42:37 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: rom_hop_data.sh [-help]
+# usage: rom_hop_data.sh [-lib_map_path]
+# usage: rom_hop_data.sh [-noclean_files]
+# usage: rom_hop_data.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xvlog_opts="--relax"
+
+
+# Script info
+echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rom_hop_data xil_defaultlib.rom_hop_data xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim rom_hop_data -key {Behavioral:sim_1:Functional:rom_hop_data} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rom_hop_data.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: rom_hop_data.sh [-help]\n\
+Usage: rom_hop_data.sh [-lib_map_path]\n\
+Usage: rom_hop_data.sh [-reset_run]\n\
+Usage: rom_hop_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/vlog.prj

@@ -0,0 +1,6 @@
+verilog xil_defaultlib  \
+"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023
+# Generated by export_simulation on Mon Apr 03 20:47:27 CST 2023
 #
 ################################################################################
 

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do

@@ -8,11 +8,11 @@ vmap xil_defaultlib activehdl/xil_defaultlib
 vmap xpm activehdl/xpm
 
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
-"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
 "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Mon Apr 03 20:47:27 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
@@ -93,10 +93,9 @@ setup()
 map_setup_file()
 {
   file="library.cfg"
+  lib_map_path=""
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
-  else
-    lib_map_path="D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/activehdl"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023
+# Generated by export_simulation on Mon Apr 03 20:47:27 CST 2023
 #
 ################################################################################
 

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f

@@ -1,9 +1,9 @@
 -makelib ies_lib/xil_defaultlib -sv \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib ies_lib/xpm \
-  "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib ies_lib/xil_defaultlib \
   "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh

@@ -9,8 +9,8 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Tue Mar 21 22:54:16 +0800 2023
-# SW Build 2644227 on Wed Sep  4 09:45:24 MDT 2019
+# Generated by Vivado on Mon Apr 03 20:47:27 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Tue Mar 21 22:54:16 +0800 2023
+# Generated by export_simulation on Mon Apr 03 20:47:27 CST 2023
 #
 ################################################################################
 

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do

@@ -2,13 +2,21 @@ vlib modelsim_lib/work
 vlib modelsim_lib/msim
 
 vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
 
 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+
+vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
 "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \
 
-
 vlog -work xil_defaultlib \
 "glbl.v"
 

projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt

@@ -1,2 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v