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update dl814_k7_coarse; add ad9361 noise data

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in dl814_k7_cal_coarse, change ant_clk to clk_96m, add rx_pre_test to verify nulling algorithm, with the ability to switch rx data between ad9361 data and test data
This commit is contained in:
josh
2023-04-03 21:14:03 +08:00
parent a10e5305e3
commit d2c22dbeb5
221 changed files with 544082 additions and 7333 deletions
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projects/datalink_814/dl814_k7_cal_coarse/project.tcl
+25 -9
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@@ -3,7 +3,7 @@
#
# project.tcl: Tcl script for re-creating project 'project'
#
# Generated by Vivado on Sat Apr 01 17:22:07 CST 2023
# Generated by Vivado on Mon Apr 03 21:10:02 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -37,6 +37,7 @@
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rfcontrl/ila_rfcontrl.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_test/vio_ant_test.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rfcontrl/vio_rfcontrl.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"
@@ -81,6 +82,7 @@
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_test.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_master.v"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_salve.v"
@@ -99,6 +101,7 @@
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/coe/one_hop_data.coe"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc"
# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/testbenches/tb_rx_pre.v"
@@ -182,7 +185,7 @@ set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/Model/2019.1" -objects $obj
set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Mentor/CompLib/2019.1.3" -objects $obj
set_property -name "compxlib.vcs_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/VCS/2019.1" -objects $obj
set_property -name "corecontainer.enable" -value "1" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
@@ -210,15 +213,16 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_simulator" -value "VCS" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "47" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "47" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "47" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "48" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "48" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "48" -objects $obj
set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "47" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "47" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "47" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "48" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "48" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "48" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "29" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "47" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "48" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
@@ -246,6 +250,7 @@ set files [list \
[file normalize "${origin_dir}/ip/ila_rfcontrl/ila_rfcontrl.xci"] \
[file normalize "${origin_dir}/ip/vio_ant_test/vio_ant_test.xci"] \
[file normalize "${origin_dir}/ip/vio_rfcontrl/vio_rfcontrl.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"] \
@@ -290,6 +295,7 @@ set files [list \
[file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_process.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_test.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/spatial_filter.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_master.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_salve.v"] \
@@ -308,6 +314,7 @@ set files [list \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \
[file normalize "${origin_dir}/ip/vio_cal/vio_cal.xci"] \
[file normalize "${origin_dir}/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/coe/one_hop_data.coe"] \
]
add_files -norecurse -fileset $obj $files
@@ -402,6 +409,15 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]