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update dl814_k7_coarse; add ad9361 noise data

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in dl814_k7_cal_coarse, change ant_clk to clk_96m, add rx_pre_test to verify nulling algorithm, with the ability to switch rx data between ad9361 data and test data
This commit is contained in:
josh
2023-04-03 21:14:03 +08:00
parent a10e5305e3
commit d2c22dbeb5
221 changed files with 544082 additions and 7333 deletions
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projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v
+1 -1
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@@ -46,7 +46,7 @@ module accor_mat_formatting
parameter ROW_NUM = 4,
parameter COL_NUM = 4,
parameter DATA_I_WIDTH = 32,
parameter FRAME_HEAD = 32'b01001100011100001111000111001101
parameter FRAME_HEAD = 32'h7E7E7E7E
)
(
// clock & reset
projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_test.v
+472
View File
@@ -0,0 +1,472 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/16 11:18:28
// Design Name:
// Module Name: rx_pre_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rx_pre_test
#(
parameter ADC_DATA_WIDTH = 12,
parameter BYPASS_CAL = 0
)
(
// clock & reset
input sys_clk ,
input sys_clk_4x ,
input sys_rst ,
// calc result
input ad9361_cal_result , // sync to [sys_clk]
input ad9361_cal_valid ,
// output test data
output [ADC_DATA_WIDTH-1:0] rx_ch1_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch1_q , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch2_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch2_q , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch3_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch3_q , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch4_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch4_q , // sync to [sys_clk]
output hop_start_flag // sync to [sys_clk_4x]
);
localparam HOP_CNT_MOD_192M = 192*200;
localparam HOP_CNT_MOD_48M = 48*200;
// [hop_start_flag] generation
wire ad9361_cal_valid_cdc;
xpm_cdc_single #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
) u_ad9361_cal_valid_cdc
(
.dest_out (ad9361_cal_valid_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is
// registered.
.dest_clk (sys_clk_4x ), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (sys_clk ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (ad9361_cal_valid ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
reg [$clog2(HOP_CNT_MOD_192M)-1 : 0] hop_cnt_192m = 'b0;
reg hop_flag = 'b0;
assign hop_start_flag = hop_flag;
always @(posedge sys_clk_4x) begin
if (sys_rst) begin
hop_cnt_192m = 'b0;
hop_flag = 'b0;
end
else if (ad9361_cal_valid_cdc) begin
hop_cnt_192m <= (hop_cnt_192m == HOP_CNT_MOD_192M-1) ? 'b0 : hop_cnt_192m + 1'b1;
hop_flag <= (hop_cnt_192m == 20) ? 1'b1 : 1'b0;
end
else begin
hop_cnt_192m <= 'b0;
hop_flag = 'b0;
end
end
// read rx data
wire hop_flag_cdc;
xpm_cdc_pulse #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output
.RST_USED (1), // DECIMAL; 0=no reset, 1=implement reset
.SIM_ASSERT_CHK (0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
) u_hop_flag_cdc
(
.dest_pulse (hop_flag_cdc ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
// transfer is correctly initiated on src_pulse input. This output is
// combinatorial unless REG_OUTPUT is set to 1.
.dest_clk (sys_clk ), // 1-bit input: Destination clock.
.dest_rst (sys_rst ), // 1-bit input: optional; required when RST_USED = 1
.src_clk (sys_clk_4x ), // 1-bit input: Source clock.
.src_pulse (hop_flag ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
// destination clock domain. The minimum gap between each pulse transfer must be
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
// between the falling edge of a src_pulse to the rising edge of the next
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
// will generate a pulse the size of one dest_clk period in the destination
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
// src_rst and/or dest_rst are asserted.
.src_rst (sys_rst ) // 1-bit input: optional; required when RST_USED = 1
);
reg [$clog2(HOP_CNT_MOD_48M)-1 : 0] hop_cnt_48m = 'b0;
always @(posedge sys_clk) begin
if (sys_rst) begin
hop_cnt_48m <= 2'd2;
end
else if (ad9361_cal_valid) begin
if (hop_flag_cdc) begin
hop_cnt_48m = 2'd2;
end
else begin
hop_cnt_48m <= (hop_cnt_48m == HOP_CNT_MOD_48M-1 || hop_flag_cdc) ? 'b0 : hop_cnt_48m + 1'b1;
end
end
else begin
hop_cnt_48m <= 2'd2;
end
end
wire [95:0] hop_data;
wire [11:0] rom_ch1_i,rom_ch2_i,rom_ch3_i,rom_ch4_i;
wire [11:0] rom_ch1_q,rom_ch2_q,rom_ch3_q,rom_ch4_q;
assign {rom_ch1_i,rom_ch2_i,rom_ch3_i,rom_ch4_i,
rom_ch1_q,rom_ch2_q,rom_ch3_q,rom_ch4_q} = hop_data;
rom_hop_data u_rom_hop_data
(
.clka (sys_clk ), // input wire clka
.addra (hop_cnt_48m), // input wire [13 : 0] addra
.douta (hop_data ) // output wire [95 : 0] douta
);
reg [11:0] rom_ch1_i_buf,rom_ch2_i_buf,rom_ch3_i_buf,rom_ch4_i_buf;
reg [11:0] rom_ch1_q_buf,rom_ch2_q_buf,rom_ch3_q_buf,rom_ch4_q_buf;
assign rx_ch1_i = rom_ch1_i_buf;
assign rx_ch1_q = rom_ch1_q_buf;
assign rx_ch2_i = rom_ch2_i_buf;
assign rx_ch2_q = rom_ch2_q_buf;
assign rx_ch3_i = rom_ch3_i_buf;
assign rx_ch3_q = rom_ch3_q_buf;
assign rx_ch4_i = rom_ch4_i_buf;
assign rx_ch4_q = rom_ch4_q_buf;
always @(posedge sys_clk) begin
if (BYPASS_CAL) begin
rom_ch1_i_buf <= rom_ch1_i;
rom_ch1_q_buf <= rom_ch1_q;
rom_ch2_i_buf <= rom_ch2_i;
rom_ch2_q_buf <= rom_ch2_q;
rom_ch3_i_buf <= rom_ch3_i;
rom_ch3_q_buf <= rom_ch3_q;
rom_ch4_i_buf <= rom_ch4_i;
rom_ch4_q_buf <= rom_ch4_q;
end
else begin
if (ad9361_cal_result) begin
rom_ch1_i_buf <= rom_ch1_i;
rom_ch1_q_buf <= rom_ch1_q;
rom_ch2_i_buf <= -rom_ch2_i;
rom_ch2_q_buf <= -rom_ch2_q;
rom_ch3_i_buf <= -rom_ch3_i;
rom_ch3_q_buf <= -rom_ch3_q;
rom_ch4_i_buf <= rom_ch4_i;
rom_ch4_q_buf <= rom_ch4_q;
end
else begin
rom_ch1_i_buf <= rom_ch1_i;
rom_ch1_q_buf <= rom_ch1_q;
rom_ch2_i_buf <= -rom_ch2_i;
rom_ch2_q_buf <= -rom_ch2_q;
rom_ch3_i_buf <= rom_ch3_i;
rom_ch3_q_buf <= rom_ch3_q;
rom_ch4_i_buf <= -rom_ch4_i;
rom_ch4_q_buf <= -rom_ch4_q;
end
end
end
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/16 15:08:02
// Design Name:
// Module Name: tb_re_pre_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description: testbench for [rx_pre_test]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_re_pre_test;
// reg sys_clk = 1'b1;
// reg sys_clk_4x = 1'b1;
// reg sys_rst = 1'b1;
// reg ad9361_cal_result = 1'b0;
// reg ad9361_cal_valid = 1'b0;
// wire [11:0] rx_ch1_i;
// wire [11:0] rx_ch1_q;
// wire [11:0] rx_ch2_i;
// wire [11:0] rx_ch2_q;
// wire [11:0] rx_ch3_i;
// wire [11:0] rx_ch3_q;
// wire [11:0] rx_ch4_i;
// wire [11:0] rx_ch4_q;
// wire hop_start_flag;
// rx_pre_test u_rx_pre_test
// (
// // clock & reset
// .sys_clk (sys_clk ),
// .sys_clk_4x (sys_clk_4x ),
// .sys_rst (sys_rst ),
// // calc result
// .ad9361_cal_result (ad9361_cal_result ),
// .ad9361_cal_valid (ad9361_cal_valid ),
// // output test data
// .rx_ch1_i (rx_ch1_i ),
// .rx_ch1_q (rx_ch1_q ),
// .rx_ch2_i (rx_ch2_i ),
// .rx_ch2_q (rx_ch2_q ),
// .rx_ch3_i (rx_ch3_i ),
// .rx_ch3_q (rx_ch3_q ),
// .rx_ch4_i (rx_ch4_i ),
// .rx_ch4_q (rx_ch4_q ),
// .hop_start_flag (hop_start_flag )
// );
// // system clock generation
// always begin
// #20 sys_clk = ~sys_clk;
// end
// always begin
// #5 sys_clk_4x = ~sys_clk_4x;
// end
// initial begin
// #102
// sys_rst = 1'b0;
// #100
// ad9361_cal_valid = 1'b1;
// end
// endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/16 15:58:28
// Design Name:
// Module Name: tb_rx_pre_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Co-simulation testbench for [rx_pre_process] and [rx_pre_test]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_rx_pre_test;
// localparam COL_NUM = 4;
// localparam PS_PL_WIDTH = 32;
// localparam FRAME_HEAD = 32'b01001100011100001111000111001101;
// localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
// reg [FRAME_BITS-1 : 0] weight_stream_buf =
// {
// FRAME_HEAD, 32'd40,
// 32'd1681399168, -32'd984290880,
// 32'd1494147072, -32'd1542469120,
// 32'd1531326976, 32'd1443639808,
// 32'd1665626240, 32'd1083120000
// };
// reg sys_clk = 1'b1;
// reg sys_clk_4x = 1'b1;
// reg sys_rst = 1'b1;
// reg clk_96m = 1'b1;
// reg ant_rst = 1'b1;
// reg ad9361_1_cal_start = 'b0;
// wire ad9361_1_cal_done ;
// reg ad9361_2_cal_start = 'b0;
// wire ad9361_2_cal_done ;
// wire ad9361_cal_result ;
// wire ad9361_cal_valid ;
// reg ad9361_recal = 'b0;
// // phase difference of 0 degree
// wire [11:0] rx_ch1_i;
// wire [11:0] rx_ch1_q;
// wire [11:0] rx_ch2_i;
// wire [11:0] rx_ch2_q;
// wire [11:0] rx_ch3_q;
// wire [11:0] rx_ch3_i;
// wire [11:0] rx_ch4_i;
// wire [11:0] rx_ch4_q;
// wire hop_start_flag;
// wire accor_stream_valid;
// wire accor_stream_data;
// wire weight_stream_data;
// wire rx_data_valid;
// wire [11:0] rx_data_i, rx_data_q;
// rx_pre_process #(
// .BYPASS_CAL (1)
// ) u_rx_pre_process
// (
// // clock & reset
// .sys_clk (sys_clk ), // sync to adc data
// .sys_clk_4x (sys_clk_4x ), // sync to physical layer
// .sys_rst (sys_rst ), // sync to [sys_clk]
// .clk_96m (clk_96m ), // sync to c2c data
// .ant_rst (ant_rst ), // sync to [clk_96m]
// // input data interface
// .rx_ch1_i (rx_ch1_i ),
// .rx_ch1_q (rx_ch1_q ),
// .rx_ch2_i (rx_ch2_i ),
// .rx_ch2_q (rx_ch2_q ),
// .rx_ch3_i (rx_ch3_i ),
// .rx_ch3_q (rx_ch3_q ),
// .rx_ch4_i (rx_ch4_i ),
// .rx_ch4_q (rx_ch4_q ),
// // ad9361 calibration interface
// .ad9361_1_cal_start (ad9361_1_cal_start ),
// .ad9361_1_cal_done (ad9361_1_cal_done ),
// .ad9361_2_cal_start (ad9361_2_cal_start ),
// .ad9361_2_cal_done (ad9361_2_cal_done ),
// .ad9361_cal_result (ad9361_cal_result ),
// .ad9361_cal_valid (ad9361_cal_valid ),
// .ad9361_recal (ad9361_recal ),
// // nulling algotithm interface
// .hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
// .accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
// .accor_stream_data (accor_stream_data ), // sync to [clk_96m]
// .weight_stream_data (weight_stream_data ), // sync to [clk_96m]
// .rx_data_valid (rx_data_valid ), // sync to [sys_clk]
// .rx_data_i (rx_data_i ), // sync to [sys_clk]
// .rx_data_q (rx_data_q ) // sync to [sys_clk]
// );
// // temporary test cases
// rx_pre_test #(
// .BYPASS_CAL (1)
// ) u_rx_pre_test
// (
// // clock & reset
// .sys_clk (sys_clk ),
// .sys_clk_4x (sys_clk_4x ),
// .sys_rst (sys_rst ),
// // calc result
// .ad9361_cal_result (ad9361_cal_result ),
// .ad9361_cal_valid (ad9361_cal_valid ),
// // output test data
// .rx_ch1_i (rx_ch1_i ),
// .rx_ch1_q (rx_ch1_q ),
// .rx_ch2_i (rx_ch2_i ),
// .rx_ch2_q (rx_ch2_q ),
// .rx_ch3_i (rx_ch3_i ),
// .rx_ch3_q (rx_ch3_q ),
// .rx_ch4_i (rx_ch4_i ),
// .rx_ch4_q (rx_ch4_q ),
// .hop_start_flag (hop_start_flag )
// );
// // system clock generation
// always begin
// #20 sys_clk = ~sys_clk;
// end
// always begin
// #5 sys_clk_4x = ~sys_clk_4x;
// end
// always begin
// #7;
// clk_96m = ~clk_96m;
// #3;
// end
// initial begin
// #102
// sys_rst = 1'b0;
// ant_rst = 1'b0;
// end
// reg weight_stream_valid = 'b0;
// always @(negedge accor_stream_valid) begin
// #((48*50)*40+18); // 50us of 48M clock
// weight_stream_valid = 'b1;
// #(FRAME_BITS*20);
// weight_stream_valid = 'b0;
// end
// reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
// always @(posedge clk_96m) begin
// if (sys_rst) begin
// weight_stream_cnt <= 'b0;
// end
// else begin
// weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
// end
// end
// assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
// endmodule
projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v
+1 -1
View File
@@ -46,7 +46,7 @@ module weight_vec_formatting
parameter COL_NUM = 4,
parameter WEIGHT_WIDTH = 32,
parameter DATA_O_WIDTH = 16,
parameter FRAME_HEAD = 32'b10110011100011110000111000110010,
parameter FRAME_HEAD = 32'h7E7E7E7E,
parameter FIFO_CDC_DEPTH = 32
)
(
projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v
+92 -29
View File
@@ -404,25 +404,22 @@ wire accor_stream_data;
wire weight_stream_data;
// buffer output data
reg ant_cin_buf = 'b0;
reg ant_din1_buf = 'b0;
reg ant_tr_buf = 'b0;
reg ant_dary_buf = 'b0;
assign ant_cin = ant_cin_buf ;
assign ant_cin = clk_96m ;
assign ant_din1 = ant_din1_buf;
assign ant_tr = ant_tr_buf ;
assign ant_dary = ant_dary_buf;
always @(posedge clk_96m) begin
if (ant_rst) begin
ant_cin_buf <= 'b0;
ant_din1_buf <= 'b0;
ant_tr_buf <= 'b0;
ant_dary_buf <= 'b0;
end
else begin
ant_cin_buf <= rf_clk;
ant_din1_buf <= rf_data | accor_stream_data;
ant_tr_buf <= rf_tr;
ant_dary_buf <= rf_dary;
@@ -590,10 +587,20 @@ tx_qpsk u_tx_qpsk
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// Rx Signals //////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire [11:0] rx_ch1_i, rx_ch1_q;
wire [11:0] rx_ch2_i, rx_ch2_q;
wire [11:0] rx_ch3_i, rx_ch3_q;
wire [11:0] rx_ch4_i, rx_ch4_q;
reg [11:0] rx_ch1_i, rx_ch1_q;
reg [11:0] rx_ch2_i, rx_ch2_q;
reg [11:0] rx_ch3_i, rx_ch3_q;
reg [11:0] rx_ch4_i, rx_ch4_q;
wire [11:0] rx_ch1_i_9361, rx_ch1_q_9361;
wire [11:0] rx_ch2_i_9361, rx_ch2_q_9361;
wire [11:0] rx_ch3_i_9361, rx_ch3_q_9361;
wire [11:0] rx_ch4_i_9361, rx_ch4_q_9361;
wire [11:0] rx_ch1_i_test, rx_ch1_q_test;
wire [11:0] rx_ch2_i_test, rx_ch2_q_test;
wire [11:0] rx_ch3_i_test, rx_ch3_q_test;
wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
wire rx_data_valid;
wire [29:0] rx_data_i, rx_data_q;
@@ -603,7 +610,40 @@ wire accor_stream_valid ;
// wire accor_stream_data ;
// wire weight_stream_data ;
wire [11:0] rx_data;
wire rx_data_sel;
always @(posedge sys_clk) begin
if (sys_rst) begin
rx_ch1_i <= 'b0;
rx_ch2_i <= 'b0;
rx_ch3_i <= 'b0;
rx_ch4_i <= 'b0;
rx_ch1_q <= 'b0;
rx_ch2_q <= 'b0;
rx_ch3_q <= 'b0;
rx_ch4_q <= 'b0;
end
else if (rx_data_sel) begin
rx_ch1_i <= rx_ch1_i_test;
rx_ch2_i <= rx_ch2_i_test;
rx_ch3_i <= rx_ch3_i_test;
rx_ch4_i <= rx_ch4_i_test;
rx_ch1_q <= rx_ch1_q_test;
rx_ch2_q <= rx_ch2_q_test;
rx_ch3_q <= rx_ch3_q_test;
rx_ch4_q <= rx_ch4_q_test;
end
else begin
rx_ch1_i <= rx_ch1_i_9361;
rx_ch2_i <= rx_ch2_i_9361;
rx_ch3_i <= rx_ch3_i_9361;
rx_ch4_i <= rx_ch4_i_9361;
rx_ch1_q <= rx_ch1_q_9361;
rx_ch2_q <= rx_ch2_q_9361;
rx_ch3_q <= rx_ch3_q_9361;
rx_ch4_q <= rx_ch4_q_9361;
end
end
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
(
@@ -617,10 +657,10 @@ ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
.rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i
.rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q
.rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i
.rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q
.rx_ch1_i (rx_ch1_i_9361 ), // output [11:0] rx_ch1_i
.rx_ch1_q (rx_ch1_q_9361 ), // output [11:0] rx_ch1_q
.rx_ch2_i (rx_ch2_i_9361 ), // output [11:0] rx_ch2_i
.rx_ch2_q (rx_ch2_q_9361 ) // output [11:0] rx_ch2_q
);
ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
@@ -635,10 +675,10 @@ ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
.rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i
.rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q
.rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i
.rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q
.rx_ch1_i (rx_ch3_i_9361 ), // output [11:0] rx_ch1_i
.rx_ch1_q (rx_ch3_q_9361 ), // output [11:0] rx_ch1_q
.rx_ch2_i (rx_ch4_i_9361 ), // output [11:0] rx_ch2_i
.rx_ch2_q (rx_ch4_q_9361 ) // output [11:0] rx_ch2_q
);
rx_pre_process #(
@@ -678,6 +718,28 @@ rx_pre_process #(
.rx_data_q (rx_data_q ) // sync to [sys_clk]
);
// temporary test cases
rx_pre_test u_rx_pre_test
(
// clock & reset
.sys_clk (sys_clk ),
.sys_clk_4x (sys_clk_4x ),
.sys_rst (sys_rst ),
// calc result
.ad9361_cal_result (ad9361_cal_result ),
.ad9361_cal_valid (ad9361_cal_valid ),
// output test data
.rx_ch1_i (rx_ch1_i_test ),
.rx_ch1_q (rx_ch1_q_test ),
.rx_ch2_i (rx_ch2_i_test ),
.rx_ch2_q (rx_ch2_q_test ),
.rx_ch3_i (rx_ch3_i_test ),
.rx_ch3_q (rx_ch3_q_test ),
.rx_ch4_i (rx_ch4_i_test ),
.rx_ch4_q (rx_ch4_q_test ),
.hop_start_flag (hop_start_flag )
);
// <--------------------------------------------------------------------------->
// <----------------------- insert receiver logic below ----------------------->
// <--------------------------------------------------------------------------->
@@ -826,17 +888,17 @@ ila_tx u_ila_tx
ila_rx u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_cal_ch4_q ), // input wire [11:0] probe7
.probe8 (rx_data_i ), // input wire [29:0] probe8
.probe9 (rx_data_q ) // input wire [29:0] probe9
.clk (sys_clk ), // input wire clk
.probe0 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (u_rx_pre_process.rx_cal_ch4_q ), // input wire [11:0] probe7
.probe8 (rx_data_i ), // input wire [29:0] probe8
.probe9 (rx_data_q ) // input wire [29:0] probe9
);
ila_cal u_ila_cal
@@ -875,7 +937,8 @@ vio_manual_ctrl u_vio_manual_ctrl
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
.probe_out4 (bb_rshift[3:0] ), // output wire [3 : 0] probe_out4
.probe_out5 (rx_data_sel ) // output wire [0 : 0] probe_out5
);
endmodule