diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo.xcix b/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo.xcix index e4b1c4c2..37336c0d 100644 Binary files a/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo.xcix and b/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo.xcix differ diff --git a/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8.xcix b/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8.xcix index fc96b405..655db689 100644 Binary files a/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8.xcix and b/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8.xcix differ diff --git a/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b.xcix b/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b.xcix index 9407bf16..e324f797 100644 Binary files a/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b.xcix and b/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b.xcix differ diff --git a/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom.xcix b/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom.xcix index 6f527196..d8e5d85c 100644 Binary files a/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom.xcix and b/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom.xcix differ diff --git a/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025.xcix b/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025.xcix index cdc762e2..e321de17 100644 Binary files a/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025.xcix and b/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025.xcix differ diff --git a/projects/datalink_814/dl814_k7_beam/constraints/k7410t_ad9516_2ad9361_timing.xdc b/projects/datalink_814/dl814_k7_beam/constraints/k7410t_ad9516_2ad9361_timing.xdc index e5e036e6..3d9bc3d4 100644 --- a/projects/datalink_814/dl814_k7_beam/constraints/k7410t_ad9516_2ad9361_timing.xdc +++ b/projects/datalink_814/dl814_k7_beam/constraints/k7410t_ad9516_2ad9361_timing.xdc @@ -1,4 +1,4 @@ set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D] set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D] -set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D] +#set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D] set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D] \ No newline at end of file diff --git a/projects/datalink_814/dl814_k7_beam/ip/ad9361_clk_gen.xcix b/projects/datalink_814/dl814_k7_beam/ip/ad9361_clk_gen.xcix index ee6b4b7f..15804a8e 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ip/ad9361_clk_gen.xcix and b/projects/datalink_814/dl814_k7_beam/ip/ad9361_clk_gen.xcix differ diff --git a/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg1.xcix b/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg1.xcix index 4f3c34ac..01effc90 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg1.xcix and b/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg1.xcix differ diff --git a/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg2.xcix b/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg2.xcix index 727f9899..8d4b6918 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg2.xcix and b/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg2.xcix differ diff --git a/projects/datalink_814/dl814_k7_beam/ip/ant_rf_interface/fifo_AntCtrl.xcix b/projects/datalink_814/dl814_k7_beam/ip/ant_rf_interface/fifo_AntCtrl.xcix index 22dc032b..c891bcfe 100644 Binary files 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Binary files a/projects/datalink_814/dl814_k7_beam/ip/vio_rf_rd.xcix and b/projects/datalink_814/dl814_k7_beam/ip/vio_rf_rd.xcix differ diff --git a/projects/datalink_814/dl814_k7_beam/ip/vio_rfcontrl.xcix b/projects/datalink_814/dl814_k7_beam/ip/vio_rfcontrl.xcix index d4e21d04..d2a62747 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ip/vio_rfcontrl.xcix and b/projects/datalink_814/dl814_k7_beam/ip/vio_rfcontrl.xcix differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hdl/system_bd_wrapper.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hdl/system_bd_wrapper.v index 433658cc..8488f3fa 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hdl/system_bd_wrapper.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hdl/system_bd_wrapper.v @@ -1,8 +1,8 @@ //Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- -//Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -//Date : Sun Mar 19 00:32:52 2023 -//Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +//Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +//Date : Wed Mar 22 22:51:50 2023 +//Host : localhost.localdomain running 64-bit unknown //Command : generate_target system_bd_wrapper.bd //Design : system_bd_wrapper //Purpose : IP block netlist diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hw_handoff/system_bd.hwh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hw_handoff/system_bd.hwh index e8617d56..64654b53 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hw_handoff/system_bd.hwh +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hw_handoff/system_bd.hwh @@ -1,5 +1,5 @@  - + @@ -804,22 +804,26 @@ + + + + + + + + + + - - - - - - @@ -840,7 +844,6 @@ - @@ -871,17 +874,11 @@ - - - - - - @@ -902,7 +899,6 @@ - @@ -918,18 +914,11 @@ - - - - - - - @@ -950,7 +939,6 @@ - @@ -981,18 +969,11 @@ - - - - - - - @@ -1013,7 +994,6 @@ - @@ -1025,63 +1005,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1102,7 +1049,6 @@ - @@ -1133,14 +1079,7 @@ - - - - - - - @@ -1161,7 +1100,6 @@ - @@ -1177,36 +1115,22 @@ - - - - - - - - - - - - - - @@ -1214,38 +1138,22 @@ - - - - - - - - - - - - - - - - @@ -1253,38 +1161,22 @@ - - - - - - - - - - - - - - - - @@ -1292,38 +1184,22 @@ - - - - - - - - - - - - - - - - diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.dcp index 64ae6b72..5b6749e2 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.xml index 780ddb76..23dd04f5 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.xml @@ -961,7 +961,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -992,7 +992,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1021,7 +1021,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1041,7 +1041,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1059,7 +1059,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1077,7 +1077,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:55:53 UTC 2023 outputProductCRC @@ -1811,6 +1811,18 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output USED_IN_synthesis xil_defaultlib + + system_bd_axi_gpio_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_axi_gpio_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_axi_gpio_0_sim_netlist.v verilogSource @@ -1825,18 +1837,6 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output USED_IN_single_language xil_defaultlib - - system_bd_axi_gpio_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_axi_gpio_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface to the AXI interface. diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.v index a5824879..9aec1d53 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:11 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_axi_gpio_0 -prefix -// system_bd_axi_gpio_0_ system_bd_axi_gpio_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:53 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.v // Design : system_bd_axi_gpio_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,6 +12,125 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_axi_gpio_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_axi_gpio_0 + (s_axi_aclk, + s_axi_aresetn, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + gpio_io_o, + gpio2_io_i); + (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [8:0]s_axi_awaddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; + (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) output [31:0]gpio_io_o; + (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [31:0]gpio2_io_i; + + wire [31:0]gpio2_io_i; + wire [31:0]gpio_io_o; + wire s_axi_aclk; + wire [8:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire NLW_U0_ip2intc_irpt_UNCONNECTED; + wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED; + wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED; + wire [31:0]NLW_U0_gpio_io_t_UNCONNECTED; + + (* C_ALL_INPUTS = "0" *) + (* C_ALL_INPUTS_2 = "1" *) + (* C_ALL_OUTPUTS = "1" *) + (* C_ALL_OUTPUTS_2 = "0" *) + (* C_DOUT_DEFAULT = "-1" *) + (* C_DOUT_DEFAULT_2 = "0" *) + (* C_FAMILY = "kintex7" *) + (* C_GPIO2_WIDTH = "32" *) + (* C_GPIO_WIDTH = "32" *) + (* C_INTERRUPT_PRESENT = "0" *) + (* C_IS_DUAL = "1" *) + (* C_S_AXI_ADDR_WIDTH = "9" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* C_TRI_DEFAULT = "-1" *) + (* C_TRI_DEFAULT_2 = "-1" *) + (* downgradeipidentifiedwarnings = "yes" *) + (* ip_group = "LOGICORE" *) + system_bd_axi_gpio_0_axi_gpio U0 + (.gpio2_io_i(gpio2_io_i), + .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]), + .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]), + .gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .gpio_io_o(gpio_io_o), + .gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[31:0]), + .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr(s_axi_araddr), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "GPIO_Core" *) module system_bd_axi_gpio_0_GPIO_Core (\Dual.ALLOUT0_ND_G1.READ_REG_GEN[31].reg1_reg , gpio_io_o, @@ -2198,6 +2317,7 @@ module system_bd_axi_gpio_0_GPIO_Core .O(ip2bus_wrack_i)); endmodule +(* ORIG_REF_NAME = "address_decoder" *) module system_bd_axi_gpio_0_address_decoder (\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 , E, @@ -2940,7 +3060,7 @@ endmodule (* C_FAMILY = "kintex7" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "32" *) (* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *) -(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) +(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) module system_bd_axi_gpio_0_axi_gpio (s_axi_aclk, s_axi_aresetn, @@ -3491,6 +3611,7 @@ module system_bd_axi_gpio_0_axi_gpio .R(bus2ip_reset)); endmodule +(* ORIG_REF_NAME = "axi_lite_ipif" *) module system_bd_axi_gpio_0_axi_lite_ipif (bus2ip_reset, Q, @@ -3869,6 +3990,7 @@ module system_bd_axi_gpio_0_axi_lite_ipif .s_axi_wvalid(s_axi_wvalid)); endmodule +(* ORIG_REF_NAME = "cdc_sync" *) module system_bd_axi_gpio_0_cdc_sync (scndry_vect_out, gpio2_io_i, @@ -5387,6 +5509,7 @@ module system_bd_axi_gpio_0_cdc_sync .R(1'b0)); endmodule +(* ORIG_REF_NAME = "pselect_f" *) module system_bd_axi_gpio_0_pselect_f (ce_expnd_i_3, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ); @@ -5422,6 +5545,7 @@ module system_bd_axi_gpio_0_pselect_f__parameterized1 .O(ce_expnd_i_1)); endmodule +(* ORIG_REF_NAME = "slave_attachment" *) module system_bd_axi_gpio_0_slave_attachment (SR, Q, @@ -6412,124 +6536,6 @@ module system_bd_axi_gpio_0_slave_attachment .Q(state[1]), .R(SR)); endmodule - -(* CHECK_LICENSE_TYPE = "system_bd_axi_gpio_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_axi_gpio_0 - (s_axi_aclk, - s_axi_aresetn, - s_axi_awaddr, - s_axi_awvalid, - s_axi_awready, - s_axi_wdata, - s_axi_wstrb, - s_axi_wvalid, - s_axi_wready, - s_axi_bresp, - s_axi_bvalid, - s_axi_bready, - s_axi_araddr, - s_axi_arvalid, - s_axi_arready, - s_axi_rdata, - s_axi_rresp, - s_axi_rvalid, - s_axi_rready, - gpio_io_o, - gpio2_io_i); - (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk; - (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [8:0]s_axi_awaddr; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; - (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; - (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) output [31:0]gpio_io_o; - (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [31:0]gpio2_io_i; - - wire [31:0]gpio2_io_i; - wire [31:0]gpio_io_o; - wire s_axi_aclk; - wire [8:0]s_axi_araddr; - wire s_axi_aresetn; - wire s_axi_arready; - wire s_axi_arvalid; - wire [8:0]s_axi_awaddr; - wire s_axi_awready; - wire s_axi_awvalid; - wire s_axi_bready; - wire [1:0]s_axi_bresp; - wire s_axi_bvalid; - wire [31:0]s_axi_rdata; - wire s_axi_rready; - wire [1:0]s_axi_rresp; - wire s_axi_rvalid; - wire [31:0]s_axi_wdata; - wire s_axi_wready; - wire [3:0]s_axi_wstrb; - wire s_axi_wvalid; - wire NLW_U0_ip2intc_irpt_UNCONNECTED; - wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED; - wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED; - wire [31:0]NLW_U0_gpio_io_t_UNCONNECTED; - - (* C_ALL_INPUTS = "0" *) - (* C_ALL_INPUTS_2 = "1" *) - (* C_ALL_OUTPUTS = "1" *) - (* C_ALL_OUTPUTS_2 = "0" *) - (* C_DOUT_DEFAULT = "-1" *) - (* C_DOUT_DEFAULT_2 = "0" *) - (* C_FAMILY = "kintex7" *) - (* C_GPIO2_WIDTH = "32" *) - (* C_GPIO_WIDTH = "32" *) - (* C_INTERRUPT_PRESENT = "0" *) - (* C_IS_DUAL = "1" *) - (* C_S_AXI_ADDR_WIDTH = "9" *) - (* C_S_AXI_DATA_WIDTH = "32" *) - (* C_TRI_DEFAULT = "-1" *) - (* C_TRI_DEFAULT_2 = "-1" *) - (* downgradeipidentifiedwarnings = "yes" *) - (* ip_group = "LOGICORE" *) - system_bd_axi_gpio_0_axi_gpio U0 - (.gpio2_io_i(gpio2_io_i), - .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]), - .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]), - .gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .gpio_io_o(gpio_io_o), - .gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[31:0]), - .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED), - .s_axi_aclk(s_axi_aclk), - .s_axi_araddr(s_axi_araddr), - .s_axi_aresetn(s_axi_aresetn), - .s_axi_arready(s_axi_arready), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awready(s_axi_awready), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_bready(s_axi_bready), - .s_axi_bresp(s_axi_bresp), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata(s_axi_rdata), - .s_axi_rready(s_axi_rready), - .s_axi_rresp(s_axi_rresp), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_wdata(s_axi_wdata), - .s_axi_wready(s_axi_wready), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wvalid(s_axi_wvalid)); -endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.vhdl index 37b29f39..74eca2f7 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:11 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_axi_gpio_0 -prefix --- system_bd_axi_gpio_0_ system_bd_axi_gpio_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:53 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.vhdl -- Design : system_bd_axi_gpio_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -20,6 +20,8 @@ entity system_bd_axi_gpio_0_cdc_sync is gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_aclk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_gpio_0_cdc_sync : entity is "cdc_sync"; end system_bd_axi_gpio_0_cdc_sync; architecture STRUCTURE of system_bd_axi_gpio_0_cdc_sync is @@ -1925,6 +1927,8 @@ entity system_bd_axi_gpio_0_pselect_f is ce_expnd_i_3 : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_gpio_0_pselect_f : entity is "pselect_f"; end system_bd_axi_gpio_0_pselect_f; architecture STRUCTURE of system_bd_axi_gpio_0_pselect_f is @@ -2055,6 +2059,8 @@ entity system_bd_axi_gpio_0_GPIO_Core is \Dual.gpio2_Data_Out_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_gpio_0_GPIO_Core : entity is "GPIO_Core"; end system_bd_axi_gpio_0_GPIO_Core; architecture STRUCTURE of system_bd_axi_gpio_0_GPIO_Core is @@ -4808,6 +4814,8 @@ entity system_bd_axi_gpio_0_address_decoder is \Dual.ALLOUT0_ND_G1.READ_REG_GEN[0].reg1_reg\ : in STD_LOGIC; \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg\ : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_gpio_0_address_decoder : entity is "address_decoder"; end system_bd_axi_gpio_0_address_decoder; architecture STRUCTURE of system_bd_axi_gpio_0_address_decoder is @@ -5554,6 +5562,8 @@ entity system_bd_axi_gpio_0_slave_attachment is s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_gpio_0_slave_attachment : entity is "slave_attachment"; end system_bd_axi_gpio_0_slave_attachment; architecture STRUCTURE of system_bd_axi_gpio_0_slave_attachment is @@ -6598,6 +6608,8 @@ entity system_bd_axi_gpio_0_axi_lite_ipif is s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_gpio_0_axi_lite_ipif : entity is "axi_lite_ipif"; end system_bd_axi_gpio_0_axi_lite_ipif; architecture STRUCTURE of system_bd_axi_gpio_0_axi_lite_ipif is @@ -6762,6 +6774,8 @@ entity system_bd_axi_gpio_0_axi_gpio is attribute C_TRI_DEFAULT of system_bd_axi_gpio_0_axi_gpio : entity is -1; attribute C_TRI_DEFAULT_2 : integer; attribute C_TRI_DEFAULT_2 of system_bd_axi_gpio_0_axi_gpio : entity is -1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_gpio_0_axi_gpio : entity is "axi_gpio"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_bd_axi_gpio_0_axi_gpio : entity is "yes"; attribute ip_group : string; diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v index c9384363..dce50989 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:11 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix -// system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:53 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v // Design : system_bd_axi_gpio_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl index ba9bd7c4..8f6bf9b9 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:11 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix --- system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:53 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl -- Design : system_bd_axi_gpio_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.dcp index 0428a20c..0076947e 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xml index 60fe5a3c..0c64dbb8 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xml @@ -968,7 +968,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -999,7 +999,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1024,7 +1024,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1044,7 +1044,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1062,7 +1062,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:55:52 UTC 2023 outputProductCRC @@ -2531,6 +2531,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_axi_spi_engine_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_axi_spi_engine_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_axi_spi_engine_0_sim_netlist.v verilogSource @@ -2545,18 +2557,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_axi_spi_engine_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_axi_spi_engine_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - axi_spi_engine_v1_0 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.v index 86dc1f7d..fa3eac62 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:11 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_axi_spi_engine_0 -prefix -// system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:52 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.v // Design : system_bd_axi_spi_engine_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,11 +12,210 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *) +(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_axi_spi_engine_0 + (s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_awprot, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_arprot, + s_axi_rvalid, + s_axi_rready, + s_axi_rresp, + s_axi_rdata, + irq, + spi_clk, + spi_resetn, + cmd_ready, + cmd_valid, + cmd_data, + sdo_data_ready, + sdo_data_valid, + sdo_data, + sdi_data_ready, + sdi_data_valid, + sdi_data, + sync_ready, + sync_valid, + sync_data); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [15:0]s_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *) input [2:0]s_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [15:0]s_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *) input [2:0]s_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]s_axi_rdata; + output irq; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input spi_clk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output spi_resetn; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *) input cmd_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *) output cmd_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *) output [15:0]cmd_data; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *) input sdo_data_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *) output sdo_data_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *) output [7:0]sdo_data; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *) output sdi_data_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *) input sdi_data_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *) input [7:0]sdi_data; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *) output sync_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *) input sync_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *) input [7:0]sync_data; + + wire [15:0]cmd_data; + wire cmd_ready; + wire cmd_valid; + wire irq; + wire s_axi_aclk; + wire [15:0]s_axi_araddr; + wire s_axi_aresetn; + wire [2:0]s_axi_arprot; + wire s_axi_arready; + wire s_axi_arvalid; + wire [15:0]s_axi_awaddr; + wire [2:0]s_axi_awprot; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire [7:0]sdi_data; + wire sdi_data_ready; + wire sdi_data_valid; + wire [7:0]sdo_data; + wire sdo_data_ready; + wire sdo_data_valid; + wire spi_clk; + wire spi_resetn; + wire [7:0]sync_data; + wire sync_ready; + wire sync_valid; + wire NLW_inst_offload0_cmd_wr_en_UNCONNECTED; + wire NLW_inst_offload0_enable_UNCONNECTED; + wire NLW_inst_offload0_mem_reset_UNCONNECTED; + wire NLW_inst_offload0_sdo_wr_en_UNCONNECTED; + wire NLW_inst_offload_sync_ready_UNCONNECTED; + wire NLW_inst_up_rack_UNCONNECTED; + wire NLW_inst_up_wack_UNCONNECTED; + wire [15:0]NLW_inst_offload0_cmd_wr_data_UNCONNECTED; + wire [7:0]NLW_inst_offload0_sdo_wr_data_UNCONNECTED; + wire [31:0]NLW_inst_up_rdata_UNCONNECTED; + + (* ASYNC_SPI_CLK = "1'b0" *) + (* CMD_FIFO_ADDRESS_WIDTH = "4" *) + (* DATA_WIDTH = "16'b0000000000001000" *) + (* ID = "0" *) + (* MM_IF_TYPE = "0" *) + (* NUM_OFFLOAD = "0" *) + (* NUM_OF_SDI = "8'b00000001" *) + (* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *) + (* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *) + (* PCORE_VERSION = "65649" *) + (* SDI_FIFO_ADDRESS_WIDTH = "5" *) + (* SDO_FIFO_ADDRESS_WIDTH = "5" *) + (* SYNC_FIFO_ADDRESS_WIDTH = "4" *) + (* S_AXI = "0" *) + (* UP_FIFO = "1" *) + system_bd_axi_spi_engine_0_axi_spi_engine inst + (.cmd_data(cmd_data), + .cmd_ready(cmd_ready), + .cmd_valid(cmd_valid), + .irq(irq), + .offload0_cmd_wr_data(NLW_inst_offload0_cmd_wr_data_UNCONNECTED[15:0]), + .offload0_cmd_wr_en(NLW_inst_offload0_cmd_wr_en_UNCONNECTED), + .offload0_enable(NLW_inst_offload0_enable_UNCONNECTED), + .offload0_enabled(1'b0), + .offload0_mem_reset(NLW_inst_offload0_mem_reset_UNCONNECTED), + .offload0_sdo_wr_data(NLW_inst_offload0_sdo_wr_data_UNCONNECTED[7:0]), + .offload0_sdo_wr_en(NLW_inst_offload0_sdo_wr_en_UNCONNECTED), + .offload_sync_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .offload_sync_ready(NLW_inst_offload_sync_ready_UNCONNECTED), + .offload_sync_valid(1'b0), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr(s_axi_araddr), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arprot(s_axi_arprot), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awprot(s_axi_awprot), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid), + .sdi_data(sdi_data), + .sdi_data_ready(sdi_data_ready), + .sdi_data_valid(sdi_data_valid), + .sdo_data(sdo_data), + .sdo_data_ready(sdo_data_ready), + .sdo_data_valid(sdo_data_valid), + .spi_clk(spi_clk), + .spi_resetn(spi_resetn), + .sync_data(sync_data), + .sync_ready(sync_ready), + .sync_valid(sync_valid), + .up_clk(1'b0), + .up_rack(NLW_inst_up_rack_UNCONNECTED), + .up_raddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .up_rdata(NLW_inst_up_rdata_UNCONNECTED[31:0]), + .up_rreq(1'b0), + .up_rstn(1'b0), + .up_wack(NLW_inst_up_wack_UNCONNECTED), + .up_waddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .up_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .up_wreq(1'b0)); +endmodule + (* ASYNC_SPI_CLK = "1'b0" *) (* CMD_FIFO_ADDRESS_WIDTH = "4" *) (* DATA_WIDTH = "16'b0000000000001000" *) (* ID = "0" *) (* MM_IF_TYPE = "0" *) (* NUM_OFFLOAD = "0" *) (* NUM_OF_SDI = "8'b00000001" *) (* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *) (* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *) -(* PCORE_VERSION = "65649" *) (* SDI_FIFO_ADDRESS_WIDTH = "5" *) (* SDO_FIFO_ADDRESS_WIDTH = "5" *) -(* SYNC_FIFO_ADDRESS_WIDTH = "4" *) (* S_AXI = "0" *) (* UP_FIFO = "1" *) +(* ORIG_REF_NAME = "axi_spi_engine" *) (* PCORE_VERSION = "65649" *) (* SDI_FIFO_ADDRESS_WIDTH = "5" *) +(* SDO_FIFO_ADDRESS_WIDTH = "5" *) (* SYNC_FIFO_ADDRESS_WIDTH = "4" *) (* S_AXI = "0" *) +(* UP_FIFO = "1" *) module system_bd_axi_spi_engine_0_axi_spi_engine (s_axi_aclk, s_axi_aresetn, @@ -1210,6 +1409,7 @@ module system_bd_axi_spi_engine_0_axi_spi_engine .R(i_up_axi_n_0)); endmodule +(* ORIG_REF_NAME = "fifo_address_sync" *) module system_bd_axi_spi_engine_0_fifo_address_sync (s_axis_ready_reg_0, m_axis_valid_reg_0, @@ -2686,204 +2886,7 @@ module system_bd_axi_spi_engine_0_fifo_address_sync__parameterized0_1 .O(\level_reg[4]_0 )); endmodule -(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *) -(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_axi_spi_engine_0 - (s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_awprot, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_arprot, - s_axi_rvalid, - s_axi_rready, - s_axi_rresp, - s_axi_rdata, - irq, - spi_clk, - spi_resetn, - cmd_ready, - cmd_valid, - cmd_data, - sdo_data_ready, - sdo_data_valid, - sdo_data, - sdi_data_ready, - sdi_data_valid, - sdi_data, - sync_ready, - sync_valid, - sync_data); - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [15:0]s_axi_awaddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *) input [2:0]s_axi_awprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [15:0]s_axi_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *) input [2:0]s_axi_arprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]s_axi_rdata; - output irq; - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input spi_clk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output spi_resetn; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *) input cmd_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *) output cmd_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *) output [15:0]cmd_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *) input sdo_data_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *) output sdo_data_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *) output [7:0]sdo_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *) output sdi_data_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *) input sdi_data_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *) input [7:0]sdi_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *) output sync_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *) input sync_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *) input [7:0]sync_data; - - wire [15:0]cmd_data; - wire cmd_ready; - wire cmd_valid; - wire irq; - wire s_axi_aclk; - wire [15:0]s_axi_araddr; - wire s_axi_aresetn; - wire [2:0]s_axi_arprot; - wire s_axi_arready; - wire s_axi_arvalid; - wire [15:0]s_axi_awaddr; - wire [2:0]s_axi_awprot; - wire s_axi_awready; - wire s_axi_awvalid; - wire s_axi_bready; - wire [1:0]s_axi_bresp; - wire s_axi_bvalid; - wire [31:0]s_axi_rdata; - wire s_axi_rready; - wire [1:0]s_axi_rresp; - wire s_axi_rvalid; - wire [31:0]s_axi_wdata; - wire s_axi_wready; - wire [3:0]s_axi_wstrb; - wire s_axi_wvalid; - wire [7:0]sdi_data; - wire sdi_data_ready; - wire sdi_data_valid; - wire [7:0]sdo_data; - wire sdo_data_ready; - wire sdo_data_valid; - wire spi_clk; - wire spi_resetn; - wire [7:0]sync_data; - wire sync_ready; - wire sync_valid; - wire NLW_inst_offload0_cmd_wr_en_UNCONNECTED; - wire NLW_inst_offload0_enable_UNCONNECTED; - wire NLW_inst_offload0_mem_reset_UNCONNECTED; - wire NLW_inst_offload0_sdo_wr_en_UNCONNECTED; - wire NLW_inst_offload_sync_ready_UNCONNECTED; - wire NLW_inst_up_rack_UNCONNECTED; - wire NLW_inst_up_wack_UNCONNECTED; - wire [15:0]NLW_inst_offload0_cmd_wr_data_UNCONNECTED; - wire [7:0]NLW_inst_offload0_sdo_wr_data_UNCONNECTED; - wire [31:0]NLW_inst_up_rdata_UNCONNECTED; - - (* ASYNC_SPI_CLK = "1'b0" *) - (* CMD_FIFO_ADDRESS_WIDTH = "4" *) - (* DATA_WIDTH = "16'b0000000000001000" *) - (* ID = "0" *) - (* MM_IF_TYPE = "0" *) - (* NUM_OFFLOAD = "0" *) - (* NUM_OF_SDI = "8'b00000001" *) - (* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *) - (* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *) - (* PCORE_VERSION = "65649" *) - (* SDI_FIFO_ADDRESS_WIDTH = "5" *) - (* SDO_FIFO_ADDRESS_WIDTH = "5" *) - (* SYNC_FIFO_ADDRESS_WIDTH = "4" *) - (* S_AXI = "0" *) - (* UP_FIFO = "1" *) - system_bd_axi_spi_engine_0_axi_spi_engine inst - (.cmd_data(cmd_data), - .cmd_ready(cmd_ready), - .cmd_valid(cmd_valid), - .irq(irq), - .offload0_cmd_wr_data(NLW_inst_offload0_cmd_wr_data_UNCONNECTED[15:0]), - .offload0_cmd_wr_en(NLW_inst_offload0_cmd_wr_en_UNCONNECTED), - .offload0_enable(NLW_inst_offload0_enable_UNCONNECTED), - .offload0_enabled(1'b0), - .offload0_mem_reset(NLW_inst_offload0_mem_reset_UNCONNECTED), - .offload0_sdo_wr_data(NLW_inst_offload0_sdo_wr_data_UNCONNECTED[7:0]), - .offload0_sdo_wr_en(NLW_inst_offload0_sdo_wr_en_UNCONNECTED), - .offload_sync_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .offload_sync_ready(NLW_inst_offload_sync_ready_UNCONNECTED), - .offload_sync_valid(1'b0), - .s_axi_aclk(s_axi_aclk), - .s_axi_araddr(s_axi_araddr), - .s_axi_aresetn(s_axi_aresetn), - .s_axi_arprot(s_axi_arprot), - .s_axi_arready(s_axi_arready), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awprot(s_axi_awprot), - .s_axi_awready(s_axi_awready), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_bready(s_axi_bready), - .s_axi_bresp(s_axi_bresp), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata(s_axi_rdata), - .s_axi_rready(s_axi_rready), - .s_axi_rresp(s_axi_rresp), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_wdata(s_axi_wdata), - .s_axi_wready(s_axi_wready), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wvalid(s_axi_wvalid), - .sdi_data(sdi_data), - .sdi_data_ready(sdi_data_ready), - .sdi_data_valid(sdi_data_valid), - .sdo_data(sdo_data), - .sdo_data_ready(sdo_data_ready), - .sdo_data_valid(sdo_data_valid), - .spi_clk(spi_clk), - .spi_resetn(spi_resetn), - .sync_data(sync_data), - .sync_ready(sync_ready), - .sync_valid(sync_valid), - .up_clk(1'b0), - .up_rack(NLW_inst_up_rack_UNCONNECTED), - .up_raddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .up_rdata(NLW_inst_up_rdata_UNCONNECTED[31:0]), - .up_rreq(1'b0), - .up_rstn(1'b0), - .up_wack(NLW_inst_up_wack_UNCONNECTED), - .up_waddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .up_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .up_wreq(1'b0)); -endmodule - +(* ORIG_REF_NAME = "up_axi" *) module system_bd_axi_spi_engine_0_up_axi (s_axi_aresetn_0, up_wreq_s, @@ -5924,6 +5927,7 @@ module system_bd_axi_spi_engine_0_up_axi .R(s_axi_aresetn_0)); endmodule +(* ORIG_REF_NAME = "util_axis_fifo" *) module system_bd_axi_spi_engine_0_util_axis_fifo (s_axis_ready_reg, m_axis_valid_reg, diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.vhdl index 329ccc9c..0e0c71c6 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:11 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_axi_spi_engine_0 -prefix --- system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:52 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.vhdl -- Design : system_bd_axi_spi_engine_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -30,6 +30,8 @@ entity system_bd_axi_spi_engine_0_fifo_address_sync is \level_reg[0]_1\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_fifo_address_sync : entity is "fifo_address_sync"; end system_bd_axi_spi_engine_0_fifo_address_sync; architecture STRUCTURE of system_bd_axi_spi_engine_0_fifo_address_sync is @@ -2061,6 +2063,8 @@ entity system_bd_axi_spi_engine_0_up_axi is s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_up_axi : entity is "up_axi"; end system_bd_axi_spi_engine_0_up_axi; architecture STRUCTURE of system_bd_axi_spi_engine_0_up_axi is @@ -5816,6 +5820,8 @@ entity system_bd_axi_spi_engine_0_util_axis_fifo is s_mem_write : in STD_LOGIC; offload0_cmd_wr_data : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_util_axis_fifo : entity is "util_axis_fifo"; end system_bd_axi_spi_engine_0_util_axis_fifo; architecture STRUCTURE of system_bd_axi_spi_engine_0_util_axis_fifo is @@ -6346,6 +6352,8 @@ entity system_bd_axi_spi_engine_0_axi_spi_engine is attribute OFFLOAD0_CMD_MEM_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_axi_spi_engine : entity is 4; attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH : integer; attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_axi_spi_engine : entity is 4; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_axi_spi_engine : entity is "axi_spi_engine"; attribute PCORE_VERSION : integer; attribute PCORE_VERSION of system_bd_axi_spi_engine_0_axi_spi_engine : entity is 65649; attribute SDI_FIFO_ADDRESS_WIDTH : integer; diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v index 9cd8f745..edce201f 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:11 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix -// system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:52 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v // Design : system_bd_axi_spi_engine_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl index c1c562fb..10f131bd 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:11 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix --- system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:52 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl -- Design : system_bd_axi_spi_engine_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.dcp index daa72cd8..1b2eba36 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.xml index c8e48f9d..f6525f71 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.xml @@ -1168,7 +1168,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:52 UTC 2023 outputProductCRC @@ -1198,7 +1198,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:52 UTC 2023 outputProductCRC @@ -1217,7 +1217,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:52 UTC 2023 outputProductCRC @@ -1236,7 +1236,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:52 UTC 2023 outputProductCRC @@ -1254,7 +1254,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:52 UTC 2023 outputProductCRC @@ -1272,7 +1272,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:55:50 UTC 2023 outputProductCRC @@ -3714,6 +3714,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_clk_wiz_25M_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_clk_wiz_25M_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_clk_wiz_25M_0_sim_netlist.v verilogSource @@ -3728,18 +3740,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_clk_wiz_25M_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_clk_wiz_25M_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.v index f64cacb6..5ca959eb 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_clk_wiz_25M_0 -prefix -// system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:50 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.v // Design : system_bd_clk_wiz_25M_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -31,6 +31,7 @@ module system_bd_clk_wiz_25M_0 .locked(locked)); endmodule +(* ORIG_REF_NAME = "system_bd_clk_wiz_25M_0_clk_wiz" *) module system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz (clk_out1, locked, diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.vhdl index f9972ddf..e56cbcfa 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_clk_wiz_25M_0 -prefix --- system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:50 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.vhdl -- Design : system_bd_clk_wiz_25M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -20,6 +20,8 @@ entity system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz is locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz : entity is "system_bd_clk_wiz_25M_0_clk_wiz"; end system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz; architecture STRUCTURE of system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz is diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v index b8c26de6..bf690b58 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix -// system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:50 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v // Design : system_bd_clk_wiz_25M_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl index d0906c5b..9c401e57 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix --- system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:50 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl -- Design : system_bd_clk_wiz_25M_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.dcp index 2cff9396..bfc5bb47 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xml index b900c8d7..407d7938 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xml @@ -1891,7 +1891,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -1909,7 +1909,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -1929,7 +1929,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -1949,7 +1949,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -1969,7 +1969,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -1987,7 +1987,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:55:51 UTC 2023 outputProductCRC @@ -3858,6 +3858,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_dlmb_bram_if_cntlr_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_dlmb_bram_if_cntlr_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v verilogSource @@ -3872,18 +3884,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_dlmb_bram_if_cntlr_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_dlmb_bram_if_cntlr_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v index a0fb26a1..cab1e58e 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:09 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix -// system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:51 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v // Design : system_bd_dlmb_bram_if_cntlr_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,6 +12,200 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_dlmb_bram_if_cntlr_0 + (LMB_Clk, + LMB_Rst, + LMB_ABus, + LMB_WriteDBus, + LMB_AddrStrobe, + LMB_ReadStrobe, + LMB_WriteStrobe, + LMB_BE, + Sl_DBus, + Sl_Ready, + Sl_Wait, + Sl_UE, + Sl_CE, + BRAM_Rst_A, + BRAM_Clk_A, + BRAM_Addr_A, + BRAM_EN_A, + BRAM_WEN_A, + BRAM_Dout_A, + BRAM_Din_A); + (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A; + + wire [0:31]BRAM_Addr_A; + wire BRAM_Clk_A; + wire [0:31]BRAM_Din_A; + wire [0:31]BRAM_Dout_A; + wire BRAM_EN_A; + wire BRAM_Rst_A; + wire [0:3]BRAM_WEN_A; + wire [0:31]LMB_ABus; + wire LMB_AddrStrobe; + wire [0:3]LMB_BE; + wire LMB_Clk; + wire LMB_ReadStrobe; + wire LMB_Rst; + wire [0:31]LMB_WriteDBus; + wire LMB_WriteStrobe; + wire Sl_CE; + wire [0:31]Sl_DBus; + wire Sl_Ready; + wire Sl_UE; + wire Sl_Wait; + wire NLW_U0_CE_UNCONNECTED; + wire NLW_U0_Interrupt_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED; + wire NLW_U0_Sl1_CE_UNCONNECTED; + wire NLW_U0_Sl1_Ready_UNCONNECTED; + wire NLW_U0_Sl1_UE_UNCONNECTED; + wire NLW_U0_Sl1_Wait_UNCONNECTED; + wire NLW_U0_Sl2_CE_UNCONNECTED; + wire NLW_U0_Sl2_Ready_UNCONNECTED; + wire NLW_U0_Sl2_UE_UNCONNECTED; + wire NLW_U0_Sl2_Wait_UNCONNECTED; + wire NLW_U0_Sl3_CE_UNCONNECTED; + wire NLW_U0_Sl3_Ready_UNCONNECTED; + wire NLW_U0_Sl3_UE_UNCONNECTED; + wire NLW_U0_Sl3_Wait_UNCONNECTED; + wire NLW_U0_UE_UNCONNECTED; + wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED; + wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED; + wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED; + wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED; + wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED; + wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED; + + (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* C_BRAM_AWIDTH = "32" *) + (* C_CE_COUNTER_WIDTH = "0" *) + (* C_CE_FAILING_REGISTERS = "0" *) + (* C_ECC = "0" *) + (* C_ECC_ONOFF_REGISTER = "0" *) + (* C_ECC_ONOFF_RESET_VALUE = "1" *) + (* C_ECC_STATUS_REGISTERS = "0" *) + (* C_FAMILY = "kintex7" *) + (* C_FAULT_INJECT = "0" *) + (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *) + (* C_INTERCONNECT = "0" *) + (* C_LMB_AWIDTH = "32" *) + (* C_LMB_DWIDTH = "32" *) + (* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *) + (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) + (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) + (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) + (* C_NUM_LMB = "1" *) + (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) + (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *) + (* C_S_AXI_CTRL_DATA_WIDTH = "32" *) + (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) + (* C_UE_FAILING_REGISTERS = "0" *) + (* C_WRITE_ACCESS = "2" *) + system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0 + (.BRAM_Addr_A(BRAM_Addr_A), + .BRAM_Clk_A(BRAM_Clk_A), + .BRAM_Din_A(BRAM_Din_A), + .BRAM_Dout_A(BRAM_Dout_A), + .BRAM_EN_A(BRAM_EN_A), + .BRAM_Rst_A(BRAM_Rst_A), + .BRAM_WEN_A(BRAM_WEN_A), + .CE(NLW_U0_CE_UNCONNECTED), + .Interrupt(NLW_U0_Interrupt_UNCONNECTED), + .LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB1_AddrStrobe(1'b0), + .LMB1_BE({1'b0,1'b0,1'b0,1'b0}), + .LMB1_ReadStrobe(1'b0), + .LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB1_WriteStrobe(1'b0), + .LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB2_AddrStrobe(1'b0), + .LMB2_BE({1'b0,1'b0,1'b0,1'b0}), + .LMB2_ReadStrobe(1'b0), + .LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB2_WriteStrobe(1'b0), + .LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB3_AddrStrobe(1'b0), + .LMB3_BE({1'b0,1'b0,1'b0,1'b0}), + .LMB3_ReadStrobe(1'b0), + .LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB3_WriteStrobe(1'b0), + .LMB_ABus(LMB_ABus), + .LMB_AddrStrobe(LMB_AddrStrobe), + .LMB_BE(LMB_BE), + .LMB_Clk(LMB_Clk), + .LMB_ReadStrobe(LMB_ReadStrobe), + .LMB_Rst(LMB_Rst), + .LMB_WriteDBus(LMB_WriteDBus), + .LMB_WriteStrobe(LMB_WriteStrobe), + .S_AXI_CTRL_ACLK(1'b0), + .S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_ARESETN(1'b0), + .S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED), + .S_AXI_CTRL_ARVALID(1'b0), + .S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED), + .S_AXI_CTRL_AWVALID(1'b0), + .S_AXI_CTRL_BREADY(1'b0), + .S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]), + .S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED), + .S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]), + .S_AXI_CTRL_RREADY(1'b0), + .S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]), + .S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED), + .S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED), + .S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_WVALID(1'b0), + .Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED), + .Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]), + .Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED), + .Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED), + .Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED), + .Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED), + .Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]), + .Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED), + .Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED), + .Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED), + .Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED), + .Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]), + .Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED), + .Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED), + .Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED), + .Sl_CE(Sl_CE), + .Sl_DBus(Sl_DBus), + .Sl_Ready(Sl_Ready), + .Sl_UE(Sl_UE), + .Sl_Wait(Sl_Wait), + .UE(NLW_U0_UE_UNCONNECTED)); +endmodule + (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *) (* C_CE_COUNTER_WIDTH = "0" *) (* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *) (* C_ECC_ONOFF_REGISTER = "0" *) (* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *) (* C_FAMILY = "kintex7" *) @@ -20,7 +214,7 @@ (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *) (* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *) -(* C_WRITE_ACCESS = "2" *) +(* C_WRITE_ACCESS = "2" *) (* ORIG_REF_NAME = "lmb_bram_if_cntlr" *) module system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr (LMB_Clk, LMB_Rst, @@ -417,200 +611,6 @@ module system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr .I1(lmb_as), .O(Sl_Ready)); endmodule - -(* CHECK_LICENSE_TYPE = "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_dlmb_bram_if_cntlr_0 - (LMB_Clk, - LMB_Rst, - LMB_ABus, - LMB_WriteDBus, - LMB_AddrStrobe, - LMB_ReadStrobe, - LMB_WriteStrobe, - LMB_BE, - Sl_DBus, - Sl_Ready, - Sl_Wait, - Sl_UE, - Sl_CE, - BRAM_Rst_A, - BRAM_Clk_A, - BRAM_Addr_A, - BRAM_EN_A, - BRAM_WEN_A, - BRAM_Dout_A, - BRAM_Din_A); - (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk; - (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A; - - wire [0:31]BRAM_Addr_A; - wire BRAM_Clk_A; - wire [0:31]BRAM_Din_A; - wire [0:31]BRAM_Dout_A; - wire BRAM_EN_A; - wire BRAM_Rst_A; - wire [0:3]BRAM_WEN_A; - wire [0:31]LMB_ABus; - wire LMB_AddrStrobe; - wire [0:3]LMB_BE; - wire LMB_Clk; - wire LMB_ReadStrobe; - wire LMB_Rst; - wire [0:31]LMB_WriteDBus; - wire LMB_WriteStrobe; - wire Sl_CE; - wire [0:31]Sl_DBus; - wire Sl_Ready; - wire Sl_UE; - wire Sl_Wait; - wire NLW_U0_CE_UNCONNECTED; - wire NLW_U0_Interrupt_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED; - wire NLW_U0_Sl1_CE_UNCONNECTED; - wire NLW_U0_Sl1_Ready_UNCONNECTED; - wire NLW_U0_Sl1_UE_UNCONNECTED; - wire NLW_U0_Sl1_Wait_UNCONNECTED; - wire NLW_U0_Sl2_CE_UNCONNECTED; - wire NLW_U0_Sl2_Ready_UNCONNECTED; - wire NLW_U0_Sl2_UE_UNCONNECTED; - wire NLW_U0_Sl2_Wait_UNCONNECTED; - wire NLW_U0_Sl3_CE_UNCONNECTED; - wire NLW_U0_Sl3_Ready_UNCONNECTED; - wire NLW_U0_Sl3_UE_UNCONNECTED; - wire NLW_U0_Sl3_Wait_UNCONNECTED; - wire NLW_U0_UE_UNCONNECTED; - wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED; - wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED; - wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED; - wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED; - wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED; - wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED; - - (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) - (* C_BRAM_AWIDTH = "32" *) - (* C_CE_COUNTER_WIDTH = "0" *) - (* C_CE_FAILING_REGISTERS = "0" *) - (* C_ECC = "0" *) - (* C_ECC_ONOFF_REGISTER = "0" *) - (* C_ECC_ONOFF_RESET_VALUE = "1" *) - (* C_ECC_STATUS_REGISTERS = "0" *) - (* C_FAMILY = "kintex7" *) - (* C_FAULT_INJECT = "0" *) - (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *) - (* C_INTERCONNECT = "0" *) - (* C_LMB_AWIDTH = "32" *) - (* C_LMB_DWIDTH = "32" *) - (* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *) - (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) - (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) - (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) - (* C_NUM_LMB = "1" *) - (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) - (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *) - (* C_S_AXI_CTRL_DATA_WIDTH = "32" *) - (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) - (* C_UE_FAILING_REGISTERS = "0" *) - (* C_WRITE_ACCESS = "2" *) - system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0 - (.BRAM_Addr_A(BRAM_Addr_A), - .BRAM_Clk_A(BRAM_Clk_A), - .BRAM_Din_A(BRAM_Din_A), - .BRAM_Dout_A(BRAM_Dout_A), - .BRAM_EN_A(BRAM_EN_A), - .BRAM_Rst_A(BRAM_Rst_A), - .BRAM_WEN_A(BRAM_WEN_A), - .CE(NLW_U0_CE_UNCONNECTED), - .Interrupt(NLW_U0_Interrupt_UNCONNECTED), - .LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB1_AddrStrobe(1'b0), - .LMB1_BE({1'b0,1'b0,1'b0,1'b0}), - .LMB1_ReadStrobe(1'b0), - .LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB1_WriteStrobe(1'b0), - .LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB2_AddrStrobe(1'b0), - .LMB2_BE({1'b0,1'b0,1'b0,1'b0}), - .LMB2_ReadStrobe(1'b0), - .LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB2_WriteStrobe(1'b0), - .LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB3_AddrStrobe(1'b0), - .LMB3_BE({1'b0,1'b0,1'b0,1'b0}), - .LMB3_ReadStrobe(1'b0), - .LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB3_WriteStrobe(1'b0), - .LMB_ABus(LMB_ABus), - .LMB_AddrStrobe(LMB_AddrStrobe), - .LMB_BE(LMB_BE), - .LMB_Clk(LMB_Clk), - .LMB_ReadStrobe(LMB_ReadStrobe), - .LMB_Rst(LMB_Rst), - .LMB_WriteDBus(LMB_WriteDBus), - .LMB_WriteStrobe(LMB_WriteStrobe), - .S_AXI_CTRL_ACLK(1'b0), - .S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_ARESETN(1'b0), - .S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED), - .S_AXI_CTRL_ARVALID(1'b0), - .S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED), - .S_AXI_CTRL_AWVALID(1'b0), - .S_AXI_CTRL_BREADY(1'b0), - .S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]), - .S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED), - .S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]), - .S_AXI_CTRL_RREADY(1'b0), - .S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]), - .S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED), - .S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED), - .S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_WVALID(1'b0), - .Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED), - .Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]), - .Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED), - .Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED), - .Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED), - .Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED), - .Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]), - .Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED), - .Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED), - .Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED), - .Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED), - .Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]), - .Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED), - .Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED), - .Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED), - .Sl_CE(Sl_CE), - .Sl_DBus(Sl_DBus), - .Sl_Ready(Sl_Ready), - .Sl_UE(Sl_UE), - .Sl_Wait(Sl_Wait), - .UE(NLW_U0_UE_UNCONNECTED)); -endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl index 2c15456d..4398d259 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:09 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix --- system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:51 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl -- Design : system_bd_dlmb_bram_if_cntlr_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -142,6 +142,8 @@ entity system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is attribute C_UE_FAILING_REGISTERS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0; attribute C_WRITE_ACCESS : integer; attribute C_WRITE_ACCESS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr"; end system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr; architecture STRUCTURE of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v index 09cc8c6e..884a9d71 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:09 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix -// system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:51 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v // Design : system_bd_dlmb_bram_if_cntlr_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl index 5d1cdc9a..fcbb4e85 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:09 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix --- system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:51 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl -- Design : system_bd_dlmb_bram_if_cntlr_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.dcp index 9b708cea..f9621bc4 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xml index e877c15f..5609ab0e 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xml @@ -2867,7 +2867,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2885,7 +2885,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2905,7 +2905,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2925,7 +2925,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2945,7 +2945,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2963,7 +2963,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:56:13 UTC 2023 outputProductCRC @@ -3456,6 +3456,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_dlmb_v10_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_dlmb_v10_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_dlmb_v10_0_sim_netlist.v verilogSource @@ -3470,18 +3482,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_dlmb_v10_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_dlmb_v10_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.v index 64dee265..207490c9 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_dlmb_v10_0 -prefix -// system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:13 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.v // Design : system_bd_dlmb_v10_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,98 +12,6 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps -(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *) -(* C_LMB_NUM_SLAVES = "1" *) -module system_bd_dlmb_v10_0_lmb_v10 - (LMB_Clk, - SYS_Rst, - LMB_Rst, - M_ABus, - M_ReadStrobe, - M_WriteStrobe, - M_AddrStrobe, - M_DBus, - M_BE, - Sl_DBus, - Sl_Ready, - Sl_Wait, - Sl_UE, - Sl_CE, - LMB_ABus, - LMB_ReadStrobe, - LMB_WriteStrobe, - LMB_AddrStrobe, - LMB_ReadDBus, - LMB_WriteDBus, - LMB_Ready, - LMB_Wait, - LMB_UE, - LMB_CE, - LMB_BE); - input LMB_Clk; - input SYS_Rst; - output LMB_Rst; - input [0:31]M_ABus; - input M_ReadStrobe; - input M_WriteStrobe; - input M_AddrStrobe; - input [0:31]M_DBus; - input [0:3]M_BE; - input [0:31]Sl_DBus; - input [0:0]Sl_Ready; - input [0:0]Sl_Wait; - input [0:0]Sl_UE; - input [0:0]Sl_CE; - output [0:31]LMB_ABus; - output LMB_ReadStrobe; - output LMB_WriteStrobe; - output LMB_AddrStrobe; - output [0:31]LMB_ReadDBus; - output [0:31]LMB_WriteDBus; - output LMB_Ready; - output LMB_Wait; - output LMB_UE; - output LMB_CE; - output [0:3]LMB_BE; - - wire LMB_Clk; - wire LMB_Rst; - wire [0:31]M_ABus; - wire M_AddrStrobe; - wire [0:3]M_BE; - wire [0:31]M_DBus; - wire M_ReadStrobe; - wire M_WriteStrobe; - wire SYS_Rst; - wire [0:0]Sl_CE; - wire [0:31]Sl_DBus; - wire [0:0]Sl_Ready; - wire [0:0]Sl_UE; - wire [0:0]Sl_Wait; - - assign LMB_ABus[0:31] = M_ABus; - assign LMB_AddrStrobe = M_AddrStrobe; - assign LMB_BE[0:3] = M_BE; - assign LMB_CE = Sl_CE; - assign LMB_ReadDBus[0:31] = Sl_DBus; - assign LMB_ReadStrobe = M_ReadStrobe; - assign LMB_Ready = Sl_Ready; - assign LMB_UE = Sl_UE; - assign LMB_Wait = Sl_Wait; - assign LMB_WriteDBus[0:31] = M_DBus; - assign LMB_WriteStrobe = M_WriteStrobe; - (* BOX_TYPE = "PRIMITIVE" *) - (* XILINX_LEGACY_PRIM = "FDS" *) - FDSE #( - .INIT(1'b1)) - POR_FF_I - (.C(LMB_Clk), - .CE(1'b1), - .D(1'b0), - .Q(LMB_Rst), - .S(SYS_Rst)); -endmodule - (* CHECK_LICENSE_TYPE = "system_bd_dlmb_v10_0,lmb_v10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_v10,Vivado 2019.1.3" *) (* NotValidForBitStream *) module system_bd_dlmb_v10_0 @@ -215,6 +123,98 @@ module system_bd_dlmb_v10_0 .Sl_UE(Sl_UE), .Sl_Wait(Sl_Wait)); endmodule + +(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *) +(* C_LMB_NUM_SLAVES = "1" *) (* ORIG_REF_NAME = "lmb_v10" *) +module system_bd_dlmb_v10_0_lmb_v10 + (LMB_Clk, + SYS_Rst, + LMB_Rst, + M_ABus, + M_ReadStrobe, + M_WriteStrobe, + M_AddrStrobe, + M_DBus, + M_BE, + Sl_DBus, + Sl_Ready, + Sl_Wait, + Sl_UE, + Sl_CE, + LMB_ABus, + LMB_ReadStrobe, + LMB_WriteStrobe, + LMB_AddrStrobe, + LMB_ReadDBus, + LMB_WriteDBus, + LMB_Ready, + LMB_Wait, + LMB_UE, + LMB_CE, + LMB_BE); + input LMB_Clk; + input SYS_Rst; + output LMB_Rst; + input [0:31]M_ABus; + input M_ReadStrobe; + input M_WriteStrobe; + input M_AddrStrobe; + input [0:31]M_DBus; + input [0:3]M_BE; + input [0:31]Sl_DBus; + input [0:0]Sl_Ready; + input [0:0]Sl_Wait; + input [0:0]Sl_UE; + input [0:0]Sl_CE; + output [0:31]LMB_ABus; + output LMB_ReadStrobe; + output LMB_WriteStrobe; + output LMB_AddrStrobe; + output [0:31]LMB_ReadDBus; + output [0:31]LMB_WriteDBus; + output LMB_Ready; + output LMB_Wait; + output LMB_UE; + output LMB_CE; + output [0:3]LMB_BE; + + wire LMB_Clk; + wire LMB_Rst; + wire [0:31]M_ABus; + wire M_AddrStrobe; + wire [0:3]M_BE; + wire [0:31]M_DBus; + wire M_ReadStrobe; + wire M_WriteStrobe; + wire SYS_Rst; + wire [0:0]Sl_CE; + wire [0:31]Sl_DBus; + wire [0:0]Sl_Ready; + wire [0:0]Sl_UE; + wire [0:0]Sl_Wait; + + assign LMB_ABus[0:31] = M_ABus; + assign LMB_AddrStrobe = M_AddrStrobe; + assign LMB_BE[0:3] = M_BE; + assign LMB_CE = Sl_CE; + assign LMB_ReadDBus[0:31] = Sl_DBus; + assign LMB_ReadStrobe = M_ReadStrobe; + assign LMB_Ready = Sl_Ready; + assign LMB_UE = Sl_UE; + assign LMB_Wait = Sl_Wait; + assign LMB_WriteDBus[0:31] = M_DBus; + assign LMB_WriteStrobe = M_WriteStrobe; + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDS" *) + FDSE #( + .INIT(1'b1)) + POR_FF_I + (.C(LMB_Clk), + .CE(1'b1), + .D(1'b0), + .Q(LMB_Rst), + .S(SYS_Rst)); +endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.vhdl index 0252f6a3..ebdc2b82 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_dlmb_v10_0 -prefix --- system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:13 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.vhdl -- Design : system_bd_dlmb_v10_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -50,6 +50,8 @@ entity system_bd_dlmb_v10_0_lmb_v10 is attribute C_LMB_DWIDTH of system_bd_dlmb_v10_0_lmb_v10 : entity is 32; attribute C_LMB_NUM_SLAVES : integer; attribute C_LMB_NUM_SLAVES of system_bd_dlmb_v10_0_lmb_v10 : entity is 1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_dlmb_v10_0_lmb_v10 : entity is "lmb_v10"; end system_bd_dlmb_v10_0_lmb_v10; architecture STRUCTURE of system_bd_dlmb_v10_0_lmb_v10 is diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v index d33e7d00..13066e74 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix -// system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:13 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v // Design : system_bd_dlmb_v10_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl index d8c076cf..44f842fa 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix --- system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:13 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl -- Design : system_bd_dlmb_v10_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.dcp index e4eecd85..97337fbd 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xml index 43d05e67..39a67155 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xml @@ -1891,7 +1891,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -1909,7 +1909,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -1929,7 +1929,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -1949,7 +1949,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -1969,7 +1969,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -1987,7 +1987,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:56:13 UTC 2023 outputProductCRC @@ -3858,6 +3858,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_ilmb_bram_if_cntlr_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_ilmb_bram_if_cntlr_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v verilogSource @@ -3872,18 +3884,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_ilmb_bram_if_cntlr_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_ilmb_bram_if_cntlr_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v index 59ebe15c..a8d7a316 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix -// system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:13 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v // Design : system_bd_ilmb_bram_if_cntlr_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,6 +12,200 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_ilmb_bram_if_cntlr_0 + (LMB_Clk, + LMB_Rst, + LMB_ABus, + LMB_WriteDBus, + LMB_AddrStrobe, + LMB_ReadStrobe, + LMB_WriteStrobe, + LMB_BE, + Sl_DBus, + Sl_Ready, + Sl_Wait, + Sl_UE, + Sl_CE, + BRAM_Rst_A, + BRAM_Clk_A, + BRAM_Addr_A, + BRAM_EN_A, + BRAM_WEN_A, + BRAM_Dout_A, + BRAM_Din_A); + (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE; + (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A; + (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A; + + wire [0:31]BRAM_Addr_A; + wire BRAM_Clk_A; + wire [0:31]BRAM_Din_A; + wire [0:31]BRAM_Dout_A; + wire BRAM_EN_A; + wire BRAM_Rst_A; + wire [0:3]BRAM_WEN_A; + wire [0:31]LMB_ABus; + wire LMB_AddrStrobe; + wire [0:3]LMB_BE; + wire LMB_Clk; + wire LMB_ReadStrobe; + wire LMB_Rst; + wire [0:31]LMB_WriteDBus; + wire LMB_WriteStrobe; + wire Sl_CE; + wire [0:31]Sl_DBus; + wire Sl_Ready; + wire Sl_UE; + wire Sl_Wait; + wire NLW_U0_CE_UNCONNECTED; + wire NLW_U0_Interrupt_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED; + wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED; + wire NLW_U0_Sl1_CE_UNCONNECTED; + wire NLW_U0_Sl1_Ready_UNCONNECTED; + wire NLW_U0_Sl1_UE_UNCONNECTED; + wire NLW_U0_Sl1_Wait_UNCONNECTED; + wire NLW_U0_Sl2_CE_UNCONNECTED; + wire NLW_U0_Sl2_Ready_UNCONNECTED; + wire NLW_U0_Sl2_UE_UNCONNECTED; + wire NLW_U0_Sl2_Wait_UNCONNECTED; + wire NLW_U0_Sl3_CE_UNCONNECTED; + wire NLW_U0_Sl3_Ready_UNCONNECTED; + wire NLW_U0_Sl3_UE_UNCONNECTED; + wire NLW_U0_Sl3_Wait_UNCONNECTED; + wire NLW_U0_UE_UNCONNECTED; + wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED; + wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED; + wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED; + wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED; + wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED; + wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED; + + (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* C_BRAM_AWIDTH = "32" *) + (* C_CE_COUNTER_WIDTH = "0" *) + (* C_CE_FAILING_REGISTERS = "0" *) + (* C_ECC = "0" *) + (* C_ECC_ONOFF_REGISTER = "0" *) + (* C_ECC_ONOFF_RESET_VALUE = "1" *) + (* C_ECC_STATUS_REGISTERS = "0" *) + (* C_FAMILY = "kintex7" *) + (* C_FAULT_INJECT = "0" *) + (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *) + (* C_INTERCONNECT = "0" *) + (* C_LMB_AWIDTH = "32" *) + (* C_LMB_DWIDTH = "32" *) + (* C_MASK = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) + (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) + (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) + (* C_NUM_LMB = "1" *) + (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) + (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *) + (* C_S_AXI_CTRL_DATA_WIDTH = "32" *) + (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) + (* C_UE_FAILING_REGISTERS = "0" *) + (* C_WRITE_ACCESS = "2" *) + system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0 + (.BRAM_Addr_A(BRAM_Addr_A), + .BRAM_Clk_A(BRAM_Clk_A), + .BRAM_Din_A(BRAM_Din_A), + .BRAM_Dout_A(BRAM_Dout_A), + .BRAM_EN_A(BRAM_EN_A), + .BRAM_Rst_A(BRAM_Rst_A), + .BRAM_WEN_A(BRAM_WEN_A), + .CE(NLW_U0_CE_UNCONNECTED), + .Interrupt(NLW_U0_Interrupt_UNCONNECTED), + .LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB1_AddrStrobe(1'b0), + .LMB1_BE({1'b0,1'b0,1'b0,1'b0}), + .LMB1_ReadStrobe(1'b0), + .LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB1_WriteStrobe(1'b0), + .LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB2_AddrStrobe(1'b0), + .LMB2_BE({1'b0,1'b0,1'b0,1'b0}), + .LMB2_ReadStrobe(1'b0), + .LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB2_WriteStrobe(1'b0), + .LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB3_AddrStrobe(1'b0), + .LMB3_BE({1'b0,1'b0,1'b0,1'b0}), + .LMB3_ReadStrobe(1'b0), + .LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB3_WriteStrobe(1'b0), + .LMB_ABus(LMB_ABus), + .LMB_AddrStrobe(LMB_AddrStrobe), + .LMB_BE(LMB_BE), + .LMB_Clk(LMB_Clk), + .LMB_ReadStrobe(LMB_ReadStrobe), + .LMB_Rst(LMB_Rst), + .LMB_WriteDBus(LMB_WriteDBus), + .LMB_WriteStrobe(LMB_WriteStrobe), + .S_AXI_CTRL_ACLK(1'b0), + .S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_ARESETN(1'b0), + .S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED), + .S_AXI_CTRL_ARVALID(1'b0), + .S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED), + .S_AXI_CTRL_AWVALID(1'b0), + .S_AXI_CTRL_BREADY(1'b0), + .S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]), + .S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED), + .S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]), + .S_AXI_CTRL_RREADY(1'b0), + .S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]), + .S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED), + .S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED), + .S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_CTRL_WVALID(1'b0), + .Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED), + .Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]), + .Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED), + .Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED), + .Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED), + .Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED), + .Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]), + .Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED), + .Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED), + .Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED), + .Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED), + .Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]), + .Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED), + .Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED), + .Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED), + .Sl_CE(Sl_CE), + .Sl_DBus(Sl_DBus), + .Sl_Ready(Sl_Ready), + .Sl_UE(Sl_UE), + .Sl_Wait(Sl_Wait), + .UE(NLW_U0_UE_UNCONNECTED)); +endmodule + (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *) (* C_CE_COUNTER_WIDTH = "0" *) (* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *) (* C_ECC_ONOFF_REGISTER = "0" *) (* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *) (* C_FAMILY = "kintex7" *) @@ -20,7 +214,7 @@ (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *) (* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *) -(* C_WRITE_ACCESS = "2" *) +(* C_WRITE_ACCESS = "2" *) (* ORIG_REF_NAME = "lmb_bram_if_cntlr" *) module system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr (LMB_Clk, LMB_Rst, @@ -412,200 +606,6 @@ module system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr .I1(lmb_as), .O(Sl_Ready)); endmodule - -(* CHECK_LICENSE_TYPE = "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_ilmb_bram_if_cntlr_0 - (LMB_Clk, - LMB_Rst, - LMB_ABus, - LMB_WriteDBus, - LMB_AddrStrobe, - LMB_ReadStrobe, - LMB_WriteStrobe, - LMB_BE, - Sl_DBus, - Sl_Ready, - Sl_Wait, - Sl_UE, - Sl_CE, - BRAM_Rst_A, - BRAM_Clk_A, - BRAM_Addr_A, - BRAM_EN_A, - BRAM_WEN_A, - BRAM_Dout_A, - BRAM_Din_A); - (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk; - (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE; - (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A; - (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A; - - wire [0:31]BRAM_Addr_A; - wire BRAM_Clk_A; - wire [0:31]BRAM_Din_A; - wire [0:31]BRAM_Dout_A; - wire BRAM_EN_A; - wire BRAM_Rst_A; - wire [0:3]BRAM_WEN_A; - wire [0:31]LMB_ABus; - wire LMB_AddrStrobe; - wire [0:3]LMB_BE; - wire LMB_Clk; - wire LMB_ReadStrobe; - wire LMB_Rst; - wire [0:31]LMB_WriteDBus; - wire LMB_WriteStrobe; - wire Sl_CE; - wire [0:31]Sl_DBus; - wire Sl_Ready; - wire Sl_UE; - wire Sl_Wait; - wire NLW_U0_CE_UNCONNECTED; - wire NLW_U0_Interrupt_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED; - wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED; - wire NLW_U0_Sl1_CE_UNCONNECTED; - wire NLW_U0_Sl1_Ready_UNCONNECTED; - wire NLW_U0_Sl1_UE_UNCONNECTED; - wire NLW_U0_Sl1_Wait_UNCONNECTED; - wire NLW_U0_Sl2_CE_UNCONNECTED; - wire NLW_U0_Sl2_Ready_UNCONNECTED; - wire NLW_U0_Sl2_UE_UNCONNECTED; - wire NLW_U0_Sl2_Wait_UNCONNECTED; - wire NLW_U0_Sl3_CE_UNCONNECTED; - wire NLW_U0_Sl3_Ready_UNCONNECTED; - wire NLW_U0_Sl3_UE_UNCONNECTED; - wire NLW_U0_Sl3_Wait_UNCONNECTED; - wire NLW_U0_UE_UNCONNECTED; - wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED; - wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED; - wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED; - wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED; - wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED; - wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED; - - (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) - (* C_BRAM_AWIDTH = "32" *) - (* C_CE_COUNTER_WIDTH = "0" *) - (* C_CE_FAILING_REGISTERS = "0" *) - (* C_ECC = "0" *) - (* C_ECC_ONOFF_REGISTER = "0" *) - (* C_ECC_ONOFF_RESET_VALUE = "1" *) - (* C_ECC_STATUS_REGISTERS = "0" *) - (* C_FAMILY = "kintex7" *) - (* C_FAULT_INJECT = "0" *) - (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *) - (* C_INTERCONNECT = "0" *) - (* C_LMB_AWIDTH = "32" *) - (* C_LMB_DWIDTH = "32" *) - (* C_MASK = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) - (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) - (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) - (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) - (* C_NUM_LMB = "1" *) - (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) - (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *) - (* C_S_AXI_CTRL_DATA_WIDTH = "32" *) - (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) - (* C_UE_FAILING_REGISTERS = "0" *) - (* C_WRITE_ACCESS = "2" *) - system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0 - (.BRAM_Addr_A(BRAM_Addr_A), - .BRAM_Clk_A(BRAM_Clk_A), - .BRAM_Din_A(BRAM_Din_A), - .BRAM_Dout_A(BRAM_Dout_A), - .BRAM_EN_A(BRAM_EN_A), - .BRAM_Rst_A(BRAM_Rst_A), - .BRAM_WEN_A(BRAM_WEN_A), - .CE(NLW_U0_CE_UNCONNECTED), - .Interrupt(NLW_U0_Interrupt_UNCONNECTED), - .LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB1_AddrStrobe(1'b0), - .LMB1_BE({1'b0,1'b0,1'b0,1'b0}), - .LMB1_ReadStrobe(1'b0), - .LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB1_WriteStrobe(1'b0), - .LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB2_AddrStrobe(1'b0), - .LMB2_BE({1'b0,1'b0,1'b0,1'b0}), - .LMB2_ReadStrobe(1'b0), - .LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB2_WriteStrobe(1'b0), - .LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB3_AddrStrobe(1'b0), - .LMB3_BE({1'b0,1'b0,1'b0,1'b0}), - .LMB3_ReadStrobe(1'b0), - .LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB3_WriteStrobe(1'b0), - .LMB_ABus(LMB_ABus), - .LMB_AddrStrobe(LMB_AddrStrobe), - .LMB_BE(LMB_BE), - .LMB_Clk(LMB_Clk), - .LMB_ReadStrobe(LMB_ReadStrobe), - .LMB_Rst(LMB_Rst), - .LMB_WriteDBus(LMB_WriteDBus), - .LMB_WriteStrobe(LMB_WriteStrobe), - .S_AXI_CTRL_ACLK(1'b0), - .S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_ARESETN(1'b0), - .S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED), - .S_AXI_CTRL_ARVALID(1'b0), - .S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED), - .S_AXI_CTRL_AWVALID(1'b0), - .S_AXI_CTRL_BREADY(1'b0), - .S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]), - .S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED), - .S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]), - .S_AXI_CTRL_RREADY(1'b0), - .S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]), - .S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED), - .S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED), - .S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}), - .S_AXI_CTRL_WVALID(1'b0), - .Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED), - .Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]), - .Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED), - .Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED), - .Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED), - .Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED), - .Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]), - .Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED), - .Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED), - .Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED), - .Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED), - .Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]), - .Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED), - .Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED), - .Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED), - .Sl_CE(Sl_CE), - .Sl_DBus(Sl_DBus), - .Sl_Ready(Sl_Ready), - .Sl_UE(Sl_UE), - .Sl_Wait(Sl_Wait), - .UE(NLW_U0_UE_UNCONNECTED)); -endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl index 7eb2569d..06043e52 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix --- system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:13 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl -- Design : system_bd_ilmb_bram_if_cntlr_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -142,6 +142,8 @@ entity system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr is attribute C_UE_FAILING_REGISTERS of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0; attribute C_WRITE_ACCESS : integer; attribute C_WRITE_ACCESS of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr"; end system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr; architecture STRUCTURE of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr is diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v index cdb86876..009b3fa6 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix -// system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:13 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v // Design : system_bd_ilmb_bram_if_cntlr_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl index dcf7be42..109c3d0a 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix --- system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:13 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl -- Design : system_bd_ilmb_bram_if_cntlr_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.dcp old mode 100644 new mode 100755 index 5c973124..dd3f02ae Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xml index 035574bd..60cc4c29 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xml @@ -2867,7 +2867,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2885,7 +2885,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2905,7 +2905,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2925,7 +2925,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2945,7 +2945,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -2963,7 +2963,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:56:19 UTC 2023 outputProductCRC @@ -3456,6 +3456,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_ilmb_v10_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_ilmb_v10_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_ilmb_v10_0_sim_netlist.v verilogSource @@ -3470,18 +3482,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_ilmb_v10_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_ilmb_v10_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.v index 045860e2..768bde3f 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.v @@ -1,8 +1,8 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:13 2023 +// Host : localhost.localdomain running 64-bit unknown // Command : write_verilog -force -mode funcsim -rename_top system_bd_ilmb_v10_0 -prefix // system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.v // Design : system_bd_dlmb_v10_0 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.vhdl index af31ce33..5a30c111 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.vhdl @@ -1,8 +1,8 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:13 2023 +-- Host : localhost.localdomain running 64-bit unknown -- Command : write_vhdl -force -mode funcsim -rename_top system_bd_ilmb_v10_0 -prefix -- system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.vhdl -- Design : system_bd_dlmb_v10_0 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.v index 1d06f203..0e034bce 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.v @@ -1,8 +1,8 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:13 2023 +// Host : localhost.localdomain running 64-bit unknown // Command : write_verilog -force -mode synth_stub -rename_top system_bd_ilmb_v10_0 -prefix // system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_stub.v // Design : system_bd_dlmb_v10_0 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.vhdl index 6cf0b8ff..54f6bd98 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.vhdl @@ -1,8 +1,8 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:13 2023 +-- Host : localhost.localdomain running 64-bit unknown -- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_ilmb_v10_0 -prefix -- system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_stub.vhdl -- Design : system_bd_dlmb_v10_0 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.dcp index 819e2304..cef9e3e6 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xml index cd43b89d..9a2ae369 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xml @@ -1458,7 +1458,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -1489,7 +1489,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -1508,7 +1508,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -1528,7 +1528,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -1546,7 +1546,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:57:03 UTC 2023 outputProductCRC @@ -3529,6 +3529,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_lmb_bram_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_lmb_bram_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_lmb_bram_0_sim_netlist.v verilogSource @@ -3543,18 +3555,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_lmb_bram_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_lmb_bram_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.v index bf26adea..27fb4ca0 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:58:03 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_lmb_bram_0 -prefix -// system_bd_lmb_bram_0_ system_bd_lmb_bram_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:57:03 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.v // Design : system_bd_lmb_bram_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -224,6 +224,7 @@ module system_bd_lmb_bram_0 .web(web)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module system_bd_lmb_bram_0_blk_mem_gen_generic_cstr (douta, doutb, @@ -783,6 +784,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_generic_cstr .web(web[1])); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module system_bd_lmb_bram_0_blk_mem_gen_prim_width (douta, doutb, @@ -3018,6 +3020,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_prim_width__parameterized9 .web(web)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper (douta, doutb, @@ -18817,6 +18820,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized9 .WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web})); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_top" *) module system_bd_lmb_bram_0_blk_mem_gen_top (douta, doutb, @@ -18912,7 +18916,7 @@ endmodule (* C_WEA_WIDTH = "4" *) (* C_WEB_WIDTH = "4" *) (* C_WRITE_DEPTH_A = "65536" *) (* C_WRITE_DEPTH_B = "65536" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *) -(* downgradeipidentifiedwarnings = "yes" *) +(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *) module system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 (clka, rsta, @@ -19198,6 +19202,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 .web(web)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *) module system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth (douta, doutb, diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.vhdl index fc8efddd..1115b7fa 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:58:03 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_lmb_bram_0 -prefix --- system_bd_lmb_bram_0_ system_bd_lmb_bram_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:57:03 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.vhdl -- Design : system_bd_lmb_bram_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -31,6 +31,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper is wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; end system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper; architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper is @@ -16097,6 +16099,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_prim_width is wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end system_bd_lmb_bram_0_blk_mem_gen_prim_width; architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_prim_width is @@ -17787,6 +17791,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_generic_cstr is rstb : in STD_LOGIC; enb : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end system_bd_lmb_bram_0_blk_mem_gen_generic_cstr; architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_generic_cstr is @@ -18385,6 +18391,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_top is rstb : in STD_LOGIC; enb : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_top : entity is "blk_mem_gen_top"; end system_bd_lmb_bram_0_blk_mem_gen_top; architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_top is @@ -18432,6 +18440,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth is rstb : in STD_LOGIC; enb : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth"; end system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth; architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth is @@ -18676,6 +18686,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 is attribute C_WRITE_WIDTH_B of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is 32; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is "kintex7"; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is "yes"; end system_bd_lmb_bram_0_blk_mem_gen_v8_4_3; diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v index 6680dc3a..c301879c 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:58:03 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_lmb_bram_0 -prefix -// system_bd_lmb_bram_0_ system_bd_lmb_bram_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:57:03 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v // Design : system_bd_lmb_bram_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl index 55f06610..82c39067 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:58:03 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_lmb_bram_0 -prefix --- system_bd_lmb_bram_0_ system_bd_lmb_bram_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:57:03 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl -- Design : system_bd_lmb_bram_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.dcp index ce7c4090..e1404854 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.xml index 26929588..eb3b24e7 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.xml @@ -30438,7 +30438,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -30469,7 +30469,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -30492,7 +30492,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -30512,7 +30512,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -30530,7 +30530,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:55:54 UTC 2023 outputProductCRC @@ -65390,6 +65390,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_mdm_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_mdm_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_mdm_0_sim_netlist.v verilogSource @@ -65404,18 +65416,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_mdm_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_mdm_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - Debug module for MicroBlaze Soft Processor. diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.v index b22e2f29..91891337 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:15 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_mdm_0 -prefix -// system_bd_mdm_0_ system_bd_mdm_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:53 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.v // Design : system_bd_mdm_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,6 +12,2477 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_mdm_0,MDM,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "MDM,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_mdm_0 + (Debug_SYS_Rst, + Dbg_Clk_0, + Dbg_TDI_0, + Dbg_TDO_0, + Dbg_Reg_En_0, + Dbg_Capture_0, + Dbg_Shift_0, + Dbg_Update_0, + Dbg_Rst_0, + Dbg_Disable_0); + (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.Debug_SYS_Rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output Debug_SYS_Rst; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK" *) output Dbg_Clk_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI" *) output Dbg_TDI_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO" *) input Dbg_TDO_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN" *) output [0:7]Dbg_Reg_En_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE" *) output Dbg_Capture_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT" *) output Dbg_Shift_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE" *) output Dbg_Update_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST" *) output Dbg_Rst_0; + (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 DISABLE" *) output Dbg_Disable_0; + + wire Dbg_Capture_0; + wire Dbg_Clk_0; + wire Dbg_Disable_0; + wire [0:7]Dbg_Reg_En_0; + wire Dbg_Rst_0; + wire Dbg_Shift_0; + wire Dbg_TDI_0; + wire Dbg_TDO_0; + wire Dbg_Update_0; + wire Debug_SYS_Rst; + wire NLW_U0_Dbg_ARVALID_0_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_1_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_10_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_11_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_12_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_13_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_14_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_15_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_16_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_17_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_18_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_19_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_2_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_20_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_21_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_22_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_23_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_24_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_25_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_26_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_27_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_28_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_29_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_3_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_30_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_31_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_4_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_5_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_6_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_7_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_8_UNCONNECTED; + wire NLW_U0_Dbg_ARVALID_9_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_0_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_1_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_10_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_11_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_12_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_13_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_14_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_15_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_16_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_17_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_18_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_19_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_2_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_20_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_21_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_22_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_23_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_24_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_25_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_26_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_27_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_28_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_29_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_3_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_30_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_31_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_4_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_5_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_6_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_7_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_8_UNCONNECTED; + wire NLW_U0_Dbg_AWVALID_9_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_0_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_1_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_10_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_11_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_12_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_13_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_14_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_15_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_16_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_17_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_18_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_19_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_2_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_20_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_21_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_22_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_23_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_24_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_25_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_26_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_27_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_28_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_29_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_3_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_30_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_31_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_4_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_5_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_6_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_7_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_8_UNCONNECTED; + wire NLW_U0_Dbg_BREADY_9_UNCONNECTED; + wire NLW_U0_Dbg_Capture_1_UNCONNECTED; + wire NLW_U0_Dbg_Capture_10_UNCONNECTED; + wire NLW_U0_Dbg_Capture_11_UNCONNECTED; + wire NLW_U0_Dbg_Capture_12_UNCONNECTED; + wire NLW_U0_Dbg_Capture_13_UNCONNECTED; + wire NLW_U0_Dbg_Capture_14_UNCONNECTED; + wire NLW_U0_Dbg_Capture_15_UNCONNECTED; + wire NLW_U0_Dbg_Capture_16_UNCONNECTED; + wire NLW_U0_Dbg_Capture_17_UNCONNECTED; + wire NLW_U0_Dbg_Capture_18_UNCONNECTED; + wire NLW_U0_Dbg_Capture_19_UNCONNECTED; + wire NLW_U0_Dbg_Capture_2_UNCONNECTED; + wire NLW_U0_Dbg_Capture_20_UNCONNECTED; + wire NLW_U0_Dbg_Capture_21_UNCONNECTED; + wire NLW_U0_Dbg_Capture_22_UNCONNECTED; + wire NLW_U0_Dbg_Capture_23_UNCONNECTED; + wire NLW_U0_Dbg_Capture_24_UNCONNECTED; + wire NLW_U0_Dbg_Capture_25_UNCONNECTED; + wire NLW_U0_Dbg_Capture_26_UNCONNECTED; + wire NLW_U0_Dbg_Capture_27_UNCONNECTED; + wire NLW_U0_Dbg_Capture_28_UNCONNECTED; + wire NLW_U0_Dbg_Capture_29_UNCONNECTED; + wire NLW_U0_Dbg_Capture_3_UNCONNECTED; + wire NLW_U0_Dbg_Capture_30_UNCONNECTED; + wire NLW_U0_Dbg_Capture_31_UNCONNECTED; + wire NLW_U0_Dbg_Capture_4_UNCONNECTED; + wire NLW_U0_Dbg_Capture_5_UNCONNECTED; + wire NLW_U0_Dbg_Capture_6_UNCONNECTED; + wire NLW_U0_Dbg_Capture_7_UNCONNECTED; + wire NLW_U0_Dbg_Capture_8_UNCONNECTED; + wire NLW_U0_Dbg_Capture_9_UNCONNECTED; + wire NLW_U0_Dbg_Clk_1_UNCONNECTED; + wire NLW_U0_Dbg_Clk_10_UNCONNECTED; + wire NLW_U0_Dbg_Clk_11_UNCONNECTED; + wire NLW_U0_Dbg_Clk_12_UNCONNECTED; + wire NLW_U0_Dbg_Clk_13_UNCONNECTED; + wire NLW_U0_Dbg_Clk_14_UNCONNECTED; + wire NLW_U0_Dbg_Clk_15_UNCONNECTED; + wire NLW_U0_Dbg_Clk_16_UNCONNECTED; + wire NLW_U0_Dbg_Clk_17_UNCONNECTED; + wire NLW_U0_Dbg_Clk_18_UNCONNECTED; + wire NLW_U0_Dbg_Clk_19_UNCONNECTED; + wire NLW_U0_Dbg_Clk_2_UNCONNECTED; + wire NLW_U0_Dbg_Clk_20_UNCONNECTED; + wire NLW_U0_Dbg_Clk_21_UNCONNECTED; + wire NLW_U0_Dbg_Clk_22_UNCONNECTED; + wire NLW_U0_Dbg_Clk_23_UNCONNECTED; + wire NLW_U0_Dbg_Clk_24_UNCONNECTED; + wire NLW_U0_Dbg_Clk_25_UNCONNECTED; + wire NLW_U0_Dbg_Clk_26_UNCONNECTED; + wire NLW_U0_Dbg_Clk_27_UNCONNECTED; + wire NLW_U0_Dbg_Clk_28_UNCONNECTED; + wire NLW_U0_Dbg_Clk_29_UNCONNECTED; + wire NLW_U0_Dbg_Clk_3_UNCONNECTED; + wire NLW_U0_Dbg_Clk_30_UNCONNECTED; + wire NLW_U0_Dbg_Clk_31_UNCONNECTED; + wire NLW_U0_Dbg_Clk_4_UNCONNECTED; + wire NLW_U0_Dbg_Clk_5_UNCONNECTED; + wire NLW_U0_Dbg_Clk_6_UNCONNECTED; + wire NLW_U0_Dbg_Clk_7_UNCONNECTED; + wire NLW_U0_Dbg_Clk_8_UNCONNECTED; + wire NLW_U0_Dbg_Clk_9_UNCONNECTED; + wire NLW_U0_Dbg_Disable_1_UNCONNECTED; + wire NLW_U0_Dbg_Disable_10_UNCONNECTED; + wire NLW_U0_Dbg_Disable_11_UNCONNECTED; + wire NLW_U0_Dbg_Disable_12_UNCONNECTED; + wire NLW_U0_Dbg_Disable_13_UNCONNECTED; + wire NLW_U0_Dbg_Disable_14_UNCONNECTED; + wire NLW_U0_Dbg_Disable_15_UNCONNECTED; + wire NLW_U0_Dbg_Disable_16_UNCONNECTED; + wire NLW_U0_Dbg_Disable_17_UNCONNECTED; + wire NLW_U0_Dbg_Disable_18_UNCONNECTED; + wire NLW_U0_Dbg_Disable_19_UNCONNECTED; + wire NLW_U0_Dbg_Disable_2_UNCONNECTED; + wire NLW_U0_Dbg_Disable_20_UNCONNECTED; + wire NLW_U0_Dbg_Disable_21_UNCONNECTED; + wire NLW_U0_Dbg_Disable_22_UNCONNECTED; + wire NLW_U0_Dbg_Disable_23_UNCONNECTED; + wire NLW_U0_Dbg_Disable_24_UNCONNECTED; + wire NLW_U0_Dbg_Disable_25_UNCONNECTED; + wire NLW_U0_Dbg_Disable_26_UNCONNECTED; + wire NLW_U0_Dbg_Disable_27_UNCONNECTED; + wire NLW_U0_Dbg_Disable_28_UNCONNECTED; + wire NLW_U0_Dbg_Disable_29_UNCONNECTED; + wire NLW_U0_Dbg_Disable_3_UNCONNECTED; + wire NLW_U0_Dbg_Disable_30_UNCONNECTED; + wire NLW_U0_Dbg_Disable_31_UNCONNECTED; + wire NLW_U0_Dbg_Disable_4_UNCONNECTED; + wire NLW_U0_Dbg_Disable_5_UNCONNECTED; + wire NLW_U0_Dbg_Disable_6_UNCONNECTED; + wire NLW_U0_Dbg_Disable_7_UNCONNECTED; + wire NLW_U0_Dbg_Disable_8_UNCONNECTED; + wire NLW_U0_Dbg_Disable_9_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_0_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_1_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_10_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_11_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_12_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_13_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_14_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_15_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_16_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_17_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_18_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_19_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_2_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_20_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_21_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_22_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_23_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_24_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_25_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_26_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_27_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_28_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_29_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_3_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_30_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_31_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_4_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_5_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_6_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_7_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_8_UNCONNECTED; + wire NLW_U0_Dbg_RREADY_9_UNCONNECTED; + wire NLW_U0_Dbg_Rst_1_UNCONNECTED; + wire NLW_U0_Dbg_Rst_10_UNCONNECTED; + wire NLW_U0_Dbg_Rst_11_UNCONNECTED; + wire NLW_U0_Dbg_Rst_12_UNCONNECTED; + wire NLW_U0_Dbg_Rst_13_UNCONNECTED; + wire NLW_U0_Dbg_Rst_14_UNCONNECTED; + wire NLW_U0_Dbg_Rst_15_UNCONNECTED; + wire NLW_U0_Dbg_Rst_16_UNCONNECTED; + wire NLW_U0_Dbg_Rst_17_UNCONNECTED; + wire NLW_U0_Dbg_Rst_18_UNCONNECTED; + wire NLW_U0_Dbg_Rst_19_UNCONNECTED; + wire NLW_U0_Dbg_Rst_2_UNCONNECTED; + wire NLW_U0_Dbg_Rst_20_UNCONNECTED; + wire NLW_U0_Dbg_Rst_21_UNCONNECTED; + wire NLW_U0_Dbg_Rst_22_UNCONNECTED; + wire NLW_U0_Dbg_Rst_23_UNCONNECTED; + wire NLW_U0_Dbg_Rst_24_UNCONNECTED; + wire NLW_U0_Dbg_Rst_25_UNCONNECTED; + wire NLW_U0_Dbg_Rst_26_UNCONNECTED; + wire NLW_U0_Dbg_Rst_27_UNCONNECTED; + wire NLW_U0_Dbg_Rst_28_UNCONNECTED; + wire NLW_U0_Dbg_Rst_29_UNCONNECTED; + wire NLW_U0_Dbg_Rst_3_UNCONNECTED; + wire NLW_U0_Dbg_Rst_30_UNCONNECTED; + wire NLW_U0_Dbg_Rst_31_UNCONNECTED; + wire NLW_U0_Dbg_Rst_4_UNCONNECTED; + wire NLW_U0_Dbg_Rst_5_UNCONNECTED; + wire NLW_U0_Dbg_Rst_6_UNCONNECTED; + wire NLW_U0_Dbg_Rst_7_UNCONNECTED; + wire NLW_U0_Dbg_Rst_8_UNCONNECTED; + wire NLW_U0_Dbg_Rst_9_UNCONNECTED; + wire NLW_U0_Dbg_Shift_1_UNCONNECTED; + wire NLW_U0_Dbg_Shift_10_UNCONNECTED; + wire NLW_U0_Dbg_Shift_11_UNCONNECTED; + wire NLW_U0_Dbg_Shift_12_UNCONNECTED; + wire NLW_U0_Dbg_Shift_13_UNCONNECTED; + wire NLW_U0_Dbg_Shift_14_UNCONNECTED; + wire NLW_U0_Dbg_Shift_15_UNCONNECTED; + wire NLW_U0_Dbg_Shift_16_UNCONNECTED; + wire NLW_U0_Dbg_Shift_17_UNCONNECTED; + wire NLW_U0_Dbg_Shift_18_UNCONNECTED; + wire NLW_U0_Dbg_Shift_19_UNCONNECTED; + wire NLW_U0_Dbg_Shift_2_UNCONNECTED; + wire NLW_U0_Dbg_Shift_20_UNCONNECTED; + wire NLW_U0_Dbg_Shift_21_UNCONNECTED; + wire NLW_U0_Dbg_Shift_22_UNCONNECTED; + wire NLW_U0_Dbg_Shift_23_UNCONNECTED; + wire NLW_U0_Dbg_Shift_24_UNCONNECTED; + wire NLW_U0_Dbg_Shift_25_UNCONNECTED; + wire NLW_U0_Dbg_Shift_26_UNCONNECTED; + wire NLW_U0_Dbg_Shift_27_UNCONNECTED; + wire NLW_U0_Dbg_Shift_28_UNCONNECTED; + wire NLW_U0_Dbg_Shift_29_UNCONNECTED; + wire NLW_U0_Dbg_Shift_3_UNCONNECTED; + wire NLW_U0_Dbg_Shift_30_UNCONNECTED; + wire NLW_U0_Dbg_Shift_31_UNCONNECTED; + wire NLW_U0_Dbg_Shift_4_UNCONNECTED; + wire NLW_U0_Dbg_Shift_5_UNCONNECTED; + wire NLW_U0_Dbg_Shift_6_UNCONNECTED; + wire NLW_U0_Dbg_Shift_7_UNCONNECTED; + wire NLW_U0_Dbg_Shift_8_UNCONNECTED; + wire NLW_U0_Dbg_Shift_9_UNCONNECTED; + wire NLW_U0_Dbg_TDI_1_UNCONNECTED; + wire NLW_U0_Dbg_TDI_10_UNCONNECTED; + wire NLW_U0_Dbg_TDI_11_UNCONNECTED; + wire NLW_U0_Dbg_TDI_12_UNCONNECTED; + wire NLW_U0_Dbg_TDI_13_UNCONNECTED; + wire NLW_U0_Dbg_TDI_14_UNCONNECTED; + wire NLW_U0_Dbg_TDI_15_UNCONNECTED; + wire NLW_U0_Dbg_TDI_16_UNCONNECTED; + wire NLW_U0_Dbg_TDI_17_UNCONNECTED; + wire NLW_U0_Dbg_TDI_18_UNCONNECTED; + wire NLW_U0_Dbg_TDI_19_UNCONNECTED; + wire NLW_U0_Dbg_TDI_2_UNCONNECTED; + wire NLW_U0_Dbg_TDI_20_UNCONNECTED; + wire NLW_U0_Dbg_TDI_21_UNCONNECTED; + wire NLW_U0_Dbg_TDI_22_UNCONNECTED; + wire NLW_U0_Dbg_TDI_23_UNCONNECTED; + wire NLW_U0_Dbg_TDI_24_UNCONNECTED; + wire NLW_U0_Dbg_TDI_25_UNCONNECTED; + wire NLW_U0_Dbg_TDI_26_UNCONNECTED; + wire NLW_U0_Dbg_TDI_27_UNCONNECTED; + wire NLW_U0_Dbg_TDI_28_UNCONNECTED; + wire NLW_U0_Dbg_TDI_29_UNCONNECTED; + wire NLW_U0_Dbg_TDI_3_UNCONNECTED; + wire NLW_U0_Dbg_TDI_30_UNCONNECTED; + wire NLW_U0_Dbg_TDI_31_UNCONNECTED; + wire NLW_U0_Dbg_TDI_4_UNCONNECTED; + wire NLW_U0_Dbg_TDI_5_UNCONNECTED; + wire NLW_U0_Dbg_TDI_6_UNCONNECTED; + wire NLW_U0_Dbg_TDI_7_UNCONNECTED; + wire NLW_U0_Dbg_TDI_8_UNCONNECTED; + wire NLW_U0_Dbg_TDI_9_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_0_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_1_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_10_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_11_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_12_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_13_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_14_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_15_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_16_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_17_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_18_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_19_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_2_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_20_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_21_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_22_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_23_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_24_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_25_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_26_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_27_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_28_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_29_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_3_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_30_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_31_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_4_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_5_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_6_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_7_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_8_UNCONNECTED; + wire NLW_U0_Dbg_TrClk_9_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_0_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_1_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_10_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_11_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_12_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_13_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_14_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_15_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_16_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_17_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_18_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_19_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_2_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_20_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_21_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_22_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_23_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_24_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_25_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_26_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_27_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_28_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_29_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_3_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_30_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_31_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_4_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_5_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_6_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_7_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_8_UNCONNECTED; + wire NLW_U0_Dbg_TrReady_9_UNCONNECTED; + wire NLW_U0_Dbg_Update_1_UNCONNECTED; + wire NLW_U0_Dbg_Update_10_UNCONNECTED; + wire NLW_U0_Dbg_Update_11_UNCONNECTED; + wire NLW_U0_Dbg_Update_12_UNCONNECTED; + wire NLW_U0_Dbg_Update_13_UNCONNECTED; + wire NLW_U0_Dbg_Update_14_UNCONNECTED; + wire NLW_U0_Dbg_Update_15_UNCONNECTED; + wire NLW_U0_Dbg_Update_16_UNCONNECTED; + wire NLW_U0_Dbg_Update_17_UNCONNECTED; + wire NLW_U0_Dbg_Update_18_UNCONNECTED; + wire NLW_U0_Dbg_Update_19_UNCONNECTED; + wire NLW_U0_Dbg_Update_2_UNCONNECTED; + wire NLW_U0_Dbg_Update_20_UNCONNECTED; + wire NLW_U0_Dbg_Update_21_UNCONNECTED; + wire NLW_U0_Dbg_Update_22_UNCONNECTED; + wire NLW_U0_Dbg_Update_23_UNCONNECTED; + wire NLW_U0_Dbg_Update_24_UNCONNECTED; + wire NLW_U0_Dbg_Update_25_UNCONNECTED; + wire NLW_U0_Dbg_Update_26_UNCONNECTED; + wire NLW_U0_Dbg_Update_27_UNCONNECTED; + wire NLW_U0_Dbg_Update_28_UNCONNECTED; + wire NLW_U0_Dbg_Update_29_UNCONNECTED; + wire NLW_U0_Dbg_Update_3_UNCONNECTED; + wire NLW_U0_Dbg_Update_30_UNCONNECTED; + wire NLW_U0_Dbg_Update_31_UNCONNECTED; + wire NLW_U0_Dbg_Update_4_UNCONNECTED; + wire NLW_U0_Dbg_Update_5_UNCONNECTED; + wire NLW_U0_Dbg_Update_6_UNCONNECTED; + wire NLW_U0_Dbg_Update_7_UNCONNECTED; + wire NLW_U0_Dbg_Update_8_UNCONNECTED; + wire NLW_U0_Dbg_Update_9_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_0_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_1_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_10_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_11_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_12_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_13_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_14_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_15_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_16_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_17_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_18_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_19_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_2_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_20_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_21_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_22_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_23_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_24_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_25_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_26_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_27_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_28_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_29_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_3_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_30_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_31_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_4_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_5_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_6_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_7_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_8_UNCONNECTED; + wire NLW_U0_Dbg_WVALID_9_UNCONNECTED; + wire NLW_U0_Ext_BRK_UNCONNECTED; + wire NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED; + wire NLW_U0_Ext_JTAG_DRCK_UNCONNECTED; + wire NLW_U0_Ext_JTAG_RESET_UNCONNECTED; + wire NLW_U0_Ext_JTAG_SEL_UNCONNECTED; + wire NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED; + wire NLW_U0_Ext_JTAG_TDI_UNCONNECTED; + wire NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED; + wire NLW_U0_Ext_NM_BRK_UNCONNECTED; + wire NLW_U0_Interrupt_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED; + wire NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_0_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_1_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_10_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_11_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_12_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_13_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_14_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_15_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_16_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_17_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_18_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_19_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_2_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_20_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_21_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_22_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_23_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_24_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_25_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_26_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_27_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_28_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_29_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_3_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_30_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_31_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_4_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_5_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_6_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_7_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_8_UNCONNECTED; + wire NLW_U0_LMB_Read_Strobe_9_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_0_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_1_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_10_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_11_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_12_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_13_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_14_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_15_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_16_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_17_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_18_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_19_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_2_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_20_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_21_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_22_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_23_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_24_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_25_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_26_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_27_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_28_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_29_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_3_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_30_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_31_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_4_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_5_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_6_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_7_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_8_UNCONNECTED; + wire NLW_U0_LMB_Write_Strobe_9_UNCONNECTED; + wire NLW_U0_M_AXIS_TVALID_UNCONNECTED; + wire NLW_U0_M_AXI_ARLOCK_UNCONNECTED; + wire NLW_U0_M_AXI_ARVALID_UNCONNECTED; + wire NLW_U0_M_AXI_AWLOCK_UNCONNECTED; + wire NLW_U0_M_AXI_AWVALID_UNCONNECTED; + wire NLW_U0_M_AXI_BREADY_UNCONNECTED; + wire NLW_U0_M_AXI_RREADY_UNCONNECTED; + wire NLW_U0_M_AXI_WLAST_UNCONNECTED; + wire NLW_U0_M_AXI_WVALID_UNCONNECTED; + wire NLW_U0_S_AXI_ARREADY_UNCONNECTED; + wire NLW_U0_S_AXI_AWREADY_UNCONNECTED; + wire NLW_U0_S_AXI_BVALID_UNCONNECTED; + wire NLW_U0_S_AXI_RVALID_UNCONNECTED; + wire NLW_U0_S_AXI_WREADY_UNCONNECTED; + wire NLW_U0_TRACE_CLK_OUT_UNCONNECTED; + wire NLW_U0_TRACE_CTL_UNCONNECTED; + wire NLW_U0_Trig_Ack_In_0_UNCONNECTED; + wire NLW_U0_Trig_Ack_In_1_UNCONNECTED; + wire NLW_U0_Trig_Ack_In_2_UNCONNECTED; + wire NLW_U0_Trig_Ack_In_3_UNCONNECTED; + wire NLW_U0_Trig_Out_0_UNCONNECTED; + wire NLW_U0_Trig_Out_1_UNCONNECTED; + wire NLW_U0_Trig_Out_2_UNCONNECTED; + wire NLW_U0_Trig_Out_3_UNCONNECTED; + wire NLW_U0_bscan_ext_tdo_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_0_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_1_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_10_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_11_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_12_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_13_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_14_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_15_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_16_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_17_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_18_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_19_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_2_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_20_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_21_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_22_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_23_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_24_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_25_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_26_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_27_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_28_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_29_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_3_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_30_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_31_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_4_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_5_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_6_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_7_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_8_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_ARADDR_9_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_0_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_1_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_10_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_11_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_12_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_13_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_14_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_15_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_16_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_17_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_18_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_19_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_2_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_20_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_21_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_22_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_23_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_24_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_25_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_26_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_27_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_28_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_29_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_3_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_30_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_31_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_4_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_5_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_6_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_7_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_8_UNCONNECTED; + wire [14:2]NLW_U0_Dbg_AWADDR_9_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_1_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_10_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_11_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_12_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_13_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_14_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_15_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_16_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_17_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_18_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_19_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_2_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_20_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_21_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_22_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_23_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_24_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_25_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_26_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_27_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_28_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_29_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_3_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_30_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_31_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_4_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_5_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_6_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_7_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_8_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Reg_En_9_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_0_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_1_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_10_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_11_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_12_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_13_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_14_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_15_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_16_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_17_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_18_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_19_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_2_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_20_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_21_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_22_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_23_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_24_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_25_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_26_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_27_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_28_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_29_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_3_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_30_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_31_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_4_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_5_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_6_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_7_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_8_UNCONNECTED; + wire [0:7]NLW_U0_Dbg_Trig_Out_9_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_0_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_1_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_10_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_11_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_12_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_13_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_14_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_15_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_16_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_17_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_18_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_19_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_2_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_20_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_21_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_22_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_23_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_24_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_25_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_26_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_27_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_28_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_29_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_3_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_30_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_31_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_4_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_5_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_6_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_7_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_8_UNCONNECTED; + wire [31:0]NLW_U0_Dbg_WDATA_9_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_0_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_1_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_10_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_11_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_12_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_13_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_14_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_15_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_16_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_17_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_18_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_19_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_2_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_20_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_21_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_22_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_23_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_24_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_25_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_26_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_27_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_28_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_29_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_3_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_30_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_31_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_4_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_5_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_6_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_7_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_8_UNCONNECTED; + wire [0:3]NLW_U0_LMB_Byte_Enable_9_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_0_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_1_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_10_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_11_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_12_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_13_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_14_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_15_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_16_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_17_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_18_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_19_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_2_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_20_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_21_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_22_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_23_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_24_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_25_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_26_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_27_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_28_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_29_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_3_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_30_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_31_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_4_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_5_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_6_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_7_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_8_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Addr_9_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_0_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_1_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_10_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_11_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_12_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_13_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_14_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_15_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_16_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_17_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_18_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_19_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_2_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_20_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_21_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_22_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_23_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_24_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_25_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_26_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_27_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_28_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_29_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_3_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_30_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_31_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_4_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_5_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_6_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_7_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_8_UNCONNECTED; + wire [0:31]NLW_U0_LMB_Data_Write_9_UNCONNECTED; + wire [31:0]NLW_U0_M_AXIS_TDATA_UNCONNECTED; + wire [6:0]NLW_U0_M_AXIS_TID_UNCONNECTED; + wire [31:0]NLW_U0_M_AXI_ARADDR_UNCONNECTED; + wire [1:0]NLW_U0_M_AXI_ARBURST_UNCONNECTED; + wire [3:0]NLW_U0_M_AXI_ARCACHE_UNCONNECTED; + wire [0:0]NLW_U0_M_AXI_ARID_UNCONNECTED; + wire [7:0]NLW_U0_M_AXI_ARLEN_UNCONNECTED; + wire [2:0]NLW_U0_M_AXI_ARPROT_UNCONNECTED; + wire [3:0]NLW_U0_M_AXI_ARQOS_UNCONNECTED; + wire [2:0]NLW_U0_M_AXI_ARSIZE_UNCONNECTED; + wire [31:0]NLW_U0_M_AXI_AWADDR_UNCONNECTED; + wire [1:0]NLW_U0_M_AXI_AWBURST_UNCONNECTED; + wire [3:0]NLW_U0_M_AXI_AWCACHE_UNCONNECTED; + wire [0:0]NLW_U0_M_AXI_AWID_UNCONNECTED; + wire [7:0]NLW_U0_M_AXI_AWLEN_UNCONNECTED; + wire [2:0]NLW_U0_M_AXI_AWPROT_UNCONNECTED; + wire [3:0]NLW_U0_M_AXI_AWQOS_UNCONNECTED; + wire [2:0]NLW_U0_M_AXI_AWSIZE_UNCONNECTED; + wire [31:0]NLW_U0_M_AXI_WDATA_UNCONNECTED; + wire [3:0]NLW_U0_M_AXI_WSTRB_UNCONNECTED; + wire [1:0]NLW_U0_S_AXI_BRESP_UNCONNECTED; + wire [31:0]NLW_U0_S_AXI_RDATA_UNCONNECTED; + wire [1:0]NLW_U0_S_AXI_RRESP_UNCONNECTED; + wire [31:0]NLW_U0_TRACE_DATA_UNCONNECTED; + + (* C_ADDR_SIZE = "32" *) + (* C_AVOID_PRIMITIVES = "0" *) + (* C_BSCANID = "76547328" *) + (* C_DATA_SIZE = "32" *) + (* C_DBG_MEM_ACCESS = "0" *) + (* C_DBG_REG_ACCESS = "0" *) + (* C_DEBUG_INTERFACE = "0" *) + (* C_EXT_TRIG_RESET_VALUE = "20'b11110001001000110100" *) + (* C_FAMILY = "kintex7" *) + (* C_INTERCONNECT = "2" *) + (* C_JTAG_CHAIN = "2" *) + (* C_MB_DBG_PORTS = "1" *) + (* C_M_AXIS_DATA_WIDTH = "32" *) + (* C_M_AXIS_ID_WIDTH = "7" *) + (* C_M_AXI_ADDR_WIDTH = "32" *) + (* C_M_AXI_DATA_WIDTH = "32" *) + (* C_M_AXI_THREAD_ID_WIDTH = "1" *) + (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *) + (* C_S_AXI_ADDR_WIDTH = "4" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* C_TRACE_ASYNC_RESET = "0" *) + (* C_TRACE_CLK_FREQ_HZ = "200000000" *) + (* C_TRACE_CLK_OUT_PHASE = "90" *) + (* C_TRACE_DATA_WIDTH = "32" *) + (* C_TRACE_ID = "110" *) + (* C_TRACE_OUTPUT = "0" *) + (* C_TRACE_PROTOCOL = "1" *) + (* C_USE_BSCAN = "0" *) + (* C_USE_CONFIG_RESET = "0" *) + (* C_USE_CROSS_TRIGGER = "0" *) + (* C_USE_UART = "0" *) + system_bd_mdm_0_MDM U0 + (.Config_Reset(1'b0), + .Dbg_ARADDR_0(NLW_U0_Dbg_ARADDR_0_UNCONNECTED[14:2]), + .Dbg_ARADDR_1(NLW_U0_Dbg_ARADDR_1_UNCONNECTED[14:2]), + .Dbg_ARADDR_10(NLW_U0_Dbg_ARADDR_10_UNCONNECTED[14:2]), + .Dbg_ARADDR_11(NLW_U0_Dbg_ARADDR_11_UNCONNECTED[14:2]), + .Dbg_ARADDR_12(NLW_U0_Dbg_ARADDR_12_UNCONNECTED[14:2]), + .Dbg_ARADDR_13(NLW_U0_Dbg_ARADDR_13_UNCONNECTED[14:2]), + .Dbg_ARADDR_14(NLW_U0_Dbg_ARADDR_14_UNCONNECTED[14:2]), + .Dbg_ARADDR_15(NLW_U0_Dbg_ARADDR_15_UNCONNECTED[14:2]), + .Dbg_ARADDR_16(NLW_U0_Dbg_ARADDR_16_UNCONNECTED[14:2]), + .Dbg_ARADDR_17(NLW_U0_Dbg_ARADDR_17_UNCONNECTED[14:2]), + .Dbg_ARADDR_18(NLW_U0_Dbg_ARADDR_18_UNCONNECTED[14:2]), + .Dbg_ARADDR_19(NLW_U0_Dbg_ARADDR_19_UNCONNECTED[14:2]), + .Dbg_ARADDR_2(NLW_U0_Dbg_ARADDR_2_UNCONNECTED[14:2]), + .Dbg_ARADDR_20(NLW_U0_Dbg_ARADDR_20_UNCONNECTED[14:2]), + .Dbg_ARADDR_21(NLW_U0_Dbg_ARADDR_21_UNCONNECTED[14:2]), + .Dbg_ARADDR_22(NLW_U0_Dbg_ARADDR_22_UNCONNECTED[14:2]), + .Dbg_ARADDR_23(NLW_U0_Dbg_ARADDR_23_UNCONNECTED[14:2]), + .Dbg_ARADDR_24(NLW_U0_Dbg_ARADDR_24_UNCONNECTED[14:2]), + .Dbg_ARADDR_25(NLW_U0_Dbg_ARADDR_25_UNCONNECTED[14:2]), + .Dbg_ARADDR_26(NLW_U0_Dbg_ARADDR_26_UNCONNECTED[14:2]), + .Dbg_ARADDR_27(NLW_U0_Dbg_ARADDR_27_UNCONNECTED[14:2]), + .Dbg_ARADDR_28(NLW_U0_Dbg_ARADDR_28_UNCONNECTED[14:2]), + .Dbg_ARADDR_29(NLW_U0_Dbg_ARADDR_29_UNCONNECTED[14:2]), + .Dbg_ARADDR_3(NLW_U0_Dbg_ARADDR_3_UNCONNECTED[14:2]), + .Dbg_ARADDR_30(NLW_U0_Dbg_ARADDR_30_UNCONNECTED[14:2]), + .Dbg_ARADDR_31(NLW_U0_Dbg_ARADDR_31_UNCONNECTED[14:2]), + .Dbg_ARADDR_4(NLW_U0_Dbg_ARADDR_4_UNCONNECTED[14:2]), + .Dbg_ARADDR_5(NLW_U0_Dbg_ARADDR_5_UNCONNECTED[14:2]), + .Dbg_ARADDR_6(NLW_U0_Dbg_ARADDR_6_UNCONNECTED[14:2]), + .Dbg_ARADDR_7(NLW_U0_Dbg_ARADDR_7_UNCONNECTED[14:2]), + .Dbg_ARADDR_8(NLW_U0_Dbg_ARADDR_8_UNCONNECTED[14:2]), + .Dbg_ARADDR_9(NLW_U0_Dbg_ARADDR_9_UNCONNECTED[14:2]), + .Dbg_ARREADY_0(1'b0), + .Dbg_ARREADY_1(1'b0), + .Dbg_ARREADY_10(1'b0), + .Dbg_ARREADY_11(1'b0), + .Dbg_ARREADY_12(1'b0), + .Dbg_ARREADY_13(1'b0), + .Dbg_ARREADY_14(1'b0), + .Dbg_ARREADY_15(1'b0), + .Dbg_ARREADY_16(1'b0), + .Dbg_ARREADY_17(1'b0), + .Dbg_ARREADY_18(1'b0), + .Dbg_ARREADY_19(1'b0), + .Dbg_ARREADY_2(1'b0), + .Dbg_ARREADY_20(1'b0), + .Dbg_ARREADY_21(1'b0), + .Dbg_ARREADY_22(1'b0), + .Dbg_ARREADY_23(1'b0), + .Dbg_ARREADY_24(1'b0), + .Dbg_ARREADY_25(1'b0), + .Dbg_ARREADY_26(1'b0), + .Dbg_ARREADY_27(1'b0), + .Dbg_ARREADY_28(1'b0), + .Dbg_ARREADY_29(1'b0), + .Dbg_ARREADY_3(1'b0), + .Dbg_ARREADY_30(1'b0), + .Dbg_ARREADY_31(1'b0), + .Dbg_ARREADY_4(1'b0), + .Dbg_ARREADY_5(1'b0), + .Dbg_ARREADY_6(1'b0), + .Dbg_ARREADY_7(1'b0), + .Dbg_ARREADY_8(1'b0), + .Dbg_ARREADY_9(1'b0), + .Dbg_ARVALID_0(NLW_U0_Dbg_ARVALID_0_UNCONNECTED), + .Dbg_ARVALID_1(NLW_U0_Dbg_ARVALID_1_UNCONNECTED), + .Dbg_ARVALID_10(NLW_U0_Dbg_ARVALID_10_UNCONNECTED), + .Dbg_ARVALID_11(NLW_U0_Dbg_ARVALID_11_UNCONNECTED), + .Dbg_ARVALID_12(NLW_U0_Dbg_ARVALID_12_UNCONNECTED), + .Dbg_ARVALID_13(NLW_U0_Dbg_ARVALID_13_UNCONNECTED), + .Dbg_ARVALID_14(NLW_U0_Dbg_ARVALID_14_UNCONNECTED), + .Dbg_ARVALID_15(NLW_U0_Dbg_ARVALID_15_UNCONNECTED), + .Dbg_ARVALID_16(NLW_U0_Dbg_ARVALID_16_UNCONNECTED), + .Dbg_ARVALID_17(NLW_U0_Dbg_ARVALID_17_UNCONNECTED), + .Dbg_ARVALID_18(NLW_U0_Dbg_ARVALID_18_UNCONNECTED), + .Dbg_ARVALID_19(NLW_U0_Dbg_ARVALID_19_UNCONNECTED), + .Dbg_ARVALID_2(NLW_U0_Dbg_ARVALID_2_UNCONNECTED), + .Dbg_ARVALID_20(NLW_U0_Dbg_ARVALID_20_UNCONNECTED), + .Dbg_ARVALID_21(NLW_U0_Dbg_ARVALID_21_UNCONNECTED), + .Dbg_ARVALID_22(NLW_U0_Dbg_ARVALID_22_UNCONNECTED), + .Dbg_ARVALID_23(NLW_U0_Dbg_ARVALID_23_UNCONNECTED), + .Dbg_ARVALID_24(NLW_U0_Dbg_ARVALID_24_UNCONNECTED), + .Dbg_ARVALID_25(NLW_U0_Dbg_ARVALID_25_UNCONNECTED), + .Dbg_ARVALID_26(NLW_U0_Dbg_ARVALID_26_UNCONNECTED), + .Dbg_ARVALID_27(NLW_U0_Dbg_ARVALID_27_UNCONNECTED), + .Dbg_ARVALID_28(NLW_U0_Dbg_ARVALID_28_UNCONNECTED), + .Dbg_ARVALID_29(NLW_U0_Dbg_ARVALID_29_UNCONNECTED), + .Dbg_ARVALID_3(NLW_U0_Dbg_ARVALID_3_UNCONNECTED), + .Dbg_ARVALID_30(NLW_U0_Dbg_ARVALID_30_UNCONNECTED), + .Dbg_ARVALID_31(NLW_U0_Dbg_ARVALID_31_UNCONNECTED), + .Dbg_ARVALID_4(NLW_U0_Dbg_ARVALID_4_UNCONNECTED), + .Dbg_ARVALID_5(NLW_U0_Dbg_ARVALID_5_UNCONNECTED), + .Dbg_ARVALID_6(NLW_U0_Dbg_ARVALID_6_UNCONNECTED), + .Dbg_ARVALID_7(NLW_U0_Dbg_ARVALID_7_UNCONNECTED), + .Dbg_ARVALID_8(NLW_U0_Dbg_ARVALID_8_UNCONNECTED), + .Dbg_ARVALID_9(NLW_U0_Dbg_ARVALID_9_UNCONNECTED), + .Dbg_AWADDR_0(NLW_U0_Dbg_AWADDR_0_UNCONNECTED[14:2]), + .Dbg_AWADDR_1(NLW_U0_Dbg_AWADDR_1_UNCONNECTED[14:2]), + .Dbg_AWADDR_10(NLW_U0_Dbg_AWADDR_10_UNCONNECTED[14:2]), + .Dbg_AWADDR_11(NLW_U0_Dbg_AWADDR_11_UNCONNECTED[14:2]), + .Dbg_AWADDR_12(NLW_U0_Dbg_AWADDR_12_UNCONNECTED[14:2]), + .Dbg_AWADDR_13(NLW_U0_Dbg_AWADDR_13_UNCONNECTED[14:2]), + .Dbg_AWADDR_14(NLW_U0_Dbg_AWADDR_14_UNCONNECTED[14:2]), + .Dbg_AWADDR_15(NLW_U0_Dbg_AWADDR_15_UNCONNECTED[14:2]), + .Dbg_AWADDR_16(NLW_U0_Dbg_AWADDR_16_UNCONNECTED[14:2]), + .Dbg_AWADDR_17(NLW_U0_Dbg_AWADDR_17_UNCONNECTED[14:2]), + .Dbg_AWADDR_18(NLW_U0_Dbg_AWADDR_18_UNCONNECTED[14:2]), + .Dbg_AWADDR_19(NLW_U0_Dbg_AWADDR_19_UNCONNECTED[14:2]), + .Dbg_AWADDR_2(NLW_U0_Dbg_AWADDR_2_UNCONNECTED[14:2]), + .Dbg_AWADDR_20(NLW_U0_Dbg_AWADDR_20_UNCONNECTED[14:2]), + .Dbg_AWADDR_21(NLW_U0_Dbg_AWADDR_21_UNCONNECTED[14:2]), + .Dbg_AWADDR_22(NLW_U0_Dbg_AWADDR_22_UNCONNECTED[14:2]), + .Dbg_AWADDR_23(NLW_U0_Dbg_AWADDR_23_UNCONNECTED[14:2]), + .Dbg_AWADDR_24(NLW_U0_Dbg_AWADDR_24_UNCONNECTED[14:2]), + .Dbg_AWADDR_25(NLW_U0_Dbg_AWADDR_25_UNCONNECTED[14:2]), + .Dbg_AWADDR_26(NLW_U0_Dbg_AWADDR_26_UNCONNECTED[14:2]), + .Dbg_AWADDR_27(NLW_U0_Dbg_AWADDR_27_UNCONNECTED[14:2]), + .Dbg_AWADDR_28(NLW_U0_Dbg_AWADDR_28_UNCONNECTED[14:2]), + .Dbg_AWADDR_29(NLW_U0_Dbg_AWADDR_29_UNCONNECTED[14:2]), + .Dbg_AWADDR_3(NLW_U0_Dbg_AWADDR_3_UNCONNECTED[14:2]), + .Dbg_AWADDR_30(NLW_U0_Dbg_AWADDR_30_UNCONNECTED[14:2]), + .Dbg_AWADDR_31(NLW_U0_Dbg_AWADDR_31_UNCONNECTED[14:2]), + .Dbg_AWADDR_4(NLW_U0_Dbg_AWADDR_4_UNCONNECTED[14:2]), + .Dbg_AWADDR_5(NLW_U0_Dbg_AWADDR_5_UNCONNECTED[14:2]), + .Dbg_AWADDR_6(NLW_U0_Dbg_AWADDR_6_UNCONNECTED[14:2]), + .Dbg_AWADDR_7(NLW_U0_Dbg_AWADDR_7_UNCONNECTED[14:2]), + .Dbg_AWADDR_8(NLW_U0_Dbg_AWADDR_8_UNCONNECTED[14:2]), + .Dbg_AWADDR_9(NLW_U0_Dbg_AWADDR_9_UNCONNECTED[14:2]), + .Dbg_AWREADY_0(1'b0), + .Dbg_AWREADY_1(1'b0), + .Dbg_AWREADY_10(1'b0), + .Dbg_AWREADY_11(1'b0), + .Dbg_AWREADY_12(1'b0), + .Dbg_AWREADY_13(1'b0), + .Dbg_AWREADY_14(1'b0), + .Dbg_AWREADY_15(1'b0), + .Dbg_AWREADY_16(1'b0), + .Dbg_AWREADY_17(1'b0), + .Dbg_AWREADY_18(1'b0), + .Dbg_AWREADY_19(1'b0), + .Dbg_AWREADY_2(1'b0), + .Dbg_AWREADY_20(1'b0), + .Dbg_AWREADY_21(1'b0), + .Dbg_AWREADY_22(1'b0), + .Dbg_AWREADY_23(1'b0), + .Dbg_AWREADY_24(1'b0), + .Dbg_AWREADY_25(1'b0), + .Dbg_AWREADY_26(1'b0), + .Dbg_AWREADY_27(1'b0), + .Dbg_AWREADY_28(1'b0), + .Dbg_AWREADY_29(1'b0), + .Dbg_AWREADY_3(1'b0), + .Dbg_AWREADY_30(1'b0), + .Dbg_AWREADY_31(1'b0), + .Dbg_AWREADY_4(1'b0), + .Dbg_AWREADY_5(1'b0), + .Dbg_AWREADY_6(1'b0), + .Dbg_AWREADY_7(1'b0), + .Dbg_AWREADY_8(1'b0), + .Dbg_AWREADY_9(1'b0), + .Dbg_AWVALID_0(NLW_U0_Dbg_AWVALID_0_UNCONNECTED), + .Dbg_AWVALID_1(NLW_U0_Dbg_AWVALID_1_UNCONNECTED), + .Dbg_AWVALID_10(NLW_U0_Dbg_AWVALID_10_UNCONNECTED), + .Dbg_AWVALID_11(NLW_U0_Dbg_AWVALID_11_UNCONNECTED), + .Dbg_AWVALID_12(NLW_U0_Dbg_AWVALID_12_UNCONNECTED), + .Dbg_AWVALID_13(NLW_U0_Dbg_AWVALID_13_UNCONNECTED), + .Dbg_AWVALID_14(NLW_U0_Dbg_AWVALID_14_UNCONNECTED), + .Dbg_AWVALID_15(NLW_U0_Dbg_AWVALID_15_UNCONNECTED), + .Dbg_AWVALID_16(NLW_U0_Dbg_AWVALID_16_UNCONNECTED), + .Dbg_AWVALID_17(NLW_U0_Dbg_AWVALID_17_UNCONNECTED), + .Dbg_AWVALID_18(NLW_U0_Dbg_AWVALID_18_UNCONNECTED), + .Dbg_AWVALID_19(NLW_U0_Dbg_AWVALID_19_UNCONNECTED), + .Dbg_AWVALID_2(NLW_U0_Dbg_AWVALID_2_UNCONNECTED), + .Dbg_AWVALID_20(NLW_U0_Dbg_AWVALID_20_UNCONNECTED), + .Dbg_AWVALID_21(NLW_U0_Dbg_AWVALID_21_UNCONNECTED), + .Dbg_AWVALID_22(NLW_U0_Dbg_AWVALID_22_UNCONNECTED), + .Dbg_AWVALID_23(NLW_U0_Dbg_AWVALID_23_UNCONNECTED), + .Dbg_AWVALID_24(NLW_U0_Dbg_AWVALID_24_UNCONNECTED), + .Dbg_AWVALID_25(NLW_U0_Dbg_AWVALID_25_UNCONNECTED), + .Dbg_AWVALID_26(NLW_U0_Dbg_AWVALID_26_UNCONNECTED), + .Dbg_AWVALID_27(NLW_U0_Dbg_AWVALID_27_UNCONNECTED), + .Dbg_AWVALID_28(NLW_U0_Dbg_AWVALID_28_UNCONNECTED), + .Dbg_AWVALID_29(NLW_U0_Dbg_AWVALID_29_UNCONNECTED), + .Dbg_AWVALID_3(NLW_U0_Dbg_AWVALID_3_UNCONNECTED), + .Dbg_AWVALID_30(NLW_U0_Dbg_AWVALID_30_UNCONNECTED), + .Dbg_AWVALID_31(NLW_U0_Dbg_AWVALID_31_UNCONNECTED), + .Dbg_AWVALID_4(NLW_U0_Dbg_AWVALID_4_UNCONNECTED), + .Dbg_AWVALID_5(NLW_U0_Dbg_AWVALID_5_UNCONNECTED), + .Dbg_AWVALID_6(NLW_U0_Dbg_AWVALID_6_UNCONNECTED), + .Dbg_AWVALID_7(NLW_U0_Dbg_AWVALID_7_UNCONNECTED), + .Dbg_AWVALID_8(NLW_U0_Dbg_AWVALID_8_UNCONNECTED), + .Dbg_AWVALID_9(NLW_U0_Dbg_AWVALID_9_UNCONNECTED), + .Dbg_BREADY_0(NLW_U0_Dbg_BREADY_0_UNCONNECTED), + .Dbg_BREADY_1(NLW_U0_Dbg_BREADY_1_UNCONNECTED), + .Dbg_BREADY_10(NLW_U0_Dbg_BREADY_10_UNCONNECTED), + .Dbg_BREADY_11(NLW_U0_Dbg_BREADY_11_UNCONNECTED), + .Dbg_BREADY_12(NLW_U0_Dbg_BREADY_12_UNCONNECTED), + .Dbg_BREADY_13(NLW_U0_Dbg_BREADY_13_UNCONNECTED), + .Dbg_BREADY_14(NLW_U0_Dbg_BREADY_14_UNCONNECTED), + .Dbg_BREADY_15(NLW_U0_Dbg_BREADY_15_UNCONNECTED), + .Dbg_BREADY_16(NLW_U0_Dbg_BREADY_16_UNCONNECTED), + .Dbg_BREADY_17(NLW_U0_Dbg_BREADY_17_UNCONNECTED), + .Dbg_BREADY_18(NLW_U0_Dbg_BREADY_18_UNCONNECTED), + .Dbg_BREADY_19(NLW_U0_Dbg_BREADY_19_UNCONNECTED), + .Dbg_BREADY_2(NLW_U0_Dbg_BREADY_2_UNCONNECTED), + .Dbg_BREADY_20(NLW_U0_Dbg_BREADY_20_UNCONNECTED), + .Dbg_BREADY_21(NLW_U0_Dbg_BREADY_21_UNCONNECTED), + .Dbg_BREADY_22(NLW_U0_Dbg_BREADY_22_UNCONNECTED), + .Dbg_BREADY_23(NLW_U0_Dbg_BREADY_23_UNCONNECTED), + .Dbg_BREADY_24(NLW_U0_Dbg_BREADY_24_UNCONNECTED), + .Dbg_BREADY_25(NLW_U0_Dbg_BREADY_25_UNCONNECTED), + .Dbg_BREADY_26(NLW_U0_Dbg_BREADY_26_UNCONNECTED), + .Dbg_BREADY_27(NLW_U0_Dbg_BREADY_27_UNCONNECTED), + .Dbg_BREADY_28(NLW_U0_Dbg_BREADY_28_UNCONNECTED), + .Dbg_BREADY_29(NLW_U0_Dbg_BREADY_29_UNCONNECTED), + .Dbg_BREADY_3(NLW_U0_Dbg_BREADY_3_UNCONNECTED), + .Dbg_BREADY_30(NLW_U0_Dbg_BREADY_30_UNCONNECTED), + .Dbg_BREADY_31(NLW_U0_Dbg_BREADY_31_UNCONNECTED), + .Dbg_BREADY_4(NLW_U0_Dbg_BREADY_4_UNCONNECTED), + .Dbg_BREADY_5(NLW_U0_Dbg_BREADY_5_UNCONNECTED), + .Dbg_BREADY_6(NLW_U0_Dbg_BREADY_6_UNCONNECTED), + .Dbg_BREADY_7(NLW_U0_Dbg_BREADY_7_UNCONNECTED), + .Dbg_BREADY_8(NLW_U0_Dbg_BREADY_8_UNCONNECTED), + .Dbg_BREADY_9(NLW_U0_Dbg_BREADY_9_UNCONNECTED), + .Dbg_BRESP_0({1'b0,1'b0}), + .Dbg_BRESP_1({1'b0,1'b0}), + .Dbg_BRESP_10({1'b0,1'b0}), + .Dbg_BRESP_11({1'b0,1'b0}), + .Dbg_BRESP_12({1'b0,1'b0}), + .Dbg_BRESP_13({1'b0,1'b0}), + .Dbg_BRESP_14({1'b0,1'b0}), + .Dbg_BRESP_15({1'b0,1'b0}), + .Dbg_BRESP_16({1'b0,1'b0}), + .Dbg_BRESP_17({1'b0,1'b0}), + .Dbg_BRESP_18({1'b0,1'b0}), + .Dbg_BRESP_19({1'b0,1'b0}), + .Dbg_BRESP_2({1'b0,1'b0}), + .Dbg_BRESP_20({1'b0,1'b0}), + .Dbg_BRESP_21({1'b0,1'b0}), + .Dbg_BRESP_22({1'b0,1'b0}), + .Dbg_BRESP_23({1'b0,1'b0}), + .Dbg_BRESP_24({1'b0,1'b0}), + .Dbg_BRESP_25({1'b0,1'b0}), + .Dbg_BRESP_26({1'b0,1'b0}), + .Dbg_BRESP_27({1'b0,1'b0}), + .Dbg_BRESP_28({1'b0,1'b0}), + .Dbg_BRESP_29({1'b0,1'b0}), + .Dbg_BRESP_3({1'b0,1'b0}), + .Dbg_BRESP_30({1'b0,1'b0}), + .Dbg_BRESP_31({1'b0,1'b0}), + .Dbg_BRESP_4({1'b0,1'b0}), + .Dbg_BRESP_5({1'b0,1'b0}), + .Dbg_BRESP_6({1'b0,1'b0}), + .Dbg_BRESP_7({1'b0,1'b0}), + .Dbg_BRESP_8({1'b0,1'b0}), + .Dbg_BRESP_9({1'b0,1'b0}), + .Dbg_BVALID_0(1'b0), + .Dbg_BVALID_1(1'b0), + .Dbg_BVALID_10(1'b0), + .Dbg_BVALID_11(1'b0), + .Dbg_BVALID_12(1'b0), + .Dbg_BVALID_13(1'b0), + .Dbg_BVALID_14(1'b0), + .Dbg_BVALID_15(1'b0), + .Dbg_BVALID_16(1'b0), + .Dbg_BVALID_17(1'b0), + .Dbg_BVALID_18(1'b0), + .Dbg_BVALID_19(1'b0), + .Dbg_BVALID_2(1'b0), + .Dbg_BVALID_20(1'b0), + .Dbg_BVALID_21(1'b0), + .Dbg_BVALID_22(1'b0), + .Dbg_BVALID_23(1'b0), + .Dbg_BVALID_24(1'b0), + .Dbg_BVALID_25(1'b0), + .Dbg_BVALID_26(1'b0), + .Dbg_BVALID_27(1'b0), + .Dbg_BVALID_28(1'b0), + .Dbg_BVALID_29(1'b0), + .Dbg_BVALID_3(1'b0), + .Dbg_BVALID_30(1'b0), + .Dbg_BVALID_31(1'b0), + .Dbg_BVALID_4(1'b0), + .Dbg_BVALID_5(1'b0), + .Dbg_BVALID_6(1'b0), + .Dbg_BVALID_7(1'b0), + .Dbg_BVALID_8(1'b0), + .Dbg_BVALID_9(1'b0), + .Dbg_Capture_0(Dbg_Capture_0), + .Dbg_Capture_1(NLW_U0_Dbg_Capture_1_UNCONNECTED), + .Dbg_Capture_10(NLW_U0_Dbg_Capture_10_UNCONNECTED), + .Dbg_Capture_11(NLW_U0_Dbg_Capture_11_UNCONNECTED), + .Dbg_Capture_12(NLW_U0_Dbg_Capture_12_UNCONNECTED), + .Dbg_Capture_13(NLW_U0_Dbg_Capture_13_UNCONNECTED), + .Dbg_Capture_14(NLW_U0_Dbg_Capture_14_UNCONNECTED), + .Dbg_Capture_15(NLW_U0_Dbg_Capture_15_UNCONNECTED), + .Dbg_Capture_16(NLW_U0_Dbg_Capture_16_UNCONNECTED), + .Dbg_Capture_17(NLW_U0_Dbg_Capture_17_UNCONNECTED), + .Dbg_Capture_18(NLW_U0_Dbg_Capture_18_UNCONNECTED), + .Dbg_Capture_19(NLW_U0_Dbg_Capture_19_UNCONNECTED), + .Dbg_Capture_2(NLW_U0_Dbg_Capture_2_UNCONNECTED), + .Dbg_Capture_20(NLW_U0_Dbg_Capture_20_UNCONNECTED), + .Dbg_Capture_21(NLW_U0_Dbg_Capture_21_UNCONNECTED), + .Dbg_Capture_22(NLW_U0_Dbg_Capture_22_UNCONNECTED), + .Dbg_Capture_23(NLW_U0_Dbg_Capture_23_UNCONNECTED), + .Dbg_Capture_24(NLW_U0_Dbg_Capture_24_UNCONNECTED), + .Dbg_Capture_25(NLW_U0_Dbg_Capture_25_UNCONNECTED), + .Dbg_Capture_26(NLW_U0_Dbg_Capture_26_UNCONNECTED), + .Dbg_Capture_27(NLW_U0_Dbg_Capture_27_UNCONNECTED), + .Dbg_Capture_28(NLW_U0_Dbg_Capture_28_UNCONNECTED), + .Dbg_Capture_29(NLW_U0_Dbg_Capture_29_UNCONNECTED), + .Dbg_Capture_3(NLW_U0_Dbg_Capture_3_UNCONNECTED), + .Dbg_Capture_30(NLW_U0_Dbg_Capture_30_UNCONNECTED), + .Dbg_Capture_31(NLW_U0_Dbg_Capture_31_UNCONNECTED), + .Dbg_Capture_4(NLW_U0_Dbg_Capture_4_UNCONNECTED), + .Dbg_Capture_5(NLW_U0_Dbg_Capture_5_UNCONNECTED), + .Dbg_Capture_6(NLW_U0_Dbg_Capture_6_UNCONNECTED), + .Dbg_Capture_7(NLW_U0_Dbg_Capture_7_UNCONNECTED), + .Dbg_Capture_8(NLW_U0_Dbg_Capture_8_UNCONNECTED), + .Dbg_Capture_9(NLW_U0_Dbg_Capture_9_UNCONNECTED), + .Dbg_Clk_0(Dbg_Clk_0), + .Dbg_Clk_1(NLW_U0_Dbg_Clk_1_UNCONNECTED), + .Dbg_Clk_10(NLW_U0_Dbg_Clk_10_UNCONNECTED), + .Dbg_Clk_11(NLW_U0_Dbg_Clk_11_UNCONNECTED), + .Dbg_Clk_12(NLW_U0_Dbg_Clk_12_UNCONNECTED), + .Dbg_Clk_13(NLW_U0_Dbg_Clk_13_UNCONNECTED), + .Dbg_Clk_14(NLW_U0_Dbg_Clk_14_UNCONNECTED), + .Dbg_Clk_15(NLW_U0_Dbg_Clk_15_UNCONNECTED), + .Dbg_Clk_16(NLW_U0_Dbg_Clk_16_UNCONNECTED), + .Dbg_Clk_17(NLW_U0_Dbg_Clk_17_UNCONNECTED), + .Dbg_Clk_18(NLW_U0_Dbg_Clk_18_UNCONNECTED), + .Dbg_Clk_19(NLW_U0_Dbg_Clk_19_UNCONNECTED), + .Dbg_Clk_2(NLW_U0_Dbg_Clk_2_UNCONNECTED), + .Dbg_Clk_20(NLW_U0_Dbg_Clk_20_UNCONNECTED), + .Dbg_Clk_21(NLW_U0_Dbg_Clk_21_UNCONNECTED), + .Dbg_Clk_22(NLW_U0_Dbg_Clk_22_UNCONNECTED), + .Dbg_Clk_23(NLW_U0_Dbg_Clk_23_UNCONNECTED), + .Dbg_Clk_24(NLW_U0_Dbg_Clk_24_UNCONNECTED), + .Dbg_Clk_25(NLW_U0_Dbg_Clk_25_UNCONNECTED), + .Dbg_Clk_26(NLW_U0_Dbg_Clk_26_UNCONNECTED), + .Dbg_Clk_27(NLW_U0_Dbg_Clk_27_UNCONNECTED), + .Dbg_Clk_28(NLW_U0_Dbg_Clk_28_UNCONNECTED), + .Dbg_Clk_29(NLW_U0_Dbg_Clk_29_UNCONNECTED), + .Dbg_Clk_3(NLW_U0_Dbg_Clk_3_UNCONNECTED), + .Dbg_Clk_30(NLW_U0_Dbg_Clk_30_UNCONNECTED), + .Dbg_Clk_31(NLW_U0_Dbg_Clk_31_UNCONNECTED), + .Dbg_Clk_4(NLW_U0_Dbg_Clk_4_UNCONNECTED), + .Dbg_Clk_5(NLW_U0_Dbg_Clk_5_UNCONNECTED), + .Dbg_Clk_6(NLW_U0_Dbg_Clk_6_UNCONNECTED), + .Dbg_Clk_7(NLW_U0_Dbg_Clk_7_UNCONNECTED), + .Dbg_Clk_8(NLW_U0_Dbg_Clk_8_UNCONNECTED), + .Dbg_Clk_9(NLW_U0_Dbg_Clk_9_UNCONNECTED), + .Dbg_Disable_0(Dbg_Disable_0), + .Dbg_Disable_1(NLW_U0_Dbg_Disable_1_UNCONNECTED), + .Dbg_Disable_10(NLW_U0_Dbg_Disable_10_UNCONNECTED), + .Dbg_Disable_11(NLW_U0_Dbg_Disable_11_UNCONNECTED), + .Dbg_Disable_12(NLW_U0_Dbg_Disable_12_UNCONNECTED), + .Dbg_Disable_13(NLW_U0_Dbg_Disable_13_UNCONNECTED), + .Dbg_Disable_14(NLW_U0_Dbg_Disable_14_UNCONNECTED), + .Dbg_Disable_15(NLW_U0_Dbg_Disable_15_UNCONNECTED), + .Dbg_Disable_16(NLW_U0_Dbg_Disable_16_UNCONNECTED), + .Dbg_Disable_17(NLW_U0_Dbg_Disable_17_UNCONNECTED), + .Dbg_Disable_18(NLW_U0_Dbg_Disable_18_UNCONNECTED), + .Dbg_Disable_19(NLW_U0_Dbg_Disable_19_UNCONNECTED), + .Dbg_Disable_2(NLW_U0_Dbg_Disable_2_UNCONNECTED), + .Dbg_Disable_20(NLW_U0_Dbg_Disable_20_UNCONNECTED), + .Dbg_Disable_21(NLW_U0_Dbg_Disable_21_UNCONNECTED), + .Dbg_Disable_22(NLW_U0_Dbg_Disable_22_UNCONNECTED), + .Dbg_Disable_23(NLW_U0_Dbg_Disable_23_UNCONNECTED), + .Dbg_Disable_24(NLW_U0_Dbg_Disable_24_UNCONNECTED), + .Dbg_Disable_25(NLW_U0_Dbg_Disable_25_UNCONNECTED), + .Dbg_Disable_26(NLW_U0_Dbg_Disable_26_UNCONNECTED), + .Dbg_Disable_27(NLW_U0_Dbg_Disable_27_UNCONNECTED), + .Dbg_Disable_28(NLW_U0_Dbg_Disable_28_UNCONNECTED), + .Dbg_Disable_29(NLW_U0_Dbg_Disable_29_UNCONNECTED), + .Dbg_Disable_3(NLW_U0_Dbg_Disable_3_UNCONNECTED), + .Dbg_Disable_30(NLW_U0_Dbg_Disable_30_UNCONNECTED), + .Dbg_Disable_31(NLW_U0_Dbg_Disable_31_UNCONNECTED), + .Dbg_Disable_4(NLW_U0_Dbg_Disable_4_UNCONNECTED), + .Dbg_Disable_5(NLW_U0_Dbg_Disable_5_UNCONNECTED), + .Dbg_Disable_6(NLW_U0_Dbg_Disable_6_UNCONNECTED), + .Dbg_Disable_7(NLW_U0_Dbg_Disable_7_UNCONNECTED), + .Dbg_Disable_8(NLW_U0_Dbg_Disable_8_UNCONNECTED), + .Dbg_Disable_9(NLW_U0_Dbg_Disable_9_UNCONNECTED), + .Dbg_RDATA_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RDATA_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_RREADY_0(NLW_U0_Dbg_RREADY_0_UNCONNECTED), + .Dbg_RREADY_1(NLW_U0_Dbg_RREADY_1_UNCONNECTED), + .Dbg_RREADY_10(NLW_U0_Dbg_RREADY_10_UNCONNECTED), + .Dbg_RREADY_11(NLW_U0_Dbg_RREADY_11_UNCONNECTED), + .Dbg_RREADY_12(NLW_U0_Dbg_RREADY_12_UNCONNECTED), + .Dbg_RREADY_13(NLW_U0_Dbg_RREADY_13_UNCONNECTED), + .Dbg_RREADY_14(NLW_U0_Dbg_RREADY_14_UNCONNECTED), + .Dbg_RREADY_15(NLW_U0_Dbg_RREADY_15_UNCONNECTED), + .Dbg_RREADY_16(NLW_U0_Dbg_RREADY_16_UNCONNECTED), + .Dbg_RREADY_17(NLW_U0_Dbg_RREADY_17_UNCONNECTED), + .Dbg_RREADY_18(NLW_U0_Dbg_RREADY_18_UNCONNECTED), + .Dbg_RREADY_19(NLW_U0_Dbg_RREADY_19_UNCONNECTED), + .Dbg_RREADY_2(NLW_U0_Dbg_RREADY_2_UNCONNECTED), + .Dbg_RREADY_20(NLW_U0_Dbg_RREADY_20_UNCONNECTED), + .Dbg_RREADY_21(NLW_U0_Dbg_RREADY_21_UNCONNECTED), + .Dbg_RREADY_22(NLW_U0_Dbg_RREADY_22_UNCONNECTED), + .Dbg_RREADY_23(NLW_U0_Dbg_RREADY_23_UNCONNECTED), + .Dbg_RREADY_24(NLW_U0_Dbg_RREADY_24_UNCONNECTED), + .Dbg_RREADY_25(NLW_U0_Dbg_RREADY_25_UNCONNECTED), + .Dbg_RREADY_26(NLW_U0_Dbg_RREADY_26_UNCONNECTED), + .Dbg_RREADY_27(NLW_U0_Dbg_RREADY_27_UNCONNECTED), + .Dbg_RREADY_28(NLW_U0_Dbg_RREADY_28_UNCONNECTED), + .Dbg_RREADY_29(NLW_U0_Dbg_RREADY_29_UNCONNECTED), + .Dbg_RREADY_3(NLW_U0_Dbg_RREADY_3_UNCONNECTED), + .Dbg_RREADY_30(NLW_U0_Dbg_RREADY_30_UNCONNECTED), + .Dbg_RREADY_31(NLW_U0_Dbg_RREADY_31_UNCONNECTED), + .Dbg_RREADY_4(NLW_U0_Dbg_RREADY_4_UNCONNECTED), + .Dbg_RREADY_5(NLW_U0_Dbg_RREADY_5_UNCONNECTED), + .Dbg_RREADY_6(NLW_U0_Dbg_RREADY_6_UNCONNECTED), + .Dbg_RREADY_7(NLW_U0_Dbg_RREADY_7_UNCONNECTED), + .Dbg_RREADY_8(NLW_U0_Dbg_RREADY_8_UNCONNECTED), + .Dbg_RREADY_9(NLW_U0_Dbg_RREADY_9_UNCONNECTED), + .Dbg_RRESP_0({1'b0,1'b0}), + .Dbg_RRESP_1({1'b0,1'b0}), + .Dbg_RRESP_10({1'b0,1'b0}), + .Dbg_RRESP_11({1'b0,1'b0}), + .Dbg_RRESP_12({1'b0,1'b0}), + .Dbg_RRESP_13({1'b0,1'b0}), + .Dbg_RRESP_14({1'b0,1'b0}), + .Dbg_RRESP_15({1'b0,1'b0}), + .Dbg_RRESP_16({1'b0,1'b0}), + .Dbg_RRESP_17({1'b0,1'b0}), + .Dbg_RRESP_18({1'b0,1'b0}), + .Dbg_RRESP_19({1'b0,1'b0}), + .Dbg_RRESP_2({1'b0,1'b0}), + .Dbg_RRESP_20({1'b0,1'b0}), + .Dbg_RRESP_21({1'b0,1'b0}), + .Dbg_RRESP_22({1'b0,1'b0}), + .Dbg_RRESP_23({1'b0,1'b0}), + .Dbg_RRESP_24({1'b0,1'b0}), + .Dbg_RRESP_25({1'b0,1'b0}), + .Dbg_RRESP_26({1'b0,1'b0}), + .Dbg_RRESP_27({1'b0,1'b0}), + .Dbg_RRESP_28({1'b0,1'b0}), + .Dbg_RRESP_29({1'b0,1'b0}), + .Dbg_RRESP_3({1'b0,1'b0}), + .Dbg_RRESP_30({1'b0,1'b0}), + .Dbg_RRESP_31({1'b0,1'b0}), + .Dbg_RRESP_4({1'b0,1'b0}), + .Dbg_RRESP_5({1'b0,1'b0}), + .Dbg_RRESP_6({1'b0,1'b0}), + .Dbg_RRESP_7({1'b0,1'b0}), + .Dbg_RRESP_8({1'b0,1'b0}), + .Dbg_RRESP_9({1'b0,1'b0}), + .Dbg_RVALID_0(1'b0), + .Dbg_RVALID_1(1'b0), + .Dbg_RVALID_10(1'b0), + .Dbg_RVALID_11(1'b0), + .Dbg_RVALID_12(1'b0), + .Dbg_RVALID_13(1'b0), + .Dbg_RVALID_14(1'b0), + .Dbg_RVALID_15(1'b0), + .Dbg_RVALID_16(1'b0), + .Dbg_RVALID_17(1'b0), + .Dbg_RVALID_18(1'b0), + .Dbg_RVALID_19(1'b0), + .Dbg_RVALID_2(1'b0), + .Dbg_RVALID_20(1'b0), + .Dbg_RVALID_21(1'b0), + .Dbg_RVALID_22(1'b0), + .Dbg_RVALID_23(1'b0), + .Dbg_RVALID_24(1'b0), + .Dbg_RVALID_25(1'b0), + .Dbg_RVALID_26(1'b0), + .Dbg_RVALID_27(1'b0), + .Dbg_RVALID_28(1'b0), + .Dbg_RVALID_29(1'b0), + .Dbg_RVALID_3(1'b0), + .Dbg_RVALID_30(1'b0), + .Dbg_RVALID_31(1'b0), + .Dbg_RVALID_4(1'b0), + .Dbg_RVALID_5(1'b0), + .Dbg_RVALID_6(1'b0), + .Dbg_RVALID_7(1'b0), + .Dbg_RVALID_8(1'b0), + .Dbg_RVALID_9(1'b0), + .Dbg_Reg_En_0(Dbg_Reg_En_0), + .Dbg_Reg_En_1(NLW_U0_Dbg_Reg_En_1_UNCONNECTED[0:7]), + .Dbg_Reg_En_10(NLW_U0_Dbg_Reg_En_10_UNCONNECTED[0:7]), + .Dbg_Reg_En_11(NLW_U0_Dbg_Reg_En_11_UNCONNECTED[0:7]), + .Dbg_Reg_En_12(NLW_U0_Dbg_Reg_En_12_UNCONNECTED[0:7]), + .Dbg_Reg_En_13(NLW_U0_Dbg_Reg_En_13_UNCONNECTED[0:7]), + .Dbg_Reg_En_14(NLW_U0_Dbg_Reg_En_14_UNCONNECTED[0:7]), + .Dbg_Reg_En_15(NLW_U0_Dbg_Reg_En_15_UNCONNECTED[0:7]), + .Dbg_Reg_En_16(NLW_U0_Dbg_Reg_En_16_UNCONNECTED[0:7]), + .Dbg_Reg_En_17(NLW_U0_Dbg_Reg_En_17_UNCONNECTED[0:7]), + .Dbg_Reg_En_18(NLW_U0_Dbg_Reg_En_18_UNCONNECTED[0:7]), + .Dbg_Reg_En_19(NLW_U0_Dbg_Reg_En_19_UNCONNECTED[0:7]), + .Dbg_Reg_En_2(NLW_U0_Dbg_Reg_En_2_UNCONNECTED[0:7]), + .Dbg_Reg_En_20(NLW_U0_Dbg_Reg_En_20_UNCONNECTED[0:7]), + .Dbg_Reg_En_21(NLW_U0_Dbg_Reg_En_21_UNCONNECTED[0:7]), + .Dbg_Reg_En_22(NLW_U0_Dbg_Reg_En_22_UNCONNECTED[0:7]), + .Dbg_Reg_En_23(NLW_U0_Dbg_Reg_En_23_UNCONNECTED[0:7]), + .Dbg_Reg_En_24(NLW_U0_Dbg_Reg_En_24_UNCONNECTED[0:7]), + .Dbg_Reg_En_25(NLW_U0_Dbg_Reg_En_25_UNCONNECTED[0:7]), + .Dbg_Reg_En_26(NLW_U0_Dbg_Reg_En_26_UNCONNECTED[0:7]), + .Dbg_Reg_En_27(NLW_U0_Dbg_Reg_En_27_UNCONNECTED[0:7]), + .Dbg_Reg_En_28(NLW_U0_Dbg_Reg_En_28_UNCONNECTED[0:7]), + .Dbg_Reg_En_29(NLW_U0_Dbg_Reg_En_29_UNCONNECTED[0:7]), + .Dbg_Reg_En_3(NLW_U0_Dbg_Reg_En_3_UNCONNECTED[0:7]), + .Dbg_Reg_En_30(NLW_U0_Dbg_Reg_En_30_UNCONNECTED[0:7]), + .Dbg_Reg_En_31(NLW_U0_Dbg_Reg_En_31_UNCONNECTED[0:7]), + .Dbg_Reg_En_4(NLW_U0_Dbg_Reg_En_4_UNCONNECTED[0:7]), + .Dbg_Reg_En_5(NLW_U0_Dbg_Reg_En_5_UNCONNECTED[0:7]), + .Dbg_Reg_En_6(NLW_U0_Dbg_Reg_En_6_UNCONNECTED[0:7]), + .Dbg_Reg_En_7(NLW_U0_Dbg_Reg_En_7_UNCONNECTED[0:7]), + .Dbg_Reg_En_8(NLW_U0_Dbg_Reg_En_8_UNCONNECTED[0:7]), + .Dbg_Reg_En_9(NLW_U0_Dbg_Reg_En_9_UNCONNECTED[0:7]), + .Dbg_Rst_0(Dbg_Rst_0), + .Dbg_Rst_1(NLW_U0_Dbg_Rst_1_UNCONNECTED), + .Dbg_Rst_10(NLW_U0_Dbg_Rst_10_UNCONNECTED), + .Dbg_Rst_11(NLW_U0_Dbg_Rst_11_UNCONNECTED), + .Dbg_Rst_12(NLW_U0_Dbg_Rst_12_UNCONNECTED), + .Dbg_Rst_13(NLW_U0_Dbg_Rst_13_UNCONNECTED), + .Dbg_Rst_14(NLW_U0_Dbg_Rst_14_UNCONNECTED), + .Dbg_Rst_15(NLW_U0_Dbg_Rst_15_UNCONNECTED), + .Dbg_Rst_16(NLW_U0_Dbg_Rst_16_UNCONNECTED), + .Dbg_Rst_17(NLW_U0_Dbg_Rst_17_UNCONNECTED), + .Dbg_Rst_18(NLW_U0_Dbg_Rst_18_UNCONNECTED), + .Dbg_Rst_19(NLW_U0_Dbg_Rst_19_UNCONNECTED), + .Dbg_Rst_2(NLW_U0_Dbg_Rst_2_UNCONNECTED), + .Dbg_Rst_20(NLW_U0_Dbg_Rst_20_UNCONNECTED), + .Dbg_Rst_21(NLW_U0_Dbg_Rst_21_UNCONNECTED), + .Dbg_Rst_22(NLW_U0_Dbg_Rst_22_UNCONNECTED), + .Dbg_Rst_23(NLW_U0_Dbg_Rst_23_UNCONNECTED), + .Dbg_Rst_24(NLW_U0_Dbg_Rst_24_UNCONNECTED), + .Dbg_Rst_25(NLW_U0_Dbg_Rst_25_UNCONNECTED), + .Dbg_Rst_26(NLW_U0_Dbg_Rst_26_UNCONNECTED), + .Dbg_Rst_27(NLW_U0_Dbg_Rst_27_UNCONNECTED), + .Dbg_Rst_28(NLW_U0_Dbg_Rst_28_UNCONNECTED), + .Dbg_Rst_29(NLW_U0_Dbg_Rst_29_UNCONNECTED), + .Dbg_Rst_3(NLW_U0_Dbg_Rst_3_UNCONNECTED), + .Dbg_Rst_30(NLW_U0_Dbg_Rst_30_UNCONNECTED), + .Dbg_Rst_31(NLW_U0_Dbg_Rst_31_UNCONNECTED), + .Dbg_Rst_4(NLW_U0_Dbg_Rst_4_UNCONNECTED), + .Dbg_Rst_5(NLW_U0_Dbg_Rst_5_UNCONNECTED), + .Dbg_Rst_6(NLW_U0_Dbg_Rst_6_UNCONNECTED), + .Dbg_Rst_7(NLW_U0_Dbg_Rst_7_UNCONNECTED), + .Dbg_Rst_8(NLW_U0_Dbg_Rst_8_UNCONNECTED), + .Dbg_Rst_9(NLW_U0_Dbg_Rst_9_UNCONNECTED), + .Dbg_Shift_0(Dbg_Shift_0), + .Dbg_Shift_1(NLW_U0_Dbg_Shift_1_UNCONNECTED), + .Dbg_Shift_10(NLW_U0_Dbg_Shift_10_UNCONNECTED), + .Dbg_Shift_11(NLW_U0_Dbg_Shift_11_UNCONNECTED), + .Dbg_Shift_12(NLW_U0_Dbg_Shift_12_UNCONNECTED), + .Dbg_Shift_13(NLW_U0_Dbg_Shift_13_UNCONNECTED), + .Dbg_Shift_14(NLW_U0_Dbg_Shift_14_UNCONNECTED), + .Dbg_Shift_15(NLW_U0_Dbg_Shift_15_UNCONNECTED), + .Dbg_Shift_16(NLW_U0_Dbg_Shift_16_UNCONNECTED), + .Dbg_Shift_17(NLW_U0_Dbg_Shift_17_UNCONNECTED), + .Dbg_Shift_18(NLW_U0_Dbg_Shift_18_UNCONNECTED), + .Dbg_Shift_19(NLW_U0_Dbg_Shift_19_UNCONNECTED), + .Dbg_Shift_2(NLW_U0_Dbg_Shift_2_UNCONNECTED), + .Dbg_Shift_20(NLW_U0_Dbg_Shift_20_UNCONNECTED), + .Dbg_Shift_21(NLW_U0_Dbg_Shift_21_UNCONNECTED), + .Dbg_Shift_22(NLW_U0_Dbg_Shift_22_UNCONNECTED), + .Dbg_Shift_23(NLW_U0_Dbg_Shift_23_UNCONNECTED), + .Dbg_Shift_24(NLW_U0_Dbg_Shift_24_UNCONNECTED), + .Dbg_Shift_25(NLW_U0_Dbg_Shift_25_UNCONNECTED), + .Dbg_Shift_26(NLW_U0_Dbg_Shift_26_UNCONNECTED), + .Dbg_Shift_27(NLW_U0_Dbg_Shift_27_UNCONNECTED), + .Dbg_Shift_28(NLW_U0_Dbg_Shift_28_UNCONNECTED), + .Dbg_Shift_29(NLW_U0_Dbg_Shift_29_UNCONNECTED), + .Dbg_Shift_3(NLW_U0_Dbg_Shift_3_UNCONNECTED), + .Dbg_Shift_30(NLW_U0_Dbg_Shift_30_UNCONNECTED), + .Dbg_Shift_31(NLW_U0_Dbg_Shift_31_UNCONNECTED), + .Dbg_Shift_4(NLW_U0_Dbg_Shift_4_UNCONNECTED), + .Dbg_Shift_5(NLW_U0_Dbg_Shift_5_UNCONNECTED), + .Dbg_Shift_6(NLW_U0_Dbg_Shift_6_UNCONNECTED), + .Dbg_Shift_7(NLW_U0_Dbg_Shift_7_UNCONNECTED), + .Dbg_Shift_8(NLW_U0_Dbg_Shift_8_UNCONNECTED), + .Dbg_Shift_9(NLW_U0_Dbg_Shift_9_UNCONNECTED), + .Dbg_TDI_0(Dbg_TDI_0), + .Dbg_TDI_1(NLW_U0_Dbg_TDI_1_UNCONNECTED), + .Dbg_TDI_10(NLW_U0_Dbg_TDI_10_UNCONNECTED), + .Dbg_TDI_11(NLW_U0_Dbg_TDI_11_UNCONNECTED), + .Dbg_TDI_12(NLW_U0_Dbg_TDI_12_UNCONNECTED), + .Dbg_TDI_13(NLW_U0_Dbg_TDI_13_UNCONNECTED), + .Dbg_TDI_14(NLW_U0_Dbg_TDI_14_UNCONNECTED), + .Dbg_TDI_15(NLW_U0_Dbg_TDI_15_UNCONNECTED), + .Dbg_TDI_16(NLW_U0_Dbg_TDI_16_UNCONNECTED), + .Dbg_TDI_17(NLW_U0_Dbg_TDI_17_UNCONNECTED), + .Dbg_TDI_18(NLW_U0_Dbg_TDI_18_UNCONNECTED), + .Dbg_TDI_19(NLW_U0_Dbg_TDI_19_UNCONNECTED), + .Dbg_TDI_2(NLW_U0_Dbg_TDI_2_UNCONNECTED), + .Dbg_TDI_20(NLW_U0_Dbg_TDI_20_UNCONNECTED), + .Dbg_TDI_21(NLW_U0_Dbg_TDI_21_UNCONNECTED), + .Dbg_TDI_22(NLW_U0_Dbg_TDI_22_UNCONNECTED), + .Dbg_TDI_23(NLW_U0_Dbg_TDI_23_UNCONNECTED), + .Dbg_TDI_24(NLW_U0_Dbg_TDI_24_UNCONNECTED), + .Dbg_TDI_25(NLW_U0_Dbg_TDI_25_UNCONNECTED), + .Dbg_TDI_26(NLW_U0_Dbg_TDI_26_UNCONNECTED), + .Dbg_TDI_27(NLW_U0_Dbg_TDI_27_UNCONNECTED), + .Dbg_TDI_28(NLW_U0_Dbg_TDI_28_UNCONNECTED), + .Dbg_TDI_29(NLW_U0_Dbg_TDI_29_UNCONNECTED), + .Dbg_TDI_3(NLW_U0_Dbg_TDI_3_UNCONNECTED), + .Dbg_TDI_30(NLW_U0_Dbg_TDI_30_UNCONNECTED), + .Dbg_TDI_31(NLW_U0_Dbg_TDI_31_UNCONNECTED), + .Dbg_TDI_4(NLW_U0_Dbg_TDI_4_UNCONNECTED), + .Dbg_TDI_5(NLW_U0_Dbg_TDI_5_UNCONNECTED), + .Dbg_TDI_6(NLW_U0_Dbg_TDI_6_UNCONNECTED), + .Dbg_TDI_7(NLW_U0_Dbg_TDI_7_UNCONNECTED), + .Dbg_TDI_8(NLW_U0_Dbg_TDI_8_UNCONNECTED), + .Dbg_TDI_9(NLW_U0_Dbg_TDI_9_UNCONNECTED), + .Dbg_TDO_0(Dbg_TDO_0), + .Dbg_TDO_1(1'b0), + .Dbg_TDO_10(1'b0), + .Dbg_TDO_11(1'b0), + .Dbg_TDO_12(1'b0), + .Dbg_TDO_13(1'b0), + .Dbg_TDO_14(1'b0), + .Dbg_TDO_15(1'b0), + .Dbg_TDO_16(1'b0), + .Dbg_TDO_17(1'b0), + .Dbg_TDO_18(1'b0), + .Dbg_TDO_19(1'b0), + .Dbg_TDO_2(1'b0), + .Dbg_TDO_20(1'b0), + .Dbg_TDO_21(1'b0), + .Dbg_TDO_22(1'b0), + .Dbg_TDO_23(1'b0), + .Dbg_TDO_24(1'b0), + .Dbg_TDO_25(1'b0), + .Dbg_TDO_26(1'b0), + .Dbg_TDO_27(1'b0), + .Dbg_TDO_28(1'b0), + .Dbg_TDO_29(1'b0), + .Dbg_TDO_3(1'b0), + .Dbg_TDO_30(1'b0), + .Dbg_TDO_31(1'b0), + .Dbg_TDO_4(1'b0), + .Dbg_TDO_5(1'b0), + .Dbg_TDO_6(1'b0), + .Dbg_TDO_7(1'b0), + .Dbg_TDO_8(1'b0), + .Dbg_TDO_9(1'b0), + .Dbg_TrClk_0(NLW_U0_Dbg_TrClk_0_UNCONNECTED), + .Dbg_TrClk_1(NLW_U0_Dbg_TrClk_1_UNCONNECTED), + .Dbg_TrClk_10(NLW_U0_Dbg_TrClk_10_UNCONNECTED), + .Dbg_TrClk_11(NLW_U0_Dbg_TrClk_11_UNCONNECTED), + .Dbg_TrClk_12(NLW_U0_Dbg_TrClk_12_UNCONNECTED), + .Dbg_TrClk_13(NLW_U0_Dbg_TrClk_13_UNCONNECTED), + .Dbg_TrClk_14(NLW_U0_Dbg_TrClk_14_UNCONNECTED), + .Dbg_TrClk_15(NLW_U0_Dbg_TrClk_15_UNCONNECTED), + .Dbg_TrClk_16(NLW_U0_Dbg_TrClk_16_UNCONNECTED), + .Dbg_TrClk_17(NLW_U0_Dbg_TrClk_17_UNCONNECTED), + .Dbg_TrClk_18(NLW_U0_Dbg_TrClk_18_UNCONNECTED), + .Dbg_TrClk_19(NLW_U0_Dbg_TrClk_19_UNCONNECTED), + .Dbg_TrClk_2(NLW_U0_Dbg_TrClk_2_UNCONNECTED), + .Dbg_TrClk_20(NLW_U0_Dbg_TrClk_20_UNCONNECTED), + .Dbg_TrClk_21(NLW_U0_Dbg_TrClk_21_UNCONNECTED), + .Dbg_TrClk_22(NLW_U0_Dbg_TrClk_22_UNCONNECTED), + .Dbg_TrClk_23(NLW_U0_Dbg_TrClk_23_UNCONNECTED), + .Dbg_TrClk_24(NLW_U0_Dbg_TrClk_24_UNCONNECTED), + .Dbg_TrClk_25(NLW_U0_Dbg_TrClk_25_UNCONNECTED), + .Dbg_TrClk_26(NLW_U0_Dbg_TrClk_26_UNCONNECTED), + .Dbg_TrClk_27(NLW_U0_Dbg_TrClk_27_UNCONNECTED), + .Dbg_TrClk_28(NLW_U0_Dbg_TrClk_28_UNCONNECTED), + .Dbg_TrClk_29(NLW_U0_Dbg_TrClk_29_UNCONNECTED), + .Dbg_TrClk_3(NLW_U0_Dbg_TrClk_3_UNCONNECTED), + .Dbg_TrClk_30(NLW_U0_Dbg_TrClk_30_UNCONNECTED), + .Dbg_TrClk_31(NLW_U0_Dbg_TrClk_31_UNCONNECTED), + .Dbg_TrClk_4(NLW_U0_Dbg_TrClk_4_UNCONNECTED), + .Dbg_TrClk_5(NLW_U0_Dbg_TrClk_5_UNCONNECTED), + .Dbg_TrClk_6(NLW_U0_Dbg_TrClk_6_UNCONNECTED), + .Dbg_TrClk_7(NLW_U0_Dbg_TrClk_7_UNCONNECTED), + .Dbg_TrClk_8(NLW_U0_Dbg_TrClk_8_UNCONNECTED), + .Dbg_TrClk_9(NLW_U0_Dbg_TrClk_9_UNCONNECTED), + .Dbg_TrData_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrData_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_TrReady_0(NLW_U0_Dbg_TrReady_0_UNCONNECTED), + .Dbg_TrReady_1(NLW_U0_Dbg_TrReady_1_UNCONNECTED), + .Dbg_TrReady_10(NLW_U0_Dbg_TrReady_10_UNCONNECTED), + .Dbg_TrReady_11(NLW_U0_Dbg_TrReady_11_UNCONNECTED), + .Dbg_TrReady_12(NLW_U0_Dbg_TrReady_12_UNCONNECTED), + .Dbg_TrReady_13(NLW_U0_Dbg_TrReady_13_UNCONNECTED), + .Dbg_TrReady_14(NLW_U0_Dbg_TrReady_14_UNCONNECTED), + .Dbg_TrReady_15(NLW_U0_Dbg_TrReady_15_UNCONNECTED), + .Dbg_TrReady_16(NLW_U0_Dbg_TrReady_16_UNCONNECTED), + .Dbg_TrReady_17(NLW_U0_Dbg_TrReady_17_UNCONNECTED), + .Dbg_TrReady_18(NLW_U0_Dbg_TrReady_18_UNCONNECTED), + .Dbg_TrReady_19(NLW_U0_Dbg_TrReady_19_UNCONNECTED), + .Dbg_TrReady_2(NLW_U0_Dbg_TrReady_2_UNCONNECTED), + .Dbg_TrReady_20(NLW_U0_Dbg_TrReady_20_UNCONNECTED), + .Dbg_TrReady_21(NLW_U0_Dbg_TrReady_21_UNCONNECTED), + .Dbg_TrReady_22(NLW_U0_Dbg_TrReady_22_UNCONNECTED), + .Dbg_TrReady_23(NLW_U0_Dbg_TrReady_23_UNCONNECTED), + .Dbg_TrReady_24(NLW_U0_Dbg_TrReady_24_UNCONNECTED), + .Dbg_TrReady_25(NLW_U0_Dbg_TrReady_25_UNCONNECTED), + .Dbg_TrReady_26(NLW_U0_Dbg_TrReady_26_UNCONNECTED), + .Dbg_TrReady_27(NLW_U0_Dbg_TrReady_27_UNCONNECTED), + .Dbg_TrReady_28(NLW_U0_Dbg_TrReady_28_UNCONNECTED), + .Dbg_TrReady_29(NLW_U0_Dbg_TrReady_29_UNCONNECTED), + .Dbg_TrReady_3(NLW_U0_Dbg_TrReady_3_UNCONNECTED), + .Dbg_TrReady_30(NLW_U0_Dbg_TrReady_30_UNCONNECTED), + .Dbg_TrReady_31(NLW_U0_Dbg_TrReady_31_UNCONNECTED), + .Dbg_TrReady_4(NLW_U0_Dbg_TrReady_4_UNCONNECTED), + .Dbg_TrReady_5(NLW_U0_Dbg_TrReady_5_UNCONNECTED), + .Dbg_TrReady_6(NLW_U0_Dbg_TrReady_6_UNCONNECTED), + .Dbg_TrReady_7(NLW_U0_Dbg_TrReady_7_UNCONNECTED), + .Dbg_TrReady_8(NLW_U0_Dbg_TrReady_8_UNCONNECTED), + .Dbg_TrReady_9(NLW_U0_Dbg_TrReady_9_UNCONNECTED), + .Dbg_TrValid_0(1'b0), + .Dbg_TrValid_1(1'b0), + .Dbg_TrValid_10(1'b0), + .Dbg_TrValid_11(1'b0), + .Dbg_TrValid_12(1'b0), + .Dbg_TrValid_13(1'b0), + .Dbg_TrValid_14(1'b0), + .Dbg_TrValid_15(1'b0), + .Dbg_TrValid_16(1'b0), + .Dbg_TrValid_17(1'b0), + .Dbg_TrValid_18(1'b0), + .Dbg_TrValid_19(1'b0), + .Dbg_TrValid_2(1'b0), + .Dbg_TrValid_20(1'b0), + .Dbg_TrValid_21(1'b0), + .Dbg_TrValid_22(1'b0), + .Dbg_TrValid_23(1'b0), + .Dbg_TrValid_24(1'b0), + .Dbg_TrValid_25(1'b0), + .Dbg_TrValid_26(1'b0), + .Dbg_TrValid_27(1'b0), + .Dbg_TrValid_28(1'b0), + .Dbg_TrValid_29(1'b0), + .Dbg_TrValid_3(1'b0), + .Dbg_TrValid_30(1'b0), + .Dbg_TrValid_31(1'b0), + .Dbg_TrValid_4(1'b0), + .Dbg_TrValid_5(1'b0), + .Dbg_TrValid_6(1'b0), + .Dbg_TrValid_7(1'b0), + .Dbg_TrValid_8(1'b0), + .Dbg_TrValid_9(1'b0), + .Dbg_Trig_Ack_In_0(NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_1(NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_10(NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_11(NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_12(NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_13(NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_14(NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_15(NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_16(NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_17(NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_18(NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_19(NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_2(NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_20(NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_21(NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_22(NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_23(NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_24(NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_25(NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_26(NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_27(NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_28(NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_29(NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_3(NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_30(NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_31(NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_4(NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_5(NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_6(NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_7(NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_8(NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_In_9(NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED[0:7]), + .Dbg_Trig_Ack_Out_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Ack_Out_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_In_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .Dbg_Trig_Out_0(NLW_U0_Dbg_Trig_Out_0_UNCONNECTED[0:7]), + .Dbg_Trig_Out_1(NLW_U0_Dbg_Trig_Out_1_UNCONNECTED[0:7]), + .Dbg_Trig_Out_10(NLW_U0_Dbg_Trig_Out_10_UNCONNECTED[0:7]), + .Dbg_Trig_Out_11(NLW_U0_Dbg_Trig_Out_11_UNCONNECTED[0:7]), + .Dbg_Trig_Out_12(NLW_U0_Dbg_Trig_Out_12_UNCONNECTED[0:7]), + .Dbg_Trig_Out_13(NLW_U0_Dbg_Trig_Out_13_UNCONNECTED[0:7]), + .Dbg_Trig_Out_14(NLW_U0_Dbg_Trig_Out_14_UNCONNECTED[0:7]), + .Dbg_Trig_Out_15(NLW_U0_Dbg_Trig_Out_15_UNCONNECTED[0:7]), + .Dbg_Trig_Out_16(NLW_U0_Dbg_Trig_Out_16_UNCONNECTED[0:7]), + .Dbg_Trig_Out_17(NLW_U0_Dbg_Trig_Out_17_UNCONNECTED[0:7]), + .Dbg_Trig_Out_18(NLW_U0_Dbg_Trig_Out_18_UNCONNECTED[0:7]), + .Dbg_Trig_Out_19(NLW_U0_Dbg_Trig_Out_19_UNCONNECTED[0:7]), + .Dbg_Trig_Out_2(NLW_U0_Dbg_Trig_Out_2_UNCONNECTED[0:7]), + .Dbg_Trig_Out_20(NLW_U0_Dbg_Trig_Out_20_UNCONNECTED[0:7]), + .Dbg_Trig_Out_21(NLW_U0_Dbg_Trig_Out_21_UNCONNECTED[0:7]), + .Dbg_Trig_Out_22(NLW_U0_Dbg_Trig_Out_22_UNCONNECTED[0:7]), + .Dbg_Trig_Out_23(NLW_U0_Dbg_Trig_Out_23_UNCONNECTED[0:7]), + .Dbg_Trig_Out_24(NLW_U0_Dbg_Trig_Out_24_UNCONNECTED[0:7]), + .Dbg_Trig_Out_25(NLW_U0_Dbg_Trig_Out_25_UNCONNECTED[0:7]), + .Dbg_Trig_Out_26(NLW_U0_Dbg_Trig_Out_26_UNCONNECTED[0:7]), + .Dbg_Trig_Out_27(NLW_U0_Dbg_Trig_Out_27_UNCONNECTED[0:7]), + .Dbg_Trig_Out_28(NLW_U0_Dbg_Trig_Out_28_UNCONNECTED[0:7]), + .Dbg_Trig_Out_29(NLW_U0_Dbg_Trig_Out_29_UNCONNECTED[0:7]), + .Dbg_Trig_Out_3(NLW_U0_Dbg_Trig_Out_3_UNCONNECTED[0:7]), + .Dbg_Trig_Out_30(NLW_U0_Dbg_Trig_Out_30_UNCONNECTED[0:7]), + .Dbg_Trig_Out_31(NLW_U0_Dbg_Trig_Out_31_UNCONNECTED[0:7]), + .Dbg_Trig_Out_4(NLW_U0_Dbg_Trig_Out_4_UNCONNECTED[0:7]), + .Dbg_Trig_Out_5(NLW_U0_Dbg_Trig_Out_5_UNCONNECTED[0:7]), + .Dbg_Trig_Out_6(NLW_U0_Dbg_Trig_Out_6_UNCONNECTED[0:7]), + .Dbg_Trig_Out_7(NLW_U0_Dbg_Trig_Out_7_UNCONNECTED[0:7]), + .Dbg_Trig_Out_8(NLW_U0_Dbg_Trig_Out_8_UNCONNECTED[0:7]), + .Dbg_Trig_Out_9(NLW_U0_Dbg_Trig_Out_9_UNCONNECTED[0:7]), + .Dbg_Update_0(Dbg_Update_0), + .Dbg_Update_1(NLW_U0_Dbg_Update_1_UNCONNECTED), + .Dbg_Update_10(NLW_U0_Dbg_Update_10_UNCONNECTED), + .Dbg_Update_11(NLW_U0_Dbg_Update_11_UNCONNECTED), + .Dbg_Update_12(NLW_U0_Dbg_Update_12_UNCONNECTED), + .Dbg_Update_13(NLW_U0_Dbg_Update_13_UNCONNECTED), + .Dbg_Update_14(NLW_U0_Dbg_Update_14_UNCONNECTED), + .Dbg_Update_15(NLW_U0_Dbg_Update_15_UNCONNECTED), + .Dbg_Update_16(NLW_U0_Dbg_Update_16_UNCONNECTED), + .Dbg_Update_17(NLW_U0_Dbg_Update_17_UNCONNECTED), + .Dbg_Update_18(NLW_U0_Dbg_Update_18_UNCONNECTED), + .Dbg_Update_19(NLW_U0_Dbg_Update_19_UNCONNECTED), + .Dbg_Update_2(NLW_U0_Dbg_Update_2_UNCONNECTED), + .Dbg_Update_20(NLW_U0_Dbg_Update_20_UNCONNECTED), + .Dbg_Update_21(NLW_U0_Dbg_Update_21_UNCONNECTED), + .Dbg_Update_22(NLW_U0_Dbg_Update_22_UNCONNECTED), + .Dbg_Update_23(NLW_U0_Dbg_Update_23_UNCONNECTED), + .Dbg_Update_24(NLW_U0_Dbg_Update_24_UNCONNECTED), + .Dbg_Update_25(NLW_U0_Dbg_Update_25_UNCONNECTED), + .Dbg_Update_26(NLW_U0_Dbg_Update_26_UNCONNECTED), + .Dbg_Update_27(NLW_U0_Dbg_Update_27_UNCONNECTED), + .Dbg_Update_28(NLW_U0_Dbg_Update_28_UNCONNECTED), + .Dbg_Update_29(NLW_U0_Dbg_Update_29_UNCONNECTED), + .Dbg_Update_3(NLW_U0_Dbg_Update_3_UNCONNECTED), + .Dbg_Update_30(NLW_U0_Dbg_Update_30_UNCONNECTED), + .Dbg_Update_31(NLW_U0_Dbg_Update_31_UNCONNECTED), + .Dbg_Update_4(NLW_U0_Dbg_Update_4_UNCONNECTED), + .Dbg_Update_5(NLW_U0_Dbg_Update_5_UNCONNECTED), + .Dbg_Update_6(NLW_U0_Dbg_Update_6_UNCONNECTED), + .Dbg_Update_7(NLW_U0_Dbg_Update_7_UNCONNECTED), + .Dbg_Update_8(NLW_U0_Dbg_Update_8_UNCONNECTED), + .Dbg_Update_9(NLW_U0_Dbg_Update_9_UNCONNECTED), + .Dbg_WDATA_0(NLW_U0_Dbg_WDATA_0_UNCONNECTED[31:0]), + .Dbg_WDATA_1(NLW_U0_Dbg_WDATA_1_UNCONNECTED[31:0]), + .Dbg_WDATA_10(NLW_U0_Dbg_WDATA_10_UNCONNECTED[31:0]), + .Dbg_WDATA_11(NLW_U0_Dbg_WDATA_11_UNCONNECTED[31:0]), + .Dbg_WDATA_12(NLW_U0_Dbg_WDATA_12_UNCONNECTED[31:0]), + .Dbg_WDATA_13(NLW_U0_Dbg_WDATA_13_UNCONNECTED[31:0]), + .Dbg_WDATA_14(NLW_U0_Dbg_WDATA_14_UNCONNECTED[31:0]), + .Dbg_WDATA_15(NLW_U0_Dbg_WDATA_15_UNCONNECTED[31:0]), + .Dbg_WDATA_16(NLW_U0_Dbg_WDATA_16_UNCONNECTED[31:0]), + .Dbg_WDATA_17(NLW_U0_Dbg_WDATA_17_UNCONNECTED[31:0]), + .Dbg_WDATA_18(NLW_U0_Dbg_WDATA_18_UNCONNECTED[31:0]), + .Dbg_WDATA_19(NLW_U0_Dbg_WDATA_19_UNCONNECTED[31:0]), + .Dbg_WDATA_2(NLW_U0_Dbg_WDATA_2_UNCONNECTED[31:0]), + .Dbg_WDATA_20(NLW_U0_Dbg_WDATA_20_UNCONNECTED[31:0]), + .Dbg_WDATA_21(NLW_U0_Dbg_WDATA_21_UNCONNECTED[31:0]), + .Dbg_WDATA_22(NLW_U0_Dbg_WDATA_22_UNCONNECTED[31:0]), + .Dbg_WDATA_23(NLW_U0_Dbg_WDATA_23_UNCONNECTED[31:0]), + .Dbg_WDATA_24(NLW_U0_Dbg_WDATA_24_UNCONNECTED[31:0]), + .Dbg_WDATA_25(NLW_U0_Dbg_WDATA_25_UNCONNECTED[31:0]), + .Dbg_WDATA_26(NLW_U0_Dbg_WDATA_26_UNCONNECTED[31:0]), + .Dbg_WDATA_27(NLW_U0_Dbg_WDATA_27_UNCONNECTED[31:0]), + .Dbg_WDATA_28(NLW_U0_Dbg_WDATA_28_UNCONNECTED[31:0]), + .Dbg_WDATA_29(NLW_U0_Dbg_WDATA_29_UNCONNECTED[31:0]), + .Dbg_WDATA_3(NLW_U0_Dbg_WDATA_3_UNCONNECTED[31:0]), + .Dbg_WDATA_30(NLW_U0_Dbg_WDATA_30_UNCONNECTED[31:0]), + .Dbg_WDATA_31(NLW_U0_Dbg_WDATA_31_UNCONNECTED[31:0]), + .Dbg_WDATA_4(NLW_U0_Dbg_WDATA_4_UNCONNECTED[31:0]), + .Dbg_WDATA_5(NLW_U0_Dbg_WDATA_5_UNCONNECTED[31:0]), + .Dbg_WDATA_6(NLW_U0_Dbg_WDATA_6_UNCONNECTED[31:0]), + .Dbg_WDATA_7(NLW_U0_Dbg_WDATA_7_UNCONNECTED[31:0]), + .Dbg_WDATA_8(NLW_U0_Dbg_WDATA_8_UNCONNECTED[31:0]), + .Dbg_WDATA_9(NLW_U0_Dbg_WDATA_9_UNCONNECTED[31:0]), + .Dbg_WREADY_0(1'b0), + .Dbg_WREADY_1(1'b0), + .Dbg_WREADY_10(1'b0), + .Dbg_WREADY_11(1'b0), + .Dbg_WREADY_12(1'b0), + .Dbg_WREADY_13(1'b0), + .Dbg_WREADY_14(1'b0), + .Dbg_WREADY_15(1'b0), + .Dbg_WREADY_16(1'b0), + .Dbg_WREADY_17(1'b0), + .Dbg_WREADY_18(1'b0), + .Dbg_WREADY_19(1'b0), + .Dbg_WREADY_2(1'b0), + .Dbg_WREADY_20(1'b0), + .Dbg_WREADY_21(1'b0), + .Dbg_WREADY_22(1'b0), + .Dbg_WREADY_23(1'b0), + .Dbg_WREADY_24(1'b0), + .Dbg_WREADY_25(1'b0), + .Dbg_WREADY_26(1'b0), + .Dbg_WREADY_27(1'b0), + .Dbg_WREADY_28(1'b0), + .Dbg_WREADY_29(1'b0), + .Dbg_WREADY_3(1'b0), + .Dbg_WREADY_30(1'b0), + .Dbg_WREADY_31(1'b0), + .Dbg_WREADY_4(1'b0), + .Dbg_WREADY_5(1'b0), + .Dbg_WREADY_6(1'b0), + .Dbg_WREADY_7(1'b0), + .Dbg_WREADY_8(1'b0), + .Dbg_WREADY_9(1'b0), + .Dbg_WVALID_0(NLW_U0_Dbg_WVALID_0_UNCONNECTED), + .Dbg_WVALID_1(NLW_U0_Dbg_WVALID_1_UNCONNECTED), + .Dbg_WVALID_10(NLW_U0_Dbg_WVALID_10_UNCONNECTED), + .Dbg_WVALID_11(NLW_U0_Dbg_WVALID_11_UNCONNECTED), + .Dbg_WVALID_12(NLW_U0_Dbg_WVALID_12_UNCONNECTED), + .Dbg_WVALID_13(NLW_U0_Dbg_WVALID_13_UNCONNECTED), + .Dbg_WVALID_14(NLW_U0_Dbg_WVALID_14_UNCONNECTED), + .Dbg_WVALID_15(NLW_U0_Dbg_WVALID_15_UNCONNECTED), + .Dbg_WVALID_16(NLW_U0_Dbg_WVALID_16_UNCONNECTED), + .Dbg_WVALID_17(NLW_U0_Dbg_WVALID_17_UNCONNECTED), + .Dbg_WVALID_18(NLW_U0_Dbg_WVALID_18_UNCONNECTED), + .Dbg_WVALID_19(NLW_U0_Dbg_WVALID_19_UNCONNECTED), + .Dbg_WVALID_2(NLW_U0_Dbg_WVALID_2_UNCONNECTED), + .Dbg_WVALID_20(NLW_U0_Dbg_WVALID_20_UNCONNECTED), + .Dbg_WVALID_21(NLW_U0_Dbg_WVALID_21_UNCONNECTED), + .Dbg_WVALID_22(NLW_U0_Dbg_WVALID_22_UNCONNECTED), + .Dbg_WVALID_23(NLW_U0_Dbg_WVALID_23_UNCONNECTED), + .Dbg_WVALID_24(NLW_U0_Dbg_WVALID_24_UNCONNECTED), + .Dbg_WVALID_25(NLW_U0_Dbg_WVALID_25_UNCONNECTED), + .Dbg_WVALID_26(NLW_U0_Dbg_WVALID_26_UNCONNECTED), + .Dbg_WVALID_27(NLW_U0_Dbg_WVALID_27_UNCONNECTED), + .Dbg_WVALID_28(NLW_U0_Dbg_WVALID_28_UNCONNECTED), + .Dbg_WVALID_29(NLW_U0_Dbg_WVALID_29_UNCONNECTED), + .Dbg_WVALID_3(NLW_U0_Dbg_WVALID_3_UNCONNECTED), + .Dbg_WVALID_30(NLW_U0_Dbg_WVALID_30_UNCONNECTED), + .Dbg_WVALID_31(NLW_U0_Dbg_WVALID_31_UNCONNECTED), + .Dbg_WVALID_4(NLW_U0_Dbg_WVALID_4_UNCONNECTED), + .Dbg_WVALID_5(NLW_U0_Dbg_WVALID_5_UNCONNECTED), + .Dbg_WVALID_6(NLW_U0_Dbg_WVALID_6_UNCONNECTED), + .Dbg_WVALID_7(NLW_U0_Dbg_WVALID_7_UNCONNECTED), + .Dbg_WVALID_8(NLW_U0_Dbg_WVALID_8_UNCONNECTED), + .Dbg_WVALID_9(NLW_U0_Dbg_WVALID_9_UNCONNECTED), + .Debug_SYS_Rst(Debug_SYS_Rst), + .Ext_BRK(NLW_U0_Ext_BRK_UNCONNECTED), + .Ext_JTAG_CAPTURE(NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED), + .Ext_JTAG_DRCK(NLW_U0_Ext_JTAG_DRCK_UNCONNECTED), + .Ext_JTAG_RESET(NLW_U0_Ext_JTAG_RESET_UNCONNECTED), + .Ext_JTAG_SEL(NLW_U0_Ext_JTAG_SEL_UNCONNECTED), + .Ext_JTAG_SHIFT(NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED), + .Ext_JTAG_TDI(NLW_U0_Ext_JTAG_TDI_UNCONNECTED), + .Ext_JTAG_TDO(1'b0), + .Ext_JTAG_UPDATE(NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED), + .Ext_NM_BRK(NLW_U0_Ext_NM_BRK_UNCONNECTED), + .Interrupt(NLW_U0_Interrupt_UNCONNECTED), + .LMB_Addr_Strobe_0(NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED), + .LMB_Addr_Strobe_1(NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED), + .LMB_Addr_Strobe_10(NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED), + .LMB_Addr_Strobe_11(NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED), + .LMB_Addr_Strobe_12(NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED), + .LMB_Addr_Strobe_13(NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED), + .LMB_Addr_Strobe_14(NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED), + .LMB_Addr_Strobe_15(NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED), + .LMB_Addr_Strobe_16(NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED), + .LMB_Addr_Strobe_17(NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED), + .LMB_Addr_Strobe_18(NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED), + .LMB_Addr_Strobe_19(NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED), + .LMB_Addr_Strobe_2(NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED), + .LMB_Addr_Strobe_20(NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED), + .LMB_Addr_Strobe_21(NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED), + .LMB_Addr_Strobe_22(NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED), + .LMB_Addr_Strobe_23(NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED), + .LMB_Addr_Strobe_24(NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED), + .LMB_Addr_Strobe_25(NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED), + .LMB_Addr_Strobe_26(NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED), + .LMB_Addr_Strobe_27(NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED), + .LMB_Addr_Strobe_28(NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED), + .LMB_Addr_Strobe_29(NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED), + .LMB_Addr_Strobe_3(NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED), + .LMB_Addr_Strobe_30(NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED), + .LMB_Addr_Strobe_31(NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED), + .LMB_Addr_Strobe_4(NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED), + .LMB_Addr_Strobe_5(NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED), + .LMB_Addr_Strobe_6(NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED), + .LMB_Addr_Strobe_7(NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED), + .LMB_Addr_Strobe_8(NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED), + .LMB_Addr_Strobe_9(NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED), + .LMB_Byte_Enable_0(NLW_U0_LMB_Byte_Enable_0_UNCONNECTED[0:3]), + .LMB_Byte_Enable_1(NLW_U0_LMB_Byte_Enable_1_UNCONNECTED[0:3]), + .LMB_Byte_Enable_10(NLW_U0_LMB_Byte_Enable_10_UNCONNECTED[0:3]), + .LMB_Byte_Enable_11(NLW_U0_LMB_Byte_Enable_11_UNCONNECTED[0:3]), + .LMB_Byte_Enable_12(NLW_U0_LMB_Byte_Enable_12_UNCONNECTED[0:3]), + .LMB_Byte_Enable_13(NLW_U0_LMB_Byte_Enable_13_UNCONNECTED[0:3]), + .LMB_Byte_Enable_14(NLW_U0_LMB_Byte_Enable_14_UNCONNECTED[0:3]), + .LMB_Byte_Enable_15(NLW_U0_LMB_Byte_Enable_15_UNCONNECTED[0:3]), + .LMB_Byte_Enable_16(NLW_U0_LMB_Byte_Enable_16_UNCONNECTED[0:3]), + .LMB_Byte_Enable_17(NLW_U0_LMB_Byte_Enable_17_UNCONNECTED[0:3]), + .LMB_Byte_Enable_18(NLW_U0_LMB_Byte_Enable_18_UNCONNECTED[0:3]), + .LMB_Byte_Enable_19(NLW_U0_LMB_Byte_Enable_19_UNCONNECTED[0:3]), + .LMB_Byte_Enable_2(NLW_U0_LMB_Byte_Enable_2_UNCONNECTED[0:3]), + .LMB_Byte_Enable_20(NLW_U0_LMB_Byte_Enable_20_UNCONNECTED[0:3]), + .LMB_Byte_Enable_21(NLW_U0_LMB_Byte_Enable_21_UNCONNECTED[0:3]), + .LMB_Byte_Enable_22(NLW_U0_LMB_Byte_Enable_22_UNCONNECTED[0:3]), + .LMB_Byte_Enable_23(NLW_U0_LMB_Byte_Enable_23_UNCONNECTED[0:3]), + .LMB_Byte_Enable_24(NLW_U0_LMB_Byte_Enable_24_UNCONNECTED[0:3]), + .LMB_Byte_Enable_25(NLW_U0_LMB_Byte_Enable_25_UNCONNECTED[0:3]), + .LMB_Byte_Enable_26(NLW_U0_LMB_Byte_Enable_26_UNCONNECTED[0:3]), + .LMB_Byte_Enable_27(NLW_U0_LMB_Byte_Enable_27_UNCONNECTED[0:3]), + .LMB_Byte_Enable_28(NLW_U0_LMB_Byte_Enable_28_UNCONNECTED[0:3]), + .LMB_Byte_Enable_29(NLW_U0_LMB_Byte_Enable_29_UNCONNECTED[0:3]), + .LMB_Byte_Enable_3(NLW_U0_LMB_Byte_Enable_3_UNCONNECTED[0:3]), + .LMB_Byte_Enable_30(NLW_U0_LMB_Byte_Enable_30_UNCONNECTED[0:3]), + .LMB_Byte_Enable_31(NLW_U0_LMB_Byte_Enable_31_UNCONNECTED[0:3]), + .LMB_Byte_Enable_4(NLW_U0_LMB_Byte_Enable_4_UNCONNECTED[0:3]), + .LMB_Byte_Enable_5(NLW_U0_LMB_Byte_Enable_5_UNCONNECTED[0:3]), + .LMB_Byte_Enable_6(NLW_U0_LMB_Byte_Enable_6_UNCONNECTED[0:3]), + .LMB_Byte_Enable_7(NLW_U0_LMB_Byte_Enable_7_UNCONNECTED[0:3]), + .LMB_Byte_Enable_8(NLW_U0_LMB_Byte_Enable_8_UNCONNECTED[0:3]), + .LMB_Byte_Enable_9(NLW_U0_LMB_Byte_Enable_9_UNCONNECTED[0:3]), + .LMB_CE_0(1'b0), + .LMB_CE_1(1'b0), + .LMB_CE_10(1'b0), + .LMB_CE_11(1'b0), + .LMB_CE_12(1'b0), + .LMB_CE_13(1'b0), + .LMB_CE_14(1'b0), + .LMB_CE_15(1'b0), + .LMB_CE_16(1'b0), + .LMB_CE_17(1'b0), + .LMB_CE_18(1'b0), + .LMB_CE_19(1'b0), + .LMB_CE_2(1'b0), + .LMB_CE_20(1'b0), + .LMB_CE_21(1'b0), + .LMB_CE_22(1'b0), + .LMB_CE_23(1'b0), + .LMB_CE_24(1'b0), + .LMB_CE_25(1'b0), + .LMB_CE_26(1'b0), + .LMB_CE_27(1'b0), + .LMB_CE_28(1'b0), + .LMB_CE_29(1'b0), + .LMB_CE_3(1'b0), + .LMB_CE_30(1'b0), + .LMB_CE_31(1'b0), + .LMB_CE_4(1'b0), + .LMB_CE_5(1'b0), + .LMB_CE_6(1'b0), + .LMB_CE_7(1'b0), + .LMB_CE_8(1'b0), + .LMB_CE_9(1'b0), + .LMB_Data_Addr_0(NLW_U0_LMB_Data_Addr_0_UNCONNECTED[0:31]), + .LMB_Data_Addr_1(NLW_U0_LMB_Data_Addr_1_UNCONNECTED[0:31]), + .LMB_Data_Addr_10(NLW_U0_LMB_Data_Addr_10_UNCONNECTED[0:31]), + .LMB_Data_Addr_11(NLW_U0_LMB_Data_Addr_11_UNCONNECTED[0:31]), + .LMB_Data_Addr_12(NLW_U0_LMB_Data_Addr_12_UNCONNECTED[0:31]), + .LMB_Data_Addr_13(NLW_U0_LMB_Data_Addr_13_UNCONNECTED[0:31]), + .LMB_Data_Addr_14(NLW_U0_LMB_Data_Addr_14_UNCONNECTED[0:31]), + .LMB_Data_Addr_15(NLW_U0_LMB_Data_Addr_15_UNCONNECTED[0:31]), + .LMB_Data_Addr_16(NLW_U0_LMB_Data_Addr_16_UNCONNECTED[0:31]), + .LMB_Data_Addr_17(NLW_U0_LMB_Data_Addr_17_UNCONNECTED[0:31]), + .LMB_Data_Addr_18(NLW_U0_LMB_Data_Addr_18_UNCONNECTED[0:31]), + .LMB_Data_Addr_19(NLW_U0_LMB_Data_Addr_19_UNCONNECTED[0:31]), + .LMB_Data_Addr_2(NLW_U0_LMB_Data_Addr_2_UNCONNECTED[0:31]), + .LMB_Data_Addr_20(NLW_U0_LMB_Data_Addr_20_UNCONNECTED[0:31]), + .LMB_Data_Addr_21(NLW_U0_LMB_Data_Addr_21_UNCONNECTED[0:31]), + .LMB_Data_Addr_22(NLW_U0_LMB_Data_Addr_22_UNCONNECTED[0:31]), + .LMB_Data_Addr_23(NLW_U0_LMB_Data_Addr_23_UNCONNECTED[0:31]), + .LMB_Data_Addr_24(NLW_U0_LMB_Data_Addr_24_UNCONNECTED[0:31]), + .LMB_Data_Addr_25(NLW_U0_LMB_Data_Addr_25_UNCONNECTED[0:31]), + .LMB_Data_Addr_26(NLW_U0_LMB_Data_Addr_26_UNCONNECTED[0:31]), + .LMB_Data_Addr_27(NLW_U0_LMB_Data_Addr_27_UNCONNECTED[0:31]), + .LMB_Data_Addr_28(NLW_U0_LMB_Data_Addr_28_UNCONNECTED[0:31]), + .LMB_Data_Addr_29(NLW_U0_LMB_Data_Addr_29_UNCONNECTED[0:31]), + .LMB_Data_Addr_3(NLW_U0_LMB_Data_Addr_3_UNCONNECTED[0:31]), + .LMB_Data_Addr_30(NLW_U0_LMB_Data_Addr_30_UNCONNECTED[0:31]), + .LMB_Data_Addr_31(NLW_U0_LMB_Data_Addr_31_UNCONNECTED[0:31]), + .LMB_Data_Addr_4(NLW_U0_LMB_Data_Addr_4_UNCONNECTED[0:31]), + .LMB_Data_Addr_5(NLW_U0_LMB_Data_Addr_5_UNCONNECTED[0:31]), + .LMB_Data_Addr_6(NLW_U0_LMB_Data_Addr_6_UNCONNECTED[0:31]), + .LMB_Data_Addr_7(NLW_U0_LMB_Data_Addr_7_UNCONNECTED[0:31]), + .LMB_Data_Addr_8(NLW_U0_LMB_Data_Addr_8_UNCONNECTED[0:31]), + .LMB_Data_Addr_9(NLW_U0_LMB_Data_Addr_9_UNCONNECTED[0:31]), + .LMB_Data_Read_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Read_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .LMB_Data_Write_0(NLW_U0_LMB_Data_Write_0_UNCONNECTED[0:31]), + .LMB_Data_Write_1(NLW_U0_LMB_Data_Write_1_UNCONNECTED[0:31]), + .LMB_Data_Write_10(NLW_U0_LMB_Data_Write_10_UNCONNECTED[0:31]), + .LMB_Data_Write_11(NLW_U0_LMB_Data_Write_11_UNCONNECTED[0:31]), + .LMB_Data_Write_12(NLW_U0_LMB_Data_Write_12_UNCONNECTED[0:31]), + .LMB_Data_Write_13(NLW_U0_LMB_Data_Write_13_UNCONNECTED[0:31]), + .LMB_Data_Write_14(NLW_U0_LMB_Data_Write_14_UNCONNECTED[0:31]), + .LMB_Data_Write_15(NLW_U0_LMB_Data_Write_15_UNCONNECTED[0:31]), + .LMB_Data_Write_16(NLW_U0_LMB_Data_Write_16_UNCONNECTED[0:31]), + .LMB_Data_Write_17(NLW_U0_LMB_Data_Write_17_UNCONNECTED[0:31]), + .LMB_Data_Write_18(NLW_U0_LMB_Data_Write_18_UNCONNECTED[0:31]), + .LMB_Data_Write_19(NLW_U0_LMB_Data_Write_19_UNCONNECTED[0:31]), + .LMB_Data_Write_2(NLW_U0_LMB_Data_Write_2_UNCONNECTED[0:31]), + .LMB_Data_Write_20(NLW_U0_LMB_Data_Write_20_UNCONNECTED[0:31]), + .LMB_Data_Write_21(NLW_U0_LMB_Data_Write_21_UNCONNECTED[0:31]), + .LMB_Data_Write_22(NLW_U0_LMB_Data_Write_22_UNCONNECTED[0:31]), + .LMB_Data_Write_23(NLW_U0_LMB_Data_Write_23_UNCONNECTED[0:31]), + .LMB_Data_Write_24(NLW_U0_LMB_Data_Write_24_UNCONNECTED[0:31]), + .LMB_Data_Write_25(NLW_U0_LMB_Data_Write_25_UNCONNECTED[0:31]), + .LMB_Data_Write_26(NLW_U0_LMB_Data_Write_26_UNCONNECTED[0:31]), + .LMB_Data_Write_27(NLW_U0_LMB_Data_Write_27_UNCONNECTED[0:31]), + .LMB_Data_Write_28(NLW_U0_LMB_Data_Write_28_UNCONNECTED[0:31]), + .LMB_Data_Write_29(NLW_U0_LMB_Data_Write_29_UNCONNECTED[0:31]), + .LMB_Data_Write_3(NLW_U0_LMB_Data_Write_3_UNCONNECTED[0:31]), + .LMB_Data_Write_30(NLW_U0_LMB_Data_Write_30_UNCONNECTED[0:31]), + .LMB_Data_Write_31(NLW_U0_LMB_Data_Write_31_UNCONNECTED[0:31]), + .LMB_Data_Write_4(NLW_U0_LMB_Data_Write_4_UNCONNECTED[0:31]), + .LMB_Data_Write_5(NLW_U0_LMB_Data_Write_5_UNCONNECTED[0:31]), + .LMB_Data_Write_6(NLW_U0_LMB_Data_Write_6_UNCONNECTED[0:31]), + .LMB_Data_Write_7(NLW_U0_LMB_Data_Write_7_UNCONNECTED[0:31]), + .LMB_Data_Write_8(NLW_U0_LMB_Data_Write_8_UNCONNECTED[0:31]), + .LMB_Data_Write_9(NLW_U0_LMB_Data_Write_9_UNCONNECTED[0:31]), + .LMB_Read_Strobe_0(NLW_U0_LMB_Read_Strobe_0_UNCONNECTED), + .LMB_Read_Strobe_1(NLW_U0_LMB_Read_Strobe_1_UNCONNECTED), + .LMB_Read_Strobe_10(NLW_U0_LMB_Read_Strobe_10_UNCONNECTED), + .LMB_Read_Strobe_11(NLW_U0_LMB_Read_Strobe_11_UNCONNECTED), + .LMB_Read_Strobe_12(NLW_U0_LMB_Read_Strobe_12_UNCONNECTED), + .LMB_Read_Strobe_13(NLW_U0_LMB_Read_Strobe_13_UNCONNECTED), + .LMB_Read_Strobe_14(NLW_U0_LMB_Read_Strobe_14_UNCONNECTED), + .LMB_Read_Strobe_15(NLW_U0_LMB_Read_Strobe_15_UNCONNECTED), + .LMB_Read_Strobe_16(NLW_U0_LMB_Read_Strobe_16_UNCONNECTED), + .LMB_Read_Strobe_17(NLW_U0_LMB_Read_Strobe_17_UNCONNECTED), + .LMB_Read_Strobe_18(NLW_U0_LMB_Read_Strobe_18_UNCONNECTED), + .LMB_Read_Strobe_19(NLW_U0_LMB_Read_Strobe_19_UNCONNECTED), + .LMB_Read_Strobe_2(NLW_U0_LMB_Read_Strobe_2_UNCONNECTED), + .LMB_Read_Strobe_20(NLW_U0_LMB_Read_Strobe_20_UNCONNECTED), + .LMB_Read_Strobe_21(NLW_U0_LMB_Read_Strobe_21_UNCONNECTED), + .LMB_Read_Strobe_22(NLW_U0_LMB_Read_Strobe_22_UNCONNECTED), + .LMB_Read_Strobe_23(NLW_U0_LMB_Read_Strobe_23_UNCONNECTED), + .LMB_Read_Strobe_24(NLW_U0_LMB_Read_Strobe_24_UNCONNECTED), + .LMB_Read_Strobe_25(NLW_U0_LMB_Read_Strobe_25_UNCONNECTED), + .LMB_Read_Strobe_26(NLW_U0_LMB_Read_Strobe_26_UNCONNECTED), + .LMB_Read_Strobe_27(NLW_U0_LMB_Read_Strobe_27_UNCONNECTED), + .LMB_Read_Strobe_28(NLW_U0_LMB_Read_Strobe_28_UNCONNECTED), + .LMB_Read_Strobe_29(NLW_U0_LMB_Read_Strobe_29_UNCONNECTED), + .LMB_Read_Strobe_3(NLW_U0_LMB_Read_Strobe_3_UNCONNECTED), + .LMB_Read_Strobe_30(NLW_U0_LMB_Read_Strobe_30_UNCONNECTED), + .LMB_Read_Strobe_31(NLW_U0_LMB_Read_Strobe_31_UNCONNECTED), + .LMB_Read_Strobe_4(NLW_U0_LMB_Read_Strobe_4_UNCONNECTED), + .LMB_Read_Strobe_5(NLW_U0_LMB_Read_Strobe_5_UNCONNECTED), + .LMB_Read_Strobe_6(NLW_U0_LMB_Read_Strobe_6_UNCONNECTED), + .LMB_Read_Strobe_7(NLW_U0_LMB_Read_Strobe_7_UNCONNECTED), + .LMB_Read_Strobe_8(NLW_U0_LMB_Read_Strobe_8_UNCONNECTED), + .LMB_Read_Strobe_9(NLW_U0_LMB_Read_Strobe_9_UNCONNECTED), + .LMB_Ready_0(1'b0), + .LMB_Ready_1(1'b0), + .LMB_Ready_10(1'b0), + .LMB_Ready_11(1'b0), + .LMB_Ready_12(1'b0), + .LMB_Ready_13(1'b0), + .LMB_Ready_14(1'b0), + .LMB_Ready_15(1'b0), + .LMB_Ready_16(1'b0), + .LMB_Ready_17(1'b0), + .LMB_Ready_18(1'b0), + .LMB_Ready_19(1'b0), + .LMB_Ready_2(1'b0), + .LMB_Ready_20(1'b0), + .LMB_Ready_21(1'b0), + .LMB_Ready_22(1'b0), + .LMB_Ready_23(1'b0), + .LMB_Ready_24(1'b0), + .LMB_Ready_25(1'b0), + .LMB_Ready_26(1'b0), + .LMB_Ready_27(1'b0), + .LMB_Ready_28(1'b0), + .LMB_Ready_29(1'b0), + .LMB_Ready_3(1'b0), + .LMB_Ready_30(1'b0), + .LMB_Ready_31(1'b0), + .LMB_Ready_4(1'b0), + .LMB_Ready_5(1'b0), + .LMB_Ready_6(1'b0), + .LMB_Ready_7(1'b0), + .LMB_Ready_8(1'b0), + .LMB_Ready_9(1'b0), + .LMB_UE_0(1'b0), + .LMB_UE_1(1'b0), + .LMB_UE_10(1'b0), + .LMB_UE_11(1'b0), + .LMB_UE_12(1'b0), + .LMB_UE_13(1'b0), + .LMB_UE_14(1'b0), + .LMB_UE_15(1'b0), + .LMB_UE_16(1'b0), + .LMB_UE_17(1'b0), + .LMB_UE_18(1'b0), + .LMB_UE_19(1'b0), + .LMB_UE_2(1'b0), + .LMB_UE_20(1'b0), + .LMB_UE_21(1'b0), + .LMB_UE_22(1'b0), + .LMB_UE_23(1'b0), + .LMB_UE_24(1'b0), + .LMB_UE_25(1'b0), + .LMB_UE_26(1'b0), + .LMB_UE_27(1'b0), + .LMB_UE_28(1'b0), + .LMB_UE_29(1'b0), + .LMB_UE_3(1'b0), + .LMB_UE_30(1'b0), + .LMB_UE_31(1'b0), + .LMB_UE_4(1'b0), + .LMB_UE_5(1'b0), + .LMB_UE_6(1'b0), + .LMB_UE_7(1'b0), + .LMB_UE_8(1'b0), + .LMB_UE_9(1'b0), + .LMB_Wait_0(1'b0), + .LMB_Wait_1(1'b0), + .LMB_Wait_10(1'b0), + .LMB_Wait_11(1'b0), + .LMB_Wait_12(1'b0), + .LMB_Wait_13(1'b0), + .LMB_Wait_14(1'b0), + .LMB_Wait_15(1'b0), + .LMB_Wait_16(1'b0), + .LMB_Wait_17(1'b0), + .LMB_Wait_18(1'b0), + .LMB_Wait_19(1'b0), + .LMB_Wait_2(1'b0), + .LMB_Wait_20(1'b0), + .LMB_Wait_21(1'b0), + .LMB_Wait_22(1'b0), + .LMB_Wait_23(1'b0), + .LMB_Wait_24(1'b0), + .LMB_Wait_25(1'b0), + .LMB_Wait_26(1'b0), + .LMB_Wait_27(1'b0), + .LMB_Wait_28(1'b0), + .LMB_Wait_29(1'b0), + .LMB_Wait_3(1'b0), + .LMB_Wait_30(1'b0), + .LMB_Wait_31(1'b0), + .LMB_Wait_4(1'b0), + .LMB_Wait_5(1'b0), + .LMB_Wait_6(1'b0), + .LMB_Wait_7(1'b0), + .LMB_Wait_8(1'b0), + .LMB_Wait_9(1'b0), + .LMB_Write_Strobe_0(NLW_U0_LMB_Write_Strobe_0_UNCONNECTED), + .LMB_Write_Strobe_1(NLW_U0_LMB_Write_Strobe_1_UNCONNECTED), + .LMB_Write_Strobe_10(NLW_U0_LMB_Write_Strobe_10_UNCONNECTED), + .LMB_Write_Strobe_11(NLW_U0_LMB_Write_Strobe_11_UNCONNECTED), + .LMB_Write_Strobe_12(NLW_U0_LMB_Write_Strobe_12_UNCONNECTED), + .LMB_Write_Strobe_13(NLW_U0_LMB_Write_Strobe_13_UNCONNECTED), + .LMB_Write_Strobe_14(NLW_U0_LMB_Write_Strobe_14_UNCONNECTED), + .LMB_Write_Strobe_15(NLW_U0_LMB_Write_Strobe_15_UNCONNECTED), + .LMB_Write_Strobe_16(NLW_U0_LMB_Write_Strobe_16_UNCONNECTED), + .LMB_Write_Strobe_17(NLW_U0_LMB_Write_Strobe_17_UNCONNECTED), + .LMB_Write_Strobe_18(NLW_U0_LMB_Write_Strobe_18_UNCONNECTED), + .LMB_Write_Strobe_19(NLW_U0_LMB_Write_Strobe_19_UNCONNECTED), + .LMB_Write_Strobe_2(NLW_U0_LMB_Write_Strobe_2_UNCONNECTED), + .LMB_Write_Strobe_20(NLW_U0_LMB_Write_Strobe_20_UNCONNECTED), + .LMB_Write_Strobe_21(NLW_U0_LMB_Write_Strobe_21_UNCONNECTED), + .LMB_Write_Strobe_22(NLW_U0_LMB_Write_Strobe_22_UNCONNECTED), + .LMB_Write_Strobe_23(NLW_U0_LMB_Write_Strobe_23_UNCONNECTED), + .LMB_Write_Strobe_24(NLW_U0_LMB_Write_Strobe_24_UNCONNECTED), + .LMB_Write_Strobe_25(NLW_U0_LMB_Write_Strobe_25_UNCONNECTED), + .LMB_Write_Strobe_26(NLW_U0_LMB_Write_Strobe_26_UNCONNECTED), + .LMB_Write_Strobe_27(NLW_U0_LMB_Write_Strobe_27_UNCONNECTED), + .LMB_Write_Strobe_28(NLW_U0_LMB_Write_Strobe_28_UNCONNECTED), + .LMB_Write_Strobe_29(NLW_U0_LMB_Write_Strobe_29_UNCONNECTED), + .LMB_Write_Strobe_3(NLW_U0_LMB_Write_Strobe_3_UNCONNECTED), + .LMB_Write_Strobe_30(NLW_U0_LMB_Write_Strobe_30_UNCONNECTED), + .LMB_Write_Strobe_31(NLW_U0_LMB_Write_Strobe_31_UNCONNECTED), + .LMB_Write_Strobe_4(NLW_U0_LMB_Write_Strobe_4_UNCONNECTED), + .LMB_Write_Strobe_5(NLW_U0_LMB_Write_Strobe_5_UNCONNECTED), + .LMB_Write_Strobe_6(NLW_U0_LMB_Write_Strobe_6_UNCONNECTED), + .LMB_Write_Strobe_7(NLW_U0_LMB_Write_Strobe_7_UNCONNECTED), + .LMB_Write_Strobe_8(NLW_U0_LMB_Write_Strobe_8_UNCONNECTED), + .LMB_Write_Strobe_9(NLW_U0_LMB_Write_Strobe_9_UNCONNECTED), + .M_AXIS_ACLK(1'b0), + .M_AXIS_ARESETN(1'b0), + .M_AXIS_TDATA(NLW_U0_M_AXIS_TDATA_UNCONNECTED[31:0]), + .M_AXIS_TID(NLW_U0_M_AXIS_TID_UNCONNECTED[6:0]), + .M_AXIS_TREADY(1'b1), + .M_AXIS_TVALID(NLW_U0_M_AXIS_TVALID_UNCONNECTED), + .M_AXI_ACLK(1'b0), + .M_AXI_ARADDR(NLW_U0_M_AXI_ARADDR_UNCONNECTED[31:0]), + .M_AXI_ARBURST(NLW_U0_M_AXI_ARBURST_UNCONNECTED[1:0]), + .M_AXI_ARCACHE(NLW_U0_M_AXI_ARCACHE_UNCONNECTED[3:0]), + .M_AXI_ARESETN(1'b0), + .M_AXI_ARID(NLW_U0_M_AXI_ARID_UNCONNECTED[0]), + .M_AXI_ARLEN(NLW_U0_M_AXI_ARLEN_UNCONNECTED[7:0]), + .M_AXI_ARLOCK(NLW_U0_M_AXI_ARLOCK_UNCONNECTED), + .M_AXI_ARPROT(NLW_U0_M_AXI_ARPROT_UNCONNECTED[2:0]), + .M_AXI_ARQOS(NLW_U0_M_AXI_ARQOS_UNCONNECTED[3:0]), + .M_AXI_ARREADY(1'b0), + .M_AXI_ARSIZE(NLW_U0_M_AXI_ARSIZE_UNCONNECTED[2:0]), + .M_AXI_ARVALID(NLW_U0_M_AXI_ARVALID_UNCONNECTED), + .M_AXI_AWADDR(NLW_U0_M_AXI_AWADDR_UNCONNECTED[31:0]), + .M_AXI_AWBURST(NLW_U0_M_AXI_AWBURST_UNCONNECTED[1:0]), + .M_AXI_AWCACHE(NLW_U0_M_AXI_AWCACHE_UNCONNECTED[3:0]), + .M_AXI_AWID(NLW_U0_M_AXI_AWID_UNCONNECTED[0]), + .M_AXI_AWLEN(NLW_U0_M_AXI_AWLEN_UNCONNECTED[7:0]), + .M_AXI_AWLOCK(NLW_U0_M_AXI_AWLOCK_UNCONNECTED), + .M_AXI_AWPROT(NLW_U0_M_AXI_AWPROT_UNCONNECTED[2:0]), + .M_AXI_AWQOS(NLW_U0_M_AXI_AWQOS_UNCONNECTED[3:0]), + .M_AXI_AWREADY(1'b0), + .M_AXI_AWSIZE(NLW_U0_M_AXI_AWSIZE_UNCONNECTED[2:0]), + .M_AXI_AWVALID(NLW_U0_M_AXI_AWVALID_UNCONNECTED), + .M_AXI_BID(1'b0), + .M_AXI_BREADY(NLW_U0_M_AXI_BREADY_UNCONNECTED), + .M_AXI_BRESP({1'b0,1'b0}), + .M_AXI_BVALID(1'b0), + .M_AXI_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_RID(1'b0), + .M_AXI_RLAST(1'b0), + .M_AXI_RREADY(NLW_U0_M_AXI_RREADY_UNCONNECTED), + .M_AXI_RRESP({1'b0,1'b0}), + .M_AXI_RVALID(1'b0), + .M_AXI_WDATA(NLW_U0_M_AXI_WDATA_UNCONNECTED[31:0]), + .M_AXI_WLAST(NLW_U0_M_AXI_WLAST_UNCONNECTED), + .M_AXI_WREADY(1'b0), + .M_AXI_WSTRB(NLW_U0_M_AXI_WSTRB_UNCONNECTED[3:0]), + .M_AXI_WVALID(NLW_U0_M_AXI_WVALID_UNCONNECTED), + .S_AXI_ACLK(1'b0), + .S_AXI_ARADDR({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ARESETN(1'b0), + .S_AXI_ARREADY(NLW_U0_S_AXI_ARREADY_UNCONNECTED), + .S_AXI_ARVALID(1'b0), + .S_AXI_AWADDR({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_AWREADY(NLW_U0_S_AXI_AWREADY_UNCONNECTED), + .S_AXI_AWVALID(1'b0), + .S_AXI_BREADY(1'b0), + .S_AXI_BRESP(NLW_U0_S_AXI_BRESP_UNCONNECTED[1:0]), + .S_AXI_BVALID(NLW_U0_S_AXI_BVALID_UNCONNECTED), + .S_AXI_RDATA(NLW_U0_S_AXI_RDATA_UNCONNECTED[31:0]), + .S_AXI_RREADY(1'b0), + .S_AXI_RRESP(NLW_U0_S_AXI_RRESP_UNCONNECTED[1:0]), + .S_AXI_RVALID(NLW_U0_S_AXI_RVALID_UNCONNECTED), + .S_AXI_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_WREADY(NLW_U0_S_AXI_WREADY_UNCONNECTED), + .S_AXI_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_WVALID(1'b0), + .Scan_En(1'b0), + .Scan_Reset(1'b0), + .Scan_Reset_Sel(1'b0), + .TRACE_CLK(1'b0), + .TRACE_CLK_OUT(NLW_U0_TRACE_CLK_OUT_UNCONNECTED), + .TRACE_CTL(NLW_U0_TRACE_CTL_UNCONNECTED), + .TRACE_DATA(NLW_U0_TRACE_DATA_UNCONNECTED[31:0]), + .Trig_Ack_In_0(NLW_U0_Trig_Ack_In_0_UNCONNECTED), + .Trig_Ack_In_1(NLW_U0_Trig_Ack_In_1_UNCONNECTED), + .Trig_Ack_In_2(NLW_U0_Trig_Ack_In_2_UNCONNECTED), + .Trig_Ack_In_3(NLW_U0_Trig_Ack_In_3_UNCONNECTED), + .Trig_Ack_Out_0(1'b0), + .Trig_Ack_Out_1(1'b0), + .Trig_Ack_Out_2(1'b0), + .Trig_Ack_Out_3(1'b0), + .Trig_In_0(1'b0), + .Trig_In_1(1'b0), + .Trig_In_2(1'b0), + .Trig_In_3(1'b0), + .Trig_Out_0(NLW_U0_Trig_Out_0_UNCONNECTED), + .Trig_Out_1(NLW_U0_Trig_Out_1_UNCONNECTED), + .Trig_Out_2(NLW_U0_Trig_Out_2_UNCONNECTED), + .Trig_Out_3(NLW_U0_Trig_Out_3_UNCONNECTED), + .bscan_ext_bscanid_en(1'b0), + .bscan_ext_capture(1'b0), + .bscan_ext_drck(1'b0), + .bscan_ext_reset(1'b0), + .bscan_ext_sel(1'b0), + .bscan_ext_shift(1'b0), + .bscan_ext_tck(1'b0), + .bscan_ext_tdi(1'b0), + .bscan_ext_tdo(NLW_U0_bscan_ext_tdo_UNCONNECTED), + .bscan_ext_update(1'b0)); +endmodule + +(* ORIG_REF_NAME = "JTAG_CONTROL" *) module system_bd_mdm_0_JTAG_CONTROL (Q, AR, @@ -1198,6 +3669,7 @@ module system_bd_mdm_0_JTAG_CONTROL .Q(\tdi_shifter_reg_n_0_[7] )); endmodule +(* ORIG_REF_NAME = "MB_BSCANE2" *) module system_bd_mdm_0_MB_BSCANE2 (\Use_BSCAN.PORT_Selector_reg[0] , DRCK, @@ -1357,6 +3829,7 @@ module system_bd_mdm_0_MB_BSCANE2 .O(\shift_Count_reg[0] )); endmodule +(* ORIG_REF_NAME = "MB_BUFG" *) module system_bd_mdm_0_MB_BUFG (Ext_JTAG_DRCK, DRCK); @@ -1372,6 +3845,7 @@ module system_bd_mdm_0_MB_BUFG .O(Ext_JTAG_DRCK)); endmodule +(* ORIG_REF_NAME = "MB_FDC_1" *) module system_bd_mdm_0_MB_FDC_1 (D_1, Dbg_Reg_En_0, @@ -1965,6 +4439,7 @@ module system_bd_mdm_0_MB_FDC_1 .O(\tdi_shifter_reg[0]_0 )); endmodule +(* ORIG_REF_NAME = "MB_FDRE_1" *) module system_bd_mdm_0_MB_FDRE_1 (sync, Dbg_Shift_0, @@ -2021,6 +4496,7 @@ module system_bd_mdm_0_MB_FDRE_1 .R(D_1)); endmodule +(* ORIG_REF_NAME = "MB_SRL16E" *) module system_bd_mdm_0_MB_SRL16E (tdo, Q, @@ -2235,7 +4711,7 @@ endmodule (* C_TRACE_CLK_FREQ_HZ = "200000000" *) (* C_TRACE_CLK_OUT_PHASE = "90" *) (* C_TRACE_DATA_WIDTH = "32" *) (* C_TRACE_ID = "110" *) (* C_TRACE_OUTPUT = "0" *) (* C_TRACE_PROTOCOL = "1" *) (* C_USE_BSCAN = "0" *) (* C_USE_CONFIG_RESET = "0" *) (* C_USE_CROSS_TRIGGER = "0" *) -(* C_USE_UART = "0" *) +(* C_USE_UART = "0" *) (* ORIG_REF_NAME = "MDM" *) module system_bd_mdm_0_MDM (Config_Reset, Scan_Reset_Sel, @@ -10996,6 +13472,7 @@ module system_bd_mdm_0_MDM (.P(\ )); endmodule +(* ORIG_REF_NAME = "MDM_Core" *) module system_bd_mdm_0_MDM_Core (Q, Dbg_Disable_0, @@ -11543,2476 +14020,6 @@ module system_bd_mdm_0_MDM_Core .I5(PORT_Selector[1]), .O(\Use_E2.BSCANE2_I_i_2_n_0 )); endmodule - -(* CHECK_LICENSE_TYPE = "system_bd_mdm_0,MDM,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "MDM,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_mdm_0 - (Debug_SYS_Rst, - Dbg_Clk_0, - Dbg_TDI_0, - Dbg_TDO_0, - Dbg_Reg_En_0, - Dbg_Capture_0, - Dbg_Shift_0, - Dbg_Update_0, - Dbg_Rst_0, - Dbg_Disable_0); - (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.Debug_SYS_Rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output Debug_SYS_Rst; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK" *) output Dbg_Clk_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI" *) output Dbg_TDI_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO" *) input Dbg_TDO_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN" *) output [0:7]Dbg_Reg_En_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE" *) output Dbg_Capture_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT" *) output Dbg_Shift_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE" *) output Dbg_Update_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST" *) output Dbg_Rst_0; - (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 DISABLE" *) output Dbg_Disable_0; - - wire Dbg_Capture_0; - wire Dbg_Clk_0; - wire Dbg_Disable_0; - wire [0:7]Dbg_Reg_En_0; - wire Dbg_Rst_0; - wire Dbg_Shift_0; - wire Dbg_TDI_0; - wire Dbg_TDO_0; - wire Dbg_Update_0; - wire Debug_SYS_Rst; - wire NLW_U0_Dbg_ARVALID_0_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_1_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_10_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_11_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_12_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_13_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_14_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_15_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_16_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_17_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_18_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_19_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_2_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_20_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_21_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_22_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_23_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_24_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_25_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_26_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_27_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_28_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_29_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_3_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_30_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_31_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_4_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_5_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_6_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_7_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_8_UNCONNECTED; - wire NLW_U0_Dbg_ARVALID_9_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_0_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_1_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_10_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_11_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_12_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_13_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_14_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_15_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_16_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_17_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_18_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_19_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_2_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_20_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_21_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_22_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_23_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_24_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_25_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_26_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_27_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_28_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_29_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_3_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_30_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_31_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_4_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_5_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_6_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_7_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_8_UNCONNECTED; - wire NLW_U0_Dbg_AWVALID_9_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_0_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_1_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_10_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_11_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_12_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_13_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_14_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_15_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_16_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_17_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_18_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_19_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_2_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_20_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_21_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_22_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_23_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_24_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_25_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_26_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_27_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_28_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_29_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_3_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_30_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_31_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_4_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_5_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_6_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_7_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_8_UNCONNECTED; - wire NLW_U0_Dbg_BREADY_9_UNCONNECTED; - wire NLW_U0_Dbg_Capture_1_UNCONNECTED; - wire NLW_U0_Dbg_Capture_10_UNCONNECTED; - wire NLW_U0_Dbg_Capture_11_UNCONNECTED; - wire NLW_U0_Dbg_Capture_12_UNCONNECTED; - wire NLW_U0_Dbg_Capture_13_UNCONNECTED; - wire NLW_U0_Dbg_Capture_14_UNCONNECTED; - wire NLW_U0_Dbg_Capture_15_UNCONNECTED; - wire NLW_U0_Dbg_Capture_16_UNCONNECTED; - wire NLW_U0_Dbg_Capture_17_UNCONNECTED; - wire NLW_U0_Dbg_Capture_18_UNCONNECTED; - wire NLW_U0_Dbg_Capture_19_UNCONNECTED; - wire NLW_U0_Dbg_Capture_2_UNCONNECTED; - wire NLW_U0_Dbg_Capture_20_UNCONNECTED; - wire NLW_U0_Dbg_Capture_21_UNCONNECTED; - wire NLW_U0_Dbg_Capture_22_UNCONNECTED; - wire NLW_U0_Dbg_Capture_23_UNCONNECTED; - wire NLW_U0_Dbg_Capture_24_UNCONNECTED; - wire NLW_U0_Dbg_Capture_25_UNCONNECTED; - wire NLW_U0_Dbg_Capture_26_UNCONNECTED; - wire NLW_U0_Dbg_Capture_27_UNCONNECTED; - wire NLW_U0_Dbg_Capture_28_UNCONNECTED; - wire NLW_U0_Dbg_Capture_29_UNCONNECTED; - wire NLW_U0_Dbg_Capture_3_UNCONNECTED; - wire NLW_U0_Dbg_Capture_30_UNCONNECTED; - wire NLW_U0_Dbg_Capture_31_UNCONNECTED; - wire NLW_U0_Dbg_Capture_4_UNCONNECTED; - wire NLW_U0_Dbg_Capture_5_UNCONNECTED; - wire NLW_U0_Dbg_Capture_6_UNCONNECTED; - wire NLW_U0_Dbg_Capture_7_UNCONNECTED; - wire NLW_U0_Dbg_Capture_8_UNCONNECTED; - wire NLW_U0_Dbg_Capture_9_UNCONNECTED; - wire NLW_U0_Dbg_Clk_1_UNCONNECTED; - wire NLW_U0_Dbg_Clk_10_UNCONNECTED; - wire NLW_U0_Dbg_Clk_11_UNCONNECTED; - wire NLW_U0_Dbg_Clk_12_UNCONNECTED; - wire NLW_U0_Dbg_Clk_13_UNCONNECTED; - wire NLW_U0_Dbg_Clk_14_UNCONNECTED; - wire NLW_U0_Dbg_Clk_15_UNCONNECTED; - wire NLW_U0_Dbg_Clk_16_UNCONNECTED; - wire NLW_U0_Dbg_Clk_17_UNCONNECTED; - wire NLW_U0_Dbg_Clk_18_UNCONNECTED; - wire NLW_U0_Dbg_Clk_19_UNCONNECTED; - wire NLW_U0_Dbg_Clk_2_UNCONNECTED; - wire NLW_U0_Dbg_Clk_20_UNCONNECTED; - wire NLW_U0_Dbg_Clk_21_UNCONNECTED; - wire NLW_U0_Dbg_Clk_22_UNCONNECTED; - wire NLW_U0_Dbg_Clk_23_UNCONNECTED; - wire NLW_U0_Dbg_Clk_24_UNCONNECTED; - wire NLW_U0_Dbg_Clk_25_UNCONNECTED; - wire NLW_U0_Dbg_Clk_26_UNCONNECTED; - wire NLW_U0_Dbg_Clk_27_UNCONNECTED; - wire NLW_U0_Dbg_Clk_28_UNCONNECTED; - wire NLW_U0_Dbg_Clk_29_UNCONNECTED; - wire NLW_U0_Dbg_Clk_3_UNCONNECTED; - wire NLW_U0_Dbg_Clk_30_UNCONNECTED; - wire NLW_U0_Dbg_Clk_31_UNCONNECTED; - wire NLW_U0_Dbg_Clk_4_UNCONNECTED; - wire NLW_U0_Dbg_Clk_5_UNCONNECTED; - wire NLW_U0_Dbg_Clk_6_UNCONNECTED; - wire NLW_U0_Dbg_Clk_7_UNCONNECTED; - wire NLW_U0_Dbg_Clk_8_UNCONNECTED; - wire NLW_U0_Dbg_Clk_9_UNCONNECTED; - wire NLW_U0_Dbg_Disable_1_UNCONNECTED; - wire NLW_U0_Dbg_Disable_10_UNCONNECTED; - wire NLW_U0_Dbg_Disable_11_UNCONNECTED; - wire NLW_U0_Dbg_Disable_12_UNCONNECTED; - wire NLW_U0_Dbg_Disable_13_UNCONNECTED; - wire NLW_U0_Dbg_Disable_14_UNCONNECTED; - wire NLW_U0_Dbg_Disable_15_UNCONNECTED; - wire NLW_U0_Dbg_Disable_16_UNCONNECTED; - wire NLW_U0_Dbg_Disable_17_UNCONNECTED; - wire NLW_U0_Dbg_Disable_18_UNCONNECTED; - wire NLW_U0_Dbg_Disable_19_UNCONNECTED; - wire NLW_U0_Dbg_Disable_2_UNCONNECTED; - wire NLW_U0_Dbg_Disable_20_UNCONNECTED; - wire NLW_U0_Dbg_Disable_21_UNCONNECTED; - wire NLW_U0_Dbg_Disable_22_UNCONNECTED; - wire NLW_U0_Dbg_Disable_23_UNCONNECTED; - wire NLW_U0_Dbg_Disable_24_UNCONNECTED; - wire NLW_U0_Dbg_Disable_25_UNCONNECTED; - wire NLW_U0_Dbg_Disable_26_UNCONNECTED; - wire NLW_U0_Dbg_Disable_27_UNCONNECTED; - wire NLW_U0_Dbg_Disable_28_UNCONNECTED; - wire NLW_U0_Dbg_Disable_29_UNCONNECTED; - wire NLW_U0_Dbg_Disable_3_UNCONNECTED; - wire NLW_U0_Dbg_Disable_30_UNCONNECTED; - wire NLW_U0_Dbg_Disable_31_UNCONNECTED; - wire NLW_U0_Dbg_Disable_4_UNCONNECTED; - wire NLW_U0_Dbg_Disable_5_UNCONNECTED; - wire NLW_U0_Dbg_Disable_6_UNCONNECTED; - wire NLW_U0_Dbg_Disable_7_UNCONNECTED; - wire NLW_U0_Dbg_Disable_8_UNCONNECTED; - wire NLW_U0_Dbg_Disable_9_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_0_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_1_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_10_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_11_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_12_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_13_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_14_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_15_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_16_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_17_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_18_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_19_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_2_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_20_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_21_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_22_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_23_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_24_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_25_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_26_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_27_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_28_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_29_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_3_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_30_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_31_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_4_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_5_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_6_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_7_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_8_UNCONNECTED; - wire NLW_U0_Dbg_RREADY_9_UNCONNECTED; - wire NLW_U0_Dbg_Rst_1_UNCONNECTED; - wire NLW_U0_Dbg_Rst_10_UNCONNECTED; - wire NLW_U0_Dbg_Rst_11_UNCONNECTED; - wire NLW_U0_Dbg_Rst_12_UNCONNECTED; - wire NLW_U0_Dbg_Rst_13_UNCONNECTED; - wire NLW_U0_Dbg_Rst_14_UNCONNECTED; - wire NLW_U0_Dbg_Rst_15_UNCONNECTED; - wire NLW_U0_Dbg_Rst_16_UNCONNECTED; - wire NLW_U0_Dbg_Rst_17_UNCONNECTED; - wire NLW_U0_Dbg_Rst_18_UNCONNECTED; - wire NLW_U0_Dbg_Rst_19_UNCONNECTED; - wire NLW_U0_Dbg_Rst_2_UNCONNECTED; - wire NLW_U0_Dbg_Rst_20_UNCONNECTED; - wire NLW_U0_Dbg_Rst_21_UNCONNECTED; - wire NLW_U0_Dbg_Rst_22_UNCONNECTED; - wire NLW_U0_Dbg_Rst_23_UNCONNECTED; - wire NLW_U0_Dbg_Rst_24_UNCONNECTED; - wire NLW_U0_Dbg_Rst_25_UNCONNECTED; - wire NLW_U0_Dbg_Rst_26_UNCONNECTED; - wire NLW_U0_Dbg_Rst_27_UNCONNECTED; - wire NLW_U0_Dbg_Rst_28_UNCONNECTED; - wire NLW_U0_Dbg_Rst_29_UNCONNECTED; - wire NLW_U0_Dbg_Rst_3_UNCONNECTED; - wire NLW_U0_Dbg_Rst_30_UNCONNECTED; - wire NLW_U0_Dbg_Rst_31_UNCONNECTED; - wire NLW_U0_Dbg_Rst_4_UNCONNECTED; - wire NLW_U0_Dbg_Rst_5_UNCONNECTED; - wire NLW_U0_Dbg_Rst_6_UNCONNECTED; - wire NLW_U0_Dbg_Rst_7_UNCONNECTED; - wire NLW_U0_Dbg_Rst_8_UNCONNECTED; - wire NLW_U0_Dbg_Rst_9_UNCONNECTED; - wire NLW_U0_Dbg_Shift_1_UNCONNECTED; - wire NLW_U0_Dbg_Shift_10_UNCONNECTED; - wire NLW_U0_Dbg_Shift_11_UNCONNECTED; - wire NLW_U0_Dbg_Shift_12_UNCONNECTED; - wire NLW_U0_Dbg_Shift_13_UNCONNECTED; - wire NLW_U0_Dbg_Shift_14_UNCONNECTED; - wire NLW_U0_Dbg_Shift_15_UNCONNECTED; - wire NLW_U0_Dbg_Shift_16_UNCONNECTED; - wire NLW_U0_Dbg_Shift_17_UNCONNECTED; - wire NLW_U0_Dbg_Shift_18_UNCONNECTED; - wire NLW_U0_Dbg_Shift_19_UNCONNECTED; - wire NLW_U0_Dbg_Shift_2_UNCONNECTED; - wire NLW_U0_Dbg_Shift_20_UNCONNECTED; - wire NLW_U0_Dbg_Shift_21_UNCONNECTED; - wire NLW_U0_Dbg_Shift_22_UNCONNECTED; - wire NLW_U0_Dbg_Shift_23_UNCONNECTED; - wire NLW_U0_Dbg_Shift_24_UNCONNECTED; - wire NLW_U0_Dbg_Shift_25_UNCONNECTED; - wire NLW_U0_Dbg_Shift_26_UNCONNECTED; - wire NLW_U0_Dbg_Shift_27_UNCONNECTED; - wire NLW_U0_Dbg_Shift_28_UNCONNECTED; - wire NLW_U0_Dbg_Shift_29_UNCONNECTED; - wire NLW_U0_Dbg_Shift_3_UNCONNECTED; - wire NLW_U0_Dbg_Shift_30_UNCONNECTED; - wire NLW_U0_Dbg_Shift_31_UNCONNECTED; - wire NLW_U0_Dbg_Shift_4_UNCONNECTED; - wire NLW_U0_Dbg_Shift_5_UNCONNECTED; - wire NLW_U0_Dbg_Shift_6_UNCONNECTED; - wire NLW_U0_Dbg_Shift_7_UNCONNECTED; - wire NLW_U0_Dbg_Shift_8_UNCONNECTED; - wire NLW_U0_Dbg_Shift_9_UNCONNECTED; - wire NLW_U0_Dbg_TDI_1_UNCONNECTED; - wire NLW_U0_Dbg_TDI_10_UNCONNECTED; - wire NLW_U0_Dbg_TDI_11_UNCONNECTED; - wire NLW_U0_Dbg_TDI_12_UNCONNECTED; - wire NLW_U0_Dbg_TDI_13_UNCONNECTED; - wire NLW_U0_Dbg_TDI_14_UNCONNECTED; - wire NLW_U0_Dbg_TDI_15_UNCONNECTED; - wire NLW_U0_Dbg_TDI_16_UNCONNECTED; - wire NLW_U0_Dbg_TDI_17_UNCONNECTED; - wire NLW_U0_Dbg_TDI_18_UNCONNECTED; - wire NLW_U0_Dbg_TDI_19_UNCONNECTED; - wire NLW_U0_Dbg_TDI_2_UNCONNECTED; - wire NLW_U0_Dbg_TDI_20_UNCONNECTED; - wire NLW_U0_Dbg_TDI_21_UNCONNECTED; - wire NLW_U0_Dbg_TDI_22_UNCONNECTED; - wire NLW_U0_Dbg_TDI_23_UNCONNECTED; - wire NLW_U0_Dbg_TDI_24_UNCONNECTED; - wire NLW_U0_Dbg_TDI_25_UNCONNECTED; - wire NLW_U0_Dbg_TDI_26_UNCONNECTED; - wire NLW_U0_Dbg_TDI_27_UNCONNECTED; - wire NLW_U0_Dbg_TDI_28_UNCONNECTED; - wire NLW_U0_Dbg_TDI_29_UNCONNECTED; - wire NLW_U0_Dbg_TDI_3_UNCONNECTED; - wire NLW_U0_Dbg_TDI_30_UNCONNECTED; - wire NLW_U0_Dbg_TDI_31_UNCONNECTED; - wire NLW_U0_Dbg_TDI_4_UNCONNECTED; - wire NLW_U0_Dbg_TDI_5_UNCONNECTED; - wire NLW_U0_Dbg_TDI_6_UNCONNECTED; - wire NLW_U0_Dbg_TDI_7_UNCONNECTED; - wire NLW_U0_Dbg_TDI_8_UNCONNECTED; - wire NLW_U0_Dbg_TDI_9_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_0_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_1_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_10_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_11_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_12_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_13_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_14_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_15_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_16_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_17_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_18_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_19_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_2_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_20_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_21_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_22_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_23_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_24_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_25_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_26_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_27_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_28_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_29_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_3_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_30_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_31_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_4_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_5_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_6_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_7_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_8_UNCONNECTED; - wire NLW_U0_Dbg_TrClk_9_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_0_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_1_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_10_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_11_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_12_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_13_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_14_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_15_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_16_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_17_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_18_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_19_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_2_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_20_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_21_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_22_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_23_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_24_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_25_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_26_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_27_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_28_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_29_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_3_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_30_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_31_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_4_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_5_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_6_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_7_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_8_UNCONNECTED; - wire NLW_U0_Dbg_TrReady_9_UNCONNECTED; - wire NLW_U0_Dbg_Update_1_UNCONNECTED; - wire NLW_U0_Dbg_Update_10_UNCONNECTED; - wire NLW_U0_Dbg_Update_11_UNCONNECTED; - wire NLW_U0_Dbg_Update_12_UNCONNECTED; - wire NLW_U0_Dbg_Update_13_UNCONNECTED; - wire NLW_U0_Dbg_Update_14_UNCONNECTED; - wire NLW_U0_Dbg_Update_15_UNCONNECTED; - wire NLW_U0_Dbg_Update_16_UNCONNECTED; - wire NLW_U0_Dbg_Update_17_UNCONNECTED; - wire NLW_U0_Dbg_Update_18_UNCONNECTED; - wire NLW_U0_Dbg_Update_19_UNCONNECTED; - wire NLW_U0_Dbg_Update_2_UNCONNECTED; - wire NLW_U0_Dbg_Update_20_UNCONNECTED; - wire NLW_U0_Dbg_Update_21_UNCONNECTED; - wire NLW_U0_Dbg_Update_22_UNCONNECTED; - wire NLW_U0_Dbg_Update_23_UNCONNECTED; - wire NLW_U0_Dbg_Update_24_UNCONNECTED; - wire NLW_U0_Dbg_Update_25_UNCONNECTED; - wire NLW_U0_Dbg_Update_26_UNCONNECTED; - wire NLW_U0_Dbg_Update_27_UNCONNECTED; - wire NLW_U0_Dbg_Update_28_UNCONNECTED; - wire NLW_U0_Dbg_Update_29_UNCONNECTED; - wire NLW_U0_Dbg_Update_3_UNCONNECTED; - wire NLW_U0_Dbg_Update_30_UNCONNECTED; - wire NLW_U0_Dbg_Update_31_UNCONNECTED; - wire NLW_U0_Dbg_Update_4_UNCONNECTED; - wire NLW_U0_Dbg_Update_5_UNCONNECTED; - wire NLW_U0_Dbg_Update_6_UNCONNECTED; - wire NLW_U0_Dbg_Update_7_UNCONNECTED; - wire NLW_U0_Dbg_Update_8_UNCONNECTED; - wire NLW_U0_Dbg_Update_9_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_0_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_1_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_10_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_11_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_12_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_13_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_14_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_15_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_16_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_17_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_18_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_19_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_2_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_20_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_21_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_22_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_23_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_24_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_25_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_26_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_27_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_28_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_29_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_3_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_30_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_31_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_4_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_5_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_6_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_7_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_8_UNCONNECTED; - wire NLW_U0_Dbg_WVALID_9_UNCONNECTED; - wire NLW_U0_Ext_BRK_UNCONNECTED; - wire NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED; - wire NLW_U0_Ext_JTAG_DRCK_UNCONNECTED; - wire NLW_U0_Ext_JTAG_RESET_UNCONNECTED; - wire NLW_U0_Ext_JTAG_SEL_UNCONNECTED; - wire NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED; - wire NLW_U0_Ext_JTAG_TDI_UNCONNECTED; - wire NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED; - wire NLW_U0_Ext_NM_BRK_UNCONNECTED; - wire NLW_U0_Interrupt_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED; - wire NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_0_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_1_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_10_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_11_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_12_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_13_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_14_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_15_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_16_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_17_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_18_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_19_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_2_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_20_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_21_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_22_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_23_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_24_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_25_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_26_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_27_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_28_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_29_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_3_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_30_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_31_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_4_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_5_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_6_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_7_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_8_UNCONNECTED; - wire NLW_U0_LMB_Read_Strobe_9_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_0_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_1_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_10_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_11_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_12_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_13_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_14_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_15_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_16_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_17_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_18_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_19_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_2_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_20_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_21_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_22_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_23_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_24_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_25_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_26_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_27_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_28_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_29_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_3_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_30_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_31_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_4_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_5_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_6_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_7_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_8_UNCONNECTED; - wire NLW_U0_LMB_Write_Strobe_9_UNCONNECTED; - wire NLW_U0_M_AXIS_TVALID_UNCONNECTED; - wire NLW_U0_M_AXI_ARLOCK_UNCONNECTED; - wire NLW_U0_M_AXI_ARVALID_UNCONNECTED; - wire NLW_U0_M_AXI_AWLOCK_UNCONNECTED; - wire NLW_U0_M_AXI_AWVALID_UNCONNECTED; - wire NLW_U0_M_AXI_BREADY_UNCONNECTED; - wire NLW_U0_M_AXI_RREADY_UNCONNECTED; - wire NLW_U0_M_AXI_WLAST_UNCONNECTED; - wire NLW_U0_M_AXI_WVALID_UNCONNECTED; - wire NLW_U0_S_AXI_ARREADY_UNCONNECTED; - wire NLW_U0_S_AXI_AWREADY_UNCONNECTED; - wire NLW_U0_S_AXI_BVALID_UNCONNECTED; - wire NLW_U0_S_AXI_RVALID_UNCONNECTED; - wire NLW_U0_S_AXI_WREADY_UNCONNECTED; - wire NLW_U0_TRACE_CLK_OUT_UNCONNECTED; - wire NLW_U0_TRACE_CTL_UNCONNECTED; - wire NLW_U0_Trig_Ack_In_0_UNCONNECTED; - wire NLW_U0_Trig_Ack_In_1_UNCONNECTED; - wire NLW_U0_Trig_Ack_In_2_UNCONNECTED; - wire NLW_U0_Trig_Ack_In_3_UNCONNECTED; - wire NLW_U0_Trig_Out_0_UNCONNECTED; - wire NLW_U0_Trig_Out_1_UNCONNECTED; - wire NLW_U0_Trig_Out_2_UNCONNECTED; - wire NLW_U0_Trig_Out_3_UNCONNECTED; - wire NLW_U0_bscan_ext_tdo_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_0_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_1_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_10_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_11_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_12_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_13_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_14_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_15_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_16_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_17_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_18_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_19_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_2_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_20_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_21_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_22_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_23_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_24_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_25_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_26_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_27_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_28_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_29_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_3_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_30_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_31_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_4_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_5_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_6_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_7_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_8_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_ARADDR_9_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_0_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_1_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_10_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_11_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_12_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_13_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_14_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_15_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_16_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_17_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_18_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_19_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_2_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_20_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_21_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_22_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_23_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_24_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_25_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_26_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_27_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_28_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_29_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_3_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_30_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_31_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_4_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_5_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_6_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_7_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_8_UNCONNECTED; - wire [14:2]NLW_U0_Dbg_AWADDR_9_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_1_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_10_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_11_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_12_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_13_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_14_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_15_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_16_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_17_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_18_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_19_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_2_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_20_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_21_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_22_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_23_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_24_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_25_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_26_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_27_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_28_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_29_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_3_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_30_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_31_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_4_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_5_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_6_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_7_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_8_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Reg_En_9_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_0_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_1_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_10_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_11_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_12_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_13_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_14_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_15_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_16_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_17_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_18_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_19_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_2_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_20_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_21_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_22_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_23_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_24_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_25_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_26_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_27_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_28_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_29_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_3_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_30_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_31_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_4_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_5_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_6_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_7_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_8_UNCONNECTED; - wire [0:7]NLW_U0_Dbg_Trig_Out_9_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_0_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_1_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_10_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_11_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_12_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_13_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_14_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_15_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_16_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_17_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_18_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_19_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_2_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_20_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_21_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_22_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_23_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_24_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_25_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_26_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_27_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_28_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_29_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_3_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_30_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_31_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_4_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_5_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_6_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_7_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_8_UNCONNECTED; - wire [31:0]NLW_U0_Dbg_WDATA_9_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_0_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_1_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_10_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_11_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_12_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_13_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_14_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_15_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_16_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_17_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_18_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_19_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_2_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_20_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_21_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_22_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_23_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_24_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_25_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_26_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_27_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_28_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_29_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_3_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_30_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_31_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_4_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_5_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_6_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_7_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_8_UNCONNECTED; - wire [0:3]NLW_U0_LMB_Byte_Enable_9_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_0_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_1_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_10_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_11_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_12_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_13_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_14_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_15_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_16_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_17_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_18_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_19_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_2_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_20_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_21_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_22_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_23_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_24_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_25_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_26_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_27_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_28_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_29_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_3_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_30_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_31_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_4_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_5_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_6_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_7_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_8_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Addr_9_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_0_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_1_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_10_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_11_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_12_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_13_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_14_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_15_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_16_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_17_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_18_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_19_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_2_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_20_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_21_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_22_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_23_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_24_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_25_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_26_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_27_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_28_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_29_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_3_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_30_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_31_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_4_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_5_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_6_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_7_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_8_UNCONNECTED; - wire [0:31]NLW_U0_LMB_Data_Write_9_UNCONNECTED; - wire [31:0]NLW_U0_M_AXIS_TDATA_UNCONNECTED; - wire [6:0]NLW_U0_M_AXIS_TID_UNCONNECTED; - wire [31:0]NLW_U0_M_AXI_ARADDR_UNCONNECTED; - wire [1:0]NLW_U0_M_AXI_ARBURST_UNCONNECTED; - wire [3:0]NLW_U0_M_AXI_ARCACHE_UNCONNECTED; - wire [0:0]NLW_U0_M_AXI_ARID_UNCONNECTED; - wire [7:0]NLW_U0_M_AXI_ARLEN_UNCONNECTED; - wire [2:0]NLW_U0_M_AXI_ARPROT_UNCONNECTED; - wire [3:0]NLW_U0_M_AXI_ARQOS_UNCONNECTED; - wire [2:0]NLW_U0_M_AXI_ARSIZE_UNCONNECTED; - wire [31:0]NLW_U0_M_AXI_AWADDR_UNCONNECTED; - wire [1:0]NLW_U0_M_AXI_AWBURST_UNCONNECTED; - wire [3:0]NLW_U0_M_AXI_AWCACHE_UNCONNECTED; - wire [0:0]NLW_U0_M_AXI_AWID_UNCONNECTED; - wire [7:0]NLW_U0_M_AXI_AWLEN_UNCONNECTED; - wire [2:0]NLW_U0_M_AXI_AWPROT_UNCONNECTED; - wire [3:0]NLW_U0_M_AXI_AWQOS_UNCONNECTED; - wire [2:0]NLW_U0_M_AXI_AWSIZE_UNCONNECTED; - wire [31:0]NLW_U0_M_AXI_WDATA_UNCONNECTED; - wire [3:0]NLW_U0_M_AXI_WSTRB_UNCONNECTED; - wire [1:0]NLW_U0_S_AXI_BRESP_UNCONNECTED; - wire [31:0]NLW_U0_S_AXI_RDATA_UNCONNECTED; - wire [1:0]NLW_U0_S_AXI_RRESP_UNCONNECTED; - wire [31:0]NLW_U0_TRACE_DATA_UNCONNECTED; - - (* C_ADDR_SIZE = "32" *) - (* C_AVOID_PRIMITIVES = "0" *) - (* C_BSCANID = "76547328" *) - (* C_DATA_SIZE = "32" *) - (* C_DBG_MEM_ACCESS = "0" *) - (* C_DBG_REG_ACCESS = "0" *) - (* C_DEBUG_INTERFACE = "0" *) - (* C_EXT_TRIG_RESET_VALUE = "20'b11110001001000110100" *) - (* C_FAMILY = "kintex7" *) - (* C_INTERCONNECT = "2" *) - (* C_JTAG_CHAIN = "2" *) - (* C_MB_DBG_PORTS = "1" *) - (* C_M_AXIS_DATA_WIDTH = "32" *) - (* C_M_AXIS_ID_WIDTH = "7" *) - (* C_M_AXI_ADDR_WIDTH = "32" *) - (* C_M_AXI_DATA_WIDTH = "32" *) - (* C_M_AXI_THREAD_ID_WIDTH = "1" *) - (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *) - (* C_S_AXI_ADDR_WIDTH = "4" *) - (* C_S_AXI_DATA_WIDTH = "32" *) - (* C_TRACE_ASYNC_RESET = "0" *) - (* C_TRACE_CLK_FREQ_HZ = "200000000" *) - (* C_TRACE_CLK_OUT_PHASE = "90" *) - (* C_TRACE_DATA_WIDTH = "32" *) - (* C_TRACE_ID = "110" *) - (* C_TRACE_OUTPUT = "0" *) - (* C_TRACE_PROTOCOL = "1" *) - (* C_USE_BSCAN = "0" *) - (* C_USE_CONFIG_RESET = "0" *) - (* C_USE_CROSS_TRIGGER = "0" *) - (* C_USE_UART = "0" *) - system_bd_mdm_0_MDM U0 - (.Config_Reset(1'b0), - .Dbg_ARADDR_0(NLW_U0_Dbg_ARADDR_0_UNCONNECTED[14:2]), - .Dbg_ARADDR_1(NLW_U0_Dbg_ARADDR_1_UNCONNECTED[14:2]), - .Dbg_ARADDR_10(NLW_U0_Dbg_ARADDR_10_UNCONNECTED[14:2]), - .Dbg_ARADDR_11(NLW_U0_Dbg_ARADDR_11_UNCONNECTED[14:2]), - .Dbg_ARADDR_12(NLW_U0_Dbg_ARADDR_12_UNCONNECTED[14:2]), - .Dbg_ARADDR_13(NLW_U0_Dbg_ARADDR_13_UNCONNECTED[14:2]), - .Dbg_ARADDR_14(NLW_U0_Dbg_ARADDR_14_UNCONNECTED[14:2]), - .Dbg_ARADDR_15(NLW_U0_Dbg_ARADDR_15_UNCONNECTED[14:2]), - .Dbg_ARADDR_16(NLW_U0_Dbg_ARADDR_16_UNCONNECTED[14:2]), - .Dbg_ARADDR_17(NLW_U0_Dbg_ARADDR_17_UNCONNECTED[14:2]), - .Dbg_ARADDR_18(NLW_U0_Dbg_ARADDR_18_UNCONNECTED[14:2]), - .Dbg_ARADDR_19(NLW_U0_Dbg_ARADDR_19_UNCONNECTED[14:2]), - .Dbg_ARADDR_2(NLW_U0_Dbg_ARADDR_2_UNCONNECTED[14:2]), - .Dbg_ARADDR_20(NLW_U0_Dbg_ARADDR_20_UNCONNECTED[14:2]), - .Dbg_ARADDR_21(NLW_U0_Dbg_ARADDR_21_UNCONNECTED[14:2]), - .Dbg_ARADDR_22(NLW_U0_Dbg_ARADDR_22_UNCONNECTED[14:2]), - .Dbg_ARADDR_23(NLW_U0_Dbg_ARADDR_23_UNCONNECTED[14:2]), - .Dbg_ARADDR_24(NLW_U0_Dbg_ARADDR_24_UNCONNECTED[14:2]), - .Dbg_ARADDR_25(NLW_U0_Dbg_ARADDR_25_UNCONNECTED[14:2]), - .Dbg_ARADDR_26(NLW_U0_Dbg_ARADDR_26_UNCONNECTED[14:2]), - .Dbg_ARADDR_27(NLW_U0_Dbg_ARADDR_27_UNCONNECTED[14:2]), - .Dbg_ARADDR_28(NLW_U0_Dbg_ARADDR_28_UNCONNECTED[14:2]), - .Dbg_ARADDR_29(NLW_U0_Dbg_ARADDR_29_UNCONNECTED[14:2]), - .Dbg_ARADDR_3(NLW_U0_Dbg_ARADDR_3_UNCONNECTED[14:2]), - .Dbg_ARADDR_30(NLW_U0_Dbg_ARADDR_30_UNCONNECTED[14:2]), - .Dbg_ARADDR_31(NLW_U0_Dbg_ARADDR_31_UNCONNECTED[14:2]), - .Dbg_ARADDR_4(NLW_U0_Dbg_ARADDR_4_UNCONNECTED[14:2]), - .Dbg_ARADDR_5(NLW_U0_Dbg_ARADDR_5_UNCONNECTED[14:2]), - .Dbg_ARADDR_6(NLW_U0_Dbg_ARADDR_6_UNCONNECTED[14:2]), - .Dbg_ARADDR_7(NLW_U0_Dbg_ARADDR_7_UNCONNECTED[14:2]), - .Dbg_ARADDR_8(NLW_U0_Dbg_ARADDR_8_UNCONNECTED[14:2]), - .Dbg_ARADDR_9(NLW_U0_Dbg_ARADDR_9_UNCONNECTED[14:2]), - .Dbg_ARREADY_0(1'b0), - .Dbg_ARREADY_1(1'b0), - .Dbg_ARREADY_10(1'b0), - .Dbg_ARREADY_11(1'b0), - .Dbg_ARREADY_12(1'b0), - .Dbg_ARREADY_13(1'b0), - .Dbg_ARREADY_14(1'b0), - .Dbg_ARREADY_15(1'b0), - .Dbg_ARREADY_16(1'b0), - .Dbg_ARREADY_17(1'b0), - .Dbg_ARREADY_18(1'b0), - .Dbg_ARREADY_19(1'b0), - .Dbg_ARREADY_2(1'b0), - .Dbg_ARREADY_20(1'b0), - .Dbg_ARREADY_21(1'b0), - .Dbg_ARREADY_22(1'b0), - .Dbg_ARREADY_23(1'b0), - .Dbg_ARREADY_24(1'b0), - .Dbg_ARREADY_25(1'b0), - .Dbg_ARREADY_26(1'b0), - .Dbg_ARREADY_27(1'b0), - .Dbg_ARREADY_28(1'b0), - .Dbg_ARREADY_29(1'b0), - .Dbg_ARREADY_3(1'b0), - .Dbg_ARREADY_30(1'b0), - .Dbg_ARREADY_31(1'b0), - .Dbg_ARREADY_4(1'b0), - .Dbg_ARREADY_5(1'b0), - .Dbg_ARREADY_6(1'b0), - .Dbg_ARREADY_7(1'b0), - .Dbg_ARREADY_8(1'b0), - .Dbg_ARREADY_9(1'b0), - .Dbg_ARVALID_0(NLW_U0_Dbg_ARVALID_0_UNCONNECTED), - .Dbg_ARVALID_1(NLW_U0_Dbg_ARVALID_1_UNCONNECTED), - .Dbg_ARVALID_10(NLW_U0_Dbg_ARVALID_10_UNCONNECTED), - .Dbg_ARVALID_11(NLW_U0_Dbg_ARVALID_11_UNCONNECTED), - .Dbg_ARVALID_12(NLW_U0_Dbg_ARVALID_12_UNCONNECTED), - .Dbg_ARVALID_13(NLW_U0_Dbg_ARVALID_13_UNCONNECTED), - .Dbg_ARVALID_14(NLW_U0_Dbg_ARVALID_14_UNCONNECTED), - .Dbg_ARVALID_15(NLW_U0_Dbg_ARVALID_15_UNCONNECTED), - .Dbg_ARVALID_16(NLW_U0_Dbg_ARVALID_16_UNCONNECTED), - .Dbg_ARVALID_17(NLW_U0_Dbg_ARVALID_17_UNCONNECTED), - .Dbg_ARVALID_18(NLW_U0_Dbg_ARVALID_18_UNCONNECTED), - .Dbg_ARVALID_19(NLW_U0_Dbg_ARVALID_19_UNCONNECTED), - .Dbg_ARVALID_2(NLW_U0_Dbg_ARVALID_2_UNCONNECTED), - .Dbg_ARVALID_20(NLW_U0_Dbg_ARVALID_20_UNCONNECTED), - .Dbg_ARVALID_21(NLW_U0_Dbg_ARVALID_21_UNCONNECTED), - .Dbg_ARVALID_22(NLW_U0_Dbg_ARVALID_22_UNCONNECTED), - .Dbg_ARVALID_23(NLW_U0_Dbg_ARVALID_23_UNCONNECTED), - .Dbg_ARVALID_24(NLW_U0_Dbg_ARVALID_24_UNCONNECTED), - .Dbg_ARVALID_25(NLW_U0_Dbg_ARVALID_25_UNCONNECTED), - .Dbg_ARVALID_26(NLW_U0_Dbg_ARVALID_26_UNCONNECTED), - .Dbg_ARVALID_27(NLW_U0_Dbg_ARVALID_27_UNCONNECTED), - .Dbg_ARVALID_28(NLW_U0_Dbg_ARVALID_28_UNCONNECTED), - .Dbg_ARVALID_29(NLW_U0_Dbg_ARVALID_29_UNCONNECTED), - .Dbg_ARVALID_3(NLW_U0_Dbg_ARVALID_3_UNCONNECTED), - .Dbg_ARVALID_30(NLW_U0_Dbg_ARVALID_30_UNCONNECTED), - .Dbg_ARVALID_31(NLW_U0_Dbg_ARVALID_31_UNCONNECTED), - .Dbg_ARVALID_4(NLW_U0_Dbg_ARVALID_4_UNCONNECTED), - .Dbg_ARVALID_5(NLW_U0_Dbg_ARVALID_5_UNCONNECTED), - .Dbg_ARVALID_6(NLW_U0_Dbg_ARVALID_6_UNCONNECTED), - .Dbg_ARVALID_7(NLW_U0_Dbg_ARVALID_7_UNCONNECTED), - .Dbg_ARVALID_8(NLW_U0_Dbg_ARVALID_8_UNCONNECTED), - .Dbg_ARVALID_9(NLW_U0_Dbg_ARVALID_9_UNCONNECTED), - .Dbg_AWADDR_0(NLW_U0_Dbg_AWADDR_0_UNCONNECTED[14:2]), - .Dbg_AWADDR_1(NLW_U0_Dbg_AWADDR_1_UNCONNECTED[14:2]), - .Dbg_AWADDR_10(NLW_U0_Dbg_AWADDR_10_UNCONNECTED[14:2]), - .Dbg_AWADDR_11(NLW_U0_Dbg_AWADDR_11_UNCONNECTED[14:2]), - .Dbg_AWADDR_12(NLW_U0_Dbg_AWADDR_12_UNCONNECTED[14:2]), - .Dbg_AWADDR_13(NLW_U0_Dbg_AWADDR_13_UNCONNECTED[14:2]), - .Dbg_AWADDR_14(NLW_U0_Dbg_AWADDR_14_UNCONNECTED[14:2]), - .Dbg_AWADDR_15(NLW_U0_Dbg_AWADDR_15_UNCONNECTED[14:2]), - .Dbg_AWADDR_16(NLW_U0_Dbg_AWADDR_16_UNCONNECTED[14:2]), - .Dbg_AWADDR_17(NLW_U0_Dbg_AWADDR_17_UNCONNECTED[14:2]), - .Dbg_AWADDR_18(NLW_U0_Dbg_AWADDR_18_UNCONNECTED[14:2]), - .Dbg_AWADDR_19(NLW_U0_Dbg_AWADDR_19_UNCONNECTED[14:2]), - .Dbg_AWADDR_2(NLW_U0_Dbg_AWADDR_2_UNCONNECTED[14:2]), - .Dbg_AWADDR_20(NLW_U0_Dbg_AWADDR_20_UNCONNECTED[14:2]), - .Dbg_AWADDR_21(NLW_U0_Dbg_AWADDR_21_UNCONNECTED[14:2]), - .Dbg_AWADDR_22(NLW_U0_Dbg_AWADDR_22_UNCONNECTED[14:2]), - .Dbg_AWADDR_23(NLW_U0_Dbg_AWADDR_23_UNCONNECTED[14:2]), - .Dbg_AWADDR_24(NLW_U0_Dbg_AWADDR_24_UNCONNECTED[14:2]), - .Dbg_AWADDR_25(NLW_U0_Dbg_AWADDR_25_UNCONNECTED[14:2]), - .Dbg_AWADDR_26(NLW_U0_Dbg_AWADDR_26_UNCONNECTED[14:2]), - .Dbg_AWADDR_27(NLW_U0_Dbg_AWADDR_27_UNCONNECTED[14:2]), - .Dbg_AWADDR_28(NLW_U0_Dbg_AWADDR_28_UNCONNECTED[14:2]), - .Dbg_AWADDR_29(NLW_U0_Dbg_AWADDR_29_UNCONNECTED[14:2]), - .Dbg_AWADDR_3(NLW_U0_Dbg_AWADDR_3_UNCONNECTED[14:2]), - .Dbg_AWADDR_30(NLW_U0_Dbg_AWADDR_30_UNCONNECTED[14:2]), - .Dbg_AWADDR_31(NLW_U0_Dbg_AWADDR_31_UNCONNECTED[14:2]), - .Dbg_AWADDR_4(NLW_U0_Dbg_AWADDR_4_UNCONNECTED[14:2]), - .Dbg_AWADDR_5(NLW_U0_Dbg_AWADDR_5_UNCONNECTED[14:2]), - .Dbg_AWADDR_6(NLW_U0_Dbg_AWADDR_6_UNCONNECTED[14:2]), - .Dbg_AWADDR_7(NLW_U0_Dbg_AWADDR_7_UNCONNECTED[14:2]), - .Dbg_AWADDR_8(NLW_U0_Dbg_AWADDR_8_UNCONNECTED[14:2]), - .Dbg_AWADDR_9(NLW_U0_Dbg_AWADDR_9_UNCONNECTED[14:2]), - .Dbg_AWREADY_0(1'b0), - .Dbg_AWREADY_1(1'b0), - .Dbg_AWREADY_10(1'b0), - .Dbg_AWREADY_11(1'b0), - .Dbg_AWREADY_12(1'b0), - .Dbg_AWREADY_13(1'b0), - .Dbg_AWREADY_14(1'b0), - .Dbg_AWREADY_15(1'b0), - .Dbg_AWREADY_16(1'b0), - .Dbg_AWREADY_17(1'b0), - .Dbg_AWREADY_18(1'b0), - .Dbg_AWREADY_19(1'b0), - .Dbg_AWREADY_2(1'b0), - .Dbg_AWREADY_20(1'b0), - .Dbg_AWREADY_21(1'b0), - .Dbg_AWREADY_22(1'b0), - .Dbg_AWREADY_23(1'b0), - .Dbg_AWREADY_24(1'b0), - .Dbg_AWREADY_25(1'b0), - .Dbg_AWREADY_26(1'b0), - .Dbg_AWREADY_27(1'b0), - .Dbg_AWREADY_28(1'b0), - .Dbg_AWREADY_29(1'b0), - .Dbg_AWREADY_3(1'b0), - .Dbg_AWREADY_30(1'b0), - .Dbg_AWREADY_31(1'b0), - .Dbg_AWREADY_4(1'b0), - .Dbg_AWREADY_5(1'b0), - .Dbg_AWREADY_6(1'b0), - .Dbg_AWREADY_7(1'b0), - .Dbg_AWREADY_8(1'b0), - .Dbg_AWREADY_9(1'b0), - .Dbg_AWVALID_0(NLW_U0_Dbg_AWVALID_0_UNCONNECTED), - .Dbg_AWVALID_1(NLW_U0_Dbg_AWVALID_1_UNCONNECTED), - .Dbg_AWVALID_10(NLW_U0_Dbg_AWVALID_10_UNCONNECTED), - .Dbg_AWVALID_11(NLW_U0_Dbg_AWVALID_11_UNCONNECTED), - .Dbg_AWVALID_12(NLW_U0_Dbg_AWVALID_12_UNCONNECTED), - .Dbg_AWVALID_13(NLW_U0_Dbg_AWVALID_13_UNCONNECTED), - .Dbg_AWVALID_14(NLW_U0_Dbg_AWVALID_14_UNCONNECTED), - .Dbg_AWVALID_15(NLW_U0_Dbg_AWVALID_15_UNCONNECTED), - .Dbg_AWVALID_16(NLW_U0_Dbg_AWVALID_16_UNCONNECTED), - .Dbg_AWVALID_17(NLW_U0_Dbg_AWVALID_17_UNCONNECTED), - .Dbg_AWVALID_18(NLW_U0_Dbg_AWVALID_18_UNCONNECTED), - .Dbg_AWVALID_19(NLW_U0_Dbg_AWVALID_19_UNCONNECTED), - .Dbg_AWVALID_2(NLW_U0_Dbg_AWVALID_2_UNCONNECTED), - .Dbg_AWVALID_20(NLW_U0_Dbg_AWVALID_20_UNCONNECTED), - .Dbg_AWVALID_21(NLW_U0_Dbg_AWVALID_21_UNCONNECTED), - .Dbg_AWVALID_22(NLW_U0_Dbg_AWVALID_22_UNCONNECTED), - .Dbg_AWVALID_23(NLW_U0_Dbg_AWVALID_23_UNCONNECTED), - .Dbg_AWVALID_24(NLW_U0_Dbg_AWVALID_24_UNCONNECTED), - .Dbg_AWVALID_25(NLW_U0_Dbg_AWVALID_25_UNCONNECTED), - .Dbg_AWVALID_26(NLW_U0_Dbg_AWVALID_26_UNCONNECTED), - .Dbg_AWVALID_27(NLW_U0_Dbg_AWVALID_27_UNCONNECTED), - .Dbg_AWVALID_28(NLW_U0_Dbg_AWVALID_28_UNCONNECTED), - .Dbg_AWVALID_29(NLW_U0_Dbg_AWVALID_29_UNCONNECTED), - .Dbg_AWVALID_3(NLW_U0_Dbg_AWVALID_3_UNCONNECTED), - .Dbg_AWVALID_30(NLW_U0_Dbg_AWVALID_30_UNCONNECTED), - .Dbg_AWVALID_31(NLW_U0_Dbg_AWVALID_31_UNCONNECTED), - .Dbg_AWVALID_4(NLW_U0_Dbg_AWVALID_4_UNCONNECTED), - .Dbg_AWVALID_5(NLW_U0_Dbg_AWVALID_5_UNCONNECTED), - .Dbg_AWVALID_6(NLW_U0_Dbg_AWVALID_6_UNCONNECTED), - .Dbg_AWVALID_7(NLW_U0_Dbg_AWVALID_7_UNCONNECTED), - .Dbg_AWVALID_8(NLW_U0_Dbg_AWVALID_8_UNCONNECTED), - .Dbg_AWVALID_9(NLW_U0_Dbg_AWVALID_9_UNCONNECTED), - .Dbg_BREADY_0(NLW_U0_Dbg_BREADY_0_UNCONNECTED), - .Dbg_BREADY_1(NLW_U0_Dbg_BREADY_1_UNCONNECTED), - .Dbg_BREADY_10(NLW_U0_Dbg_BREADY_10_UNCONNECTED), - .Dbg_BREADY_11(NLW_U0_Dbg_BREADY_11_UNCONNECTED), - .Dbg_BREADY_12(NLW_U0_Dbg_BREADY_12_UNCONNECTED), - .Dbg_BREADY_13(NLW_U0_Dbg_BREADY_13_UNCONNECTED), - .Dbg_BREADY_14(NLW_U0_Dbg_BREADY_14_UNCONNECTED), - .Dbg_BREADY_15(NLW_U0_Dbg_BREADY_15_UNCONNECTED), - .Dbg_BREADY_16(NLW_U0_Dbg_BREADY_16_UNCONNECTED), - .Dbg_BREADY_17(NLW_U0_Dbg_BREADY_17_UNCONNECTED), - .Dbg_BREADY_18(NLW_U0_Dbg_BREADY_18_UNCONNECTED), - .Dbg_BREADY_19(NLW_U0_Dbg_BREADY_19_UNCONNECTED), - .Dbg_BREADY_2(NLW_U0_Dbg_BREADY_2_UNCONNECTED), - .Dbg_BREADY_20(NLW_U0_Dbg_BREADY_20_UNCONNECTED), - .Dbg_BREADY_21(NLW_U0_Dbg_BREADY_21_UNCONNECTED), - .Dbg_BREADY_22(NLW_U0_Dbg_BREADY_22_UNCONNECTED), - .Dbg_BREADY_23(NLW_U0_Dbg_BREADY_23_UNCONNECTED), - .Dbg_BREADY_24(NLW_U0_Dbg_BREADY_24_UNCONNECTED), - .Dbg_BREADY_25(NLW_U0_Dbg_BREADY_25_UNCONNECTED), - .Dbg_BREADY_26(NLW_U0_Dbg_BREADY_26_UNCONNECTED), - .Dbg_BREADY_27(NLW_U0_Dbg_BREADY_27_UNCONNECTED), - .Dbg_BREADY_28(NLW_U0_Dbg_BREADY_28_UNCONNECTED), - .Dbg_BREADY_29(NLW_U0_Dbg_BREADY_29_UNCONNECTED), - .Dbg_BREADY_3(NLW_U0_Dbg_BREADY_3_UNCONNECTED), - .Dbg_BREADY_30(NLW_U0_Dbg_BREADY_30_UNCONNECTED), - .Dbg_BREADY_31(NLW_U0_Dbg_BREADY_31_UNCONNECTED), - .Dbg_BREADY_4(NLW_U0_Dbg_BREADY_4_UNCONNECTED), - .Dbg_BREADY_5(NLW_U0_Dbg_BREADY_5_UNCONNECTED), - .Dbg_BREADY_6(NLW_U0_Dbg_BREADY_6_UNCONNECTED), - .Dbg_BREADY_7(NLW_U0_Dbg_BREADY_7_UNCONNECTED), - .Dbg_BREADY_8(NLW_U0_Dbg_BREADY_8_UNCONNECTED), - .Dbg_BREADY_9(NLW_U0_Dbg_BREADY_9_UNCONNECTED), - .Dbg_BRESP_0({1'b0,1'b0}), - .Dbg_BRESP_1({1'b0,1'b0}), - .Dbg_BRESP_10({1'b0,1'b0}), - .Dbg_BRESP_11({1'b0,1'b0}), - .Dbg_BRESP_12({1'b0,1'b0}), - .Dbg_BRESP_13({1'b0,1'b0}), - .Dbg_BRESP_14({1'b0,1'b0}), - .Dbg_BRESP_15({1'b0,1'b0}), - .Dbg_BRESP_16({1'b0,1'b0}), - .Dbg_BRESP_17({1'b0,1'b0}), - .Dbg_BRESP_18({1'b0,1'b0}), - .Dbg_BRESP_19({1'b0,1'b0}), - .Dbg_BRESP_2({1'b0,1'b0}), - .Dbg_BRESP_20({1'b0,1'b0}), - .Dbg_BRESP_21({1'b0,1'b0}), - .Dbg_BRESP_22({1'b0,1'b0}), - .Dbg_BRESP_23({1'b0,1'b0}), - .Dbg_BRESP_24({1'b0,1'b0}), - .Dbg_BRESP_25({1'b0,1'b0}), - .Dbg_BRESP_26({1'b0,1'b0}), - .Dbg_BRESP_27({1'b0,1'b0}), - .Dbg_BRESP_28({1'b0,1'b0}), - .Dbg_BRESP_29({1'b0,1'b0}), - .Dbg_BRESP_3({1'b0,1'b0}), - .Dbg_BRESP_30({1'b0,1'b0}), - .Dbg_BRESP_31({1'b0,1'b0}), - .Dbg_BRESP_4({1'b0,1'b0}), - .Dbg_BRESP_5({1'b0,1'b0}), - .Dbg_BRESP_6({1'b0,1'b0}), - .Dbg_BRESP_7({1'b0,1'b0}), - .Dbg_BRESP_8({1'b0,1'b0}), - .Dbg_BRESP_9({1'b0,1'b0}), - .Dbg_BVALID_0(1'b0), - .Dbg_BVALID_1(1'b0), - .Dbg_BVALID_10(1'b0), - .Dbg_BVALID_11(1'b0), - .Dbg_BVALID_12(1'b0), - .Dbg_BVALID_13(1'b0), - .Dbg_BVALID_14(1'b0), - .Dbg_BVALID_15(1'b0), - .Dbg_BVALID_16(1'b0), - .Dbg_BVALID_17(1'b0), - .Dbg_BVALID_18(1'b0), - .Dbg_BVALID_19(1'b0), - .Dbg_BVALID_2(1'b0), - .Dbg_BVALID_20(1'b0), - .Dbg_BVALID_21(1'b0), - .Dbg_BVALID_22(1'b0), - .Dbg_BVALID_23(1'b0), - .Dbg_BVALID_24(1'b0), - .Dbg_BVALID_25(1'b0), - .Dbg_BVALID_26(1'b0), - .Dbg_BVALID_27(1'b0), - .Dbg_BVALID_28(1'b0), - .Dbg_BVALID_29(1'b0), - .Dbg_BVALID_3(1'b0), - .Dbg_BVALID_30(1'b0), - .Dbg_BVALID_31(1'b0), - .Dbg_BVALID_4(1'b0), - .Dbg_BVALID_5(1'b0), - .Dbg_BVALID_6(1'b0), - .Dbg_BVALID_7(1'b0), - .Dbg_BVALID_8(1'b0), - .Dbg_BVALID_9(1'b0), - .Dbg_Capture_0(Dbg_Capture_0), - .Dbg_Capture_1(NLW_U0_Dbg_Capture_1_UNCONNECTED), - .Dbg_Capture_10(NLW_U0_Dbg_Capture_10_UNCONNECTED), - .Dbg_Capture_11(NLW_U0_Dbg_Capture_11_UNCONNECTED), - .Dbg_Capture_12(NLW_U0_Dbg_Capture_12_UNCONNECTED), - .Dbg_Capture_13(NLW_U0_Dbg_Capture_13_UNCONNECTED), - .Dbg_Capture_14(NLW_U0_Dbg_Capture_14_UNCONNECTED), - .Dbg_Capture_15(NLW_U0_Dbg_Capture_15_UNCONNECTED), - .Dbg_Capture_16(NLW_U0_Dbg_Capture_16_UNCONNECTED), - .Dbg_Capture_17(NLW_U0_Dbg_Capture_17_UNCONNECTED), - .Dbg_Capture_18(NLW_U0_Dbg_Capture_18_UNCONNECTED), - .Dbg_Capture_19(NLW_U0_Dbg_Capture_19_UNCONNECTED), - .Dbg_Capture_2(NLW_U0_Dbg_Capture_2_UNCONNECTED), - .Dbg_Capture_20(NLW_U0_Dbg_Capture_20_UNCONNECTED), - .Dbg_Capture_21(NLW_U0_Dbg_Capture_21_UNCONNECTED), - .Dbg_Capture_22(NLW_U0_Dbg_Capture_22_UNCONNECTED), - .Dbg_Capture_23(NLW_U0_Dbg_Capture_23_UNCONNECTED), - .Dbg_Capture_24(NLW_U0_Dbg_Capture_24_UNCONNECTED), - .Dbg_Capture_25(NLW_U0_Dbg_Capture_25_UNCONNECTED), - .Dbg_Capture_26(NLW_U0_Dbg_Capture_26_UNCONNECTED), - .Dbg_Capture_27(NLW_U0_Dbg_Capture_27_UNCONNECTED), - .Dbg_Capture_28(NLW_U0_Dbg_Capture_28_UNCONNECTED), - .Dbg_Capture_29(NLW_U0_Dbg_Capture_29_UNCONNECTED), - .Dbg_Capture_3(NLW_U0_Dbg_Capture_3_UNCONNECTED), - .Dbg_Capture_30(NLW_U0_Dbg_Capture_30_UNCONNECTED), - .Dbg_Capture_31(NLW_U0_Dbg_Capture_31_UNCONNECTED), - .Dbg_Capture_4(NLW_U0_Dbg_Capture_4_UNCONNECTED), - .Dbg_Capture_5(NLW_U0_Dbg_Capture_5_UNCONNECTED), - .Dbg_Capture_6(NLW_U0_Dbg_Capture_6_UNCONNECTED), - .Dbg_Capture_7(NLW_U0_Dbg_Capture_7_UNCONNECTED), - .Dbg_Capture_8(NLW_U0_Dbg_Capture_8_UNCONNECTED), - .Dbg_Capture_9(NLW_U0_Dbg_Capture_9_UNCONNECTED), - .Dbg_Clk_0(Dbg_Clk_0), - .Dbg_Clk_1(NLW_U0_Dbg_Clk_1_UNCONNECTED), - .Dbg_Clk_10(NLW_U0_Dbg_Clk_10_UNCONNECTED), - .Dbg_Clk_11(NLW_U0_Dbg_Clk_11_UNCONNECTED), - .Dbg_Clk_12(NLW_U0_Dbg_Clk_12_UNCONNECTED), - .Dbg_Clk_13(NLW_U0_Dbg_Clk_13_UNCONNECTED), - .Dbg_Clk_14(NLW_U0_Dbg_Clk_14_UNCONNECTED), - .Dbg_Clk_15(NLW_U0_Dbg_Clk_15_UNCONNECTED), - .Dbg_Clk_16(NLW_U0_Dbg_Clk_16_UNCONNECTED), - .Dbg_Clk_17(NLW_U0_Dbg_Clk_17_UNCONNECTED), - .Dbg_Clk_18(NLW_U0_Dbg_Clk_18_UNCONNECTED), - .Dbg_Clk_19(NLW_U0_Dbg_Clk_19_UNCONNECTED), - .Dbg_Clk_2(NLW_U0_Dbg_Clk_2_UNCONNECTED), - .Dbg_Clk_20(NLW_U0_Dbg_Clk_20_UNCONNECTED), - .Dbg_Clk_21(NLW_U0_Dbg_Clk_21_UNCONNECTED), - .Dbg_Clk_22(NLW_U0_Dbg_Clk_22_UNCONNECTED), - .Dbg_Clk_23(NLW_U0_Dbg_Clk_23_UNCONNECTED), - .Dbg_Clk_24(NLW_U0_Dbg_Clk_24_UNCONNECTED), - .Dbg_Clk_25(NLW_U0_Dbg_Clk_25_UNCONNECTED), - .Dbg_Clk_26(NLW_U0_Dbg_Clk_26_UNCONNECTED), - .Dbg_Clk_27(NLW_U0_Dbg_Clk_27_UNCONNECTED), - .Dbg_Clk_28(NLW_U0_Dbg_Clk_28_UNCONNECTED), - .Dbg_Clk_29(NLW_U0_Dbg_Clk_29_UNCONNECTED), - .Dbg_Clk_3(NLW_U0_Dbg_Clk_3_UNCONNECTED), - .Dbg_Clk_30(NLW_U0_Dbg_Clk_30_UNCONNECTED), - .Dbg_Clk_31(NLW_U0_Dbg_Clk_31_UNCONNECTED), - .Dbg_Clk_4(NLW_U0_Dbg_Clk_4_UNCONNECTED), - .Dbg_Clk_5(NLW_U0_Dbg_Clk_5_UNCONNECTED), - .Dbg_Clk_6(NLW_U0_Dbg_Clk_6_UNCONNECTED), - .Dbg_Clk_7(NLW_U0_Dbg_Clk_7_UNCONNECTED), - .Dbg_Clk_8(NLW_U0_Dbg_Clk_8_UNCONNECTED), - .Dbg_Clk_9(NLW_U0_Dbg_Clk_9_UNCONNECTED), - .Dbg_Disable_0(Dbg_Disable_0), - .Dbg_Disable_1(NLW_U0_Dbg_Disable_1_UNCONNECTED), - .Dbg_Disable_10(NLW_U0_Dbg_Disable_10_UNCONNECTED), - .Dbg_Disable_11(NLW_U0_Dbg_Disable_11_UNCONNECTED), - .Dbg_Disable_12(NLW_U0_Dbg_Disable_12_UNCONNECTED), - .Dbg_Disable_13(NLW_U0_Dbg_Disable_13_UNCONNECTED), - .Dbg_Disable_14(NLW_U0_Dbg_Disable_14_UNCONNECTED), - .Dbg_Disable_15(NLW_U0_Dbg_Disable_15_UNCONNECTED), - .Dbg_Disable_16(NLW_U0_Dbg_Disable_16_UNCONNECTED), - .Dbg_Disable_17(NLW_U0_Dbg_Disable_17_UNCONNECTED), - .Dbg_Disable_18(NLW_U0_Dbg_Disable_18_UNCONNECTED), - .Dbg_Disable_19(NLW_U0_Dbg_Disable_19_UNCONNECTED), - .Dbg_Disable_2(NLW_U0_Dbg_Disable_2_UNCONNECTED), - .Dbg_Disable_20(NLW_U0_Dbg_Disable_20_UNCONNECTED), - .Dbg_Disable_21(NLW_U0_Dbg_Disable_21_UNCONNECTED), - .Dbg_Disable_22(NLW_U0_Dbg_Disable_22_UNCONNECTED), - .Dbg_Disable_23(NLW_U0_Dbg_Disable_23_UNCONNECTED), - .Dbg_Disable_24(NLW_U0_Dbg_Disable_24_UNCONNECTED), - .Dbg_Disable_25(NLW_U0_Dbg_Disable_25_UNCONNECTED), - .Dbg_Disable_26(NLW_U0_Dbg_Disable_26_UNCONNECTED), - .Dbg_Disable_27(NLW_U0_Dbg_Disable_27_UNCONNECTED), - .Dbg_Disable_28(NLW_U0_Dbg_Disable_28_UNCONNECTED), - .Dbg_Disable_29(NLW_U0_Dbg_Disable_29_UNCONNECTED), - .Dbg_Disable_3(NLW_U0_Dbg_Disable_3_UNCONNECTED), - .Dbg_Disable_30(NLW_U0_Dbg_Disable_30_UNCONNECTED), - .Dbg_Disable_31(NLW_U0_Dbg_Disable_31_UNCONNECTED), - .Dbg_Disable_4(NLW_U0_Dbg_Disable_4_UNCONNECTED), - .Dbg_Disable_5(NLW_U0_Dbg_Disable_5_UNCONNECTED), - .Dbg_Disable_6(NLW_U0_Dbg_Disable_6_UNCONNECTED), - .Dbg_Disable_7(NLW_U0_Dbg_Disable_7_UNCONNECTED), - .Dbg_Disable_8(NLW_U0_Dbg_Disable_8_UNCONNECTED), - .Dbg_Disable_9(NLW_U0_Dbg_Disable_9_UNCONNECTED), - .Dbg_RDATA_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RDATA_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_RREADY_0(NLW_U0_Dbg_RREADY_0_UNCONNECTED), - .Dbg_RREADY_1(NLW_U0_Dbg_RREADY_1_UNCONNECTED), - .Dbg_RREADY_10(NLW_U0_Dbg_RREADY_10_UNCONNECTED), - .Dbg_RREADY_11(NLW_U0_Dbg_RREADY_11_UNCONNECTED), - .Dbg_RREADY_12(NLW_U0_Dbg_RREADY_12_UNCONNECTED), - .Dbg_RREADY_13(NLW_U0_Dbg_RREADY_13_UNCONNECTED), - .Dbg_RREADY_14(NLW_U0_Dbg_RREADY_14_UNCONNECTED), - .Dbg_RREADY_15(NLW_U0_Dbg_RREADY_15_UNCONNECTED), - .Dbg_RREADY_16(NLW_U0_Dbg_RREADY_16_UNCONNECTED), - .Dbg_RREADY_17(NLW_U0_Dbg_RREADY_17_UNCONNECTED), - .Dbg_RREADY_18(NLW_U0_Dbg_RREADY_18_UNCONNECTED), - .Dbg_RREADY_19(NLW_U0_Dbg_RREADY_19_UNCONNECTED), - .Dbg_RREADY_2(NLW_U0_Dbg_RREADY_2_UNCONNECTED), - .Dbg_RREADY_20(NLW_U0_Dbg_RREADY_20_UNCONNECTED), - .Dbg_RREADY_21(NLW_U0_Dbg_RREADY_21_UNCONNECTED), - .Dbg_RREADY_22(NLW_U0_Dbg_RREADY_22_UNCONNECTED), - .Dbg_RREADY_23(NLW_U0_Dbg_RREADY_23_UNCONNECTED), - .Dbg_RREADY_24(NLW_U0_Dbg_RREADY_24_UNCONNECTED), - .Dbg_RREADY_25(NLW_U0_Dbg_RREADY_25_UNCONNECTED), - .Dbg_RREADY_26(NLW_U0_Dbg_RREADY_26_UNCONNECTED), - .Dbg_RREADY_27(NLW_U0_Dbg_RREADY_27_UNCONNECTED), - .Dbg_RREADY_28(NLW_U0_Dbg_RREADY_28_UNCONNECTED), - .Dbg_RREADY_29(NLW_U0_Dbg_RREADY_29_UNCONNECTED), - .Dbg_RREADY_3(NLW_U0_Dbg_RREADY_3_UNCONNECTED), - .Dbg_RREADY_30(NLW_U0_Dbg_RREADY_30_UNCONNECTED), - .Dbg_RREADY_31(NLW_U0_Dbg_RREADY_31_UNCONNECTED), - .Dbg_RREADY_4(NLW_U0_Dbg_RREADY_4_UNCONNECTED), - .Dbg_RREADY_5(NLW_U0_Dbg_RREADY_5_UNCONNECTED), - .Dbg_RREADY_6(NLW_U0_Dbg_RREADY_6_UNCONNECTED), - .Dbg_RREADY_7(NLW_U0_Dbg_RREADY_7_UNCONNECTED), - .Dbg_RREADY_8(NLW_U0_Dbg_RREADY_8_UNCONNECTED), - .Dbg_RREADY_9(NLW_U0_Dbg_RREADY_9_UNCONNECTED), - .Dbg_RRESP_0({1'b0,1'b0}), - .Dbg_RRESP_1({1'b0,1'b0}), - .Dbg_RRESP_10({1'b0,1'b0}), - .Dbg_RRESP_11({1'b0,1'b0}), - .Dbg_RRESP_12({1'b0,1'b0}), - .Dbg_RRESP_13({1'b0,1'b0}), - .Dbg_RRESP_14({1'b0,1'b0}), - .Dbg_RRESP_15({1'b0,1'b0}), - .Dbg_RRESP_16({1'b0,1'b0}), - .Dbg_RRESP_17({1'b0,1'b0}), - .Dbg_RRESP_18({1'b0,1'b0}), - .Dbg_RRESP_19({1'b0,1'b0}), - .Dbg_RRESP_2({1'b0,1'b0}), - .Dbg_RRESP_20({1'b0,1'b0}), - .Dbg_RRESP_21({1'b0,1'b0}), - .Dbg_RRESP_22({1'b0,1'b0}), - .Dbg_RRESP_23({1'b0,1'b0}), - .Dbg_RRESP_24({1'b0,1'b0}), - .Dbg_RRESP_25({1'b0,1'b0}), - .Dbg_RRESP_26({1'b0,1'b0}), - .Dbg_RRESP_27({1'b0,1'b0}), - .Dbg_RRESP_28({1'b0,1'b0}), - .Dbg_RRESP_29({1'b0,1'b0}), - .Dbg_RRESP_3({1'b0,1'b0}), - .Dbg_RRESP_30({1'b0,1'b0}), - .Dbg_RRESP_31({1'b0,1'b0}), - .Dbg_RRESP_4({1'b0,1'b0}), - .Dbg_RRESP_5({1'b0,1'b0}), - .Dbg_RRESP_6({1'b0,1'b0}), - .Dbg_RRESP_7({1'b0,1'b0}), - .Dbg_RRESP_8({1'b0,1'b0}), - .Dbg_RRESP_9({1'b0,1'b0}), - .Dbg_RVALID_0(1'b0), - .Dbg_RVALID_1(1'b0), - .Dbg_RVALID_10(1'b0), - .Dbg_RVALID_11(1'b0), - .Dbg_RVALID_12(1'b0), - .Dbg_RVALID_13(1'b0), - .Dbg_RVALID_14(1'b0), - .Dbg_RVALID_15(1'b0), - .Dbg_RVALID_16(1'b0), - .Dbg_RVALID_17(1'b0), - .Dbg_RVALID_18(1'b0), - .Dbg_RVALID_19(1'b0), - .Dbg_RVALID_2(1'b0), - .Dbg_RVALID_20(1'b0), - .Dbg_RVALID_21(1'b0), - .Dbg_RVALID_22(1'b0), - .Dbg_RVALID_23(1'b0), - .Dbg_RVALID_24(1'b0), - .Dbg_RVALID_25(1'b0), - .Dbg_RVALID_26(1'b0), - .Dbg_RVALID_27(1'b0), - .Dbg_RVALID_28(1'b0), - .Dbg_RVALID_29(1'b0), - .Dbg_RVALID_3(1'b0), - .Dbg_RVALID_30(1'b0), - .Dbg_RVALID_31(1'b0), - .Dbg_RVALID_4(1'b0), - .Dbg_RVALID_5(1'b0), - .Dbg_RVALID_6(1'b0), - .Dbg_RVALID_7(1'b0), - .Dbg_RVALID_8(1'b0), - .Dbg_RVALID_9(1'b0), - .Dbg_Reg_En_0(Dbg_Reg_En_0), - .Dbg_Reg_En_1(NLW_U0_Dbg_Reg_En_1_UNCONNECTED[0:7]), - .Dbg_Reg_En_10(NLW_U0_Dbg_Reg_En_10_UNCONNECTED[0:7]), - .Dbg_Reg_En_11(NLW_U0_Dbg_Reg_En_11_UNCONNECTED[0:7]), - .Dbg_Reg_En_12(NLW_U0_Dbg_Reg_En_12_UNCONNECTED[0:7]), - .Dbg_Reg_En_13(NLW_U0_Dbg_Reg_En_13_UNCONNECTED[0:7]), - .Dbg_Reg_En_14(NLW_U0_Dbg_Reg_En_14_UNCONNECTED[0:7]), - .Dbg_Reg_En_15(NLW_U0_Dbg_Reg_En_15_UNCONNECTED[0:7]), - .Dbg_Reg_En_16(NLW_U0_Dbg_Reg_En_16_UNCONNECTED[0:7]), - .Dbg_Reg_En_17(NLW_U0_Dbg_Reg_En_17_UNCONNECTED[0:7]), - .Dbg_Reg_En_18(NLW_U0_Dbg_Reg_En_18_UNCONNECTED[0:7]), - .Dbg_Reg_En_19(NLW_U0_Dbg_Reg_En_19_UNCONNECTED[0:7]), - .Dbg_Reg_En_2(NLW_U0_Dbg_Reg_En_2_UNCONNECTED[0:7]), - .Dbg_Reg_En_20(NLW_U0_Dbg_Reg_En_20_UNCONNECTED[0:7]), - .Dbg_Reg_En_21(NLW_U0_Dbg_Reg_En_21_UNCONNECTED[0:7]), - .Dbg_Reg_En_22(NLW_U0_Dbg_Reg_En_22_UNCONNECTED[0:7]), - .Dbg_Reg_En_23(NLW_U0_Dbg_Reg_En_23_UNCONNECTED[0:7]), - .Dbg_Reg_En_24(NLW_U0_Dbg_Reg_En_24_UNCONNECTED[0:7]), - .Dbg_Reg_En_25(NLW_U0_Dbg_Reg_En_25_UNCONNECTED[0:7]), - .Dbg_Reg_En_26(NLW_U0_Dbg_Reg_En_26_UNCONNECTED[0:7]), - .Dbg_Reg_En_27(NLW_U0_Dbg_Reg_En_27_UNCONNECTED[0:7]), - .Dbg_Reg_En_28(NLW_U0_Dbg_Reg_En_28_UNCONNECTED[0:7]), - .Dbg_Reg_En_29(NLW_U0_Dbg_Reg_En_29_UNCONNECTED[0:7]), - .Dbg_Reg_En_3(NLW_U0_Dbg_Reg_En_3_UNCONNECTED[0:7]), - .Dbg_Reg_En_30(NLW_U0_Dbg_Reg_En_30_UNCONNECTED[0:7]), - .Dbg_Reg_En_31(NLW_U0_Dbg_Reg_En_31_UNCONNECTED[0:7]), - .Dbg_Reg_En_4(NLW_U0_Dbg_Reg_En_4_UNCONNECTED[0:7]), - .Dbg_Reg_En_5(NLW_U0_Dbg_Reg_En_5_UNCONNECTED[0:7]), - .Dbg_Reg_En_6(NLW_U0_Dbg_Reg_En_6_UNCONNECTED[0:7]), - .Dbg_Reg_En_7(NLW_U0_Dbg_Reg_En_7_UNCONNECTED[0:7]), - .Dbg_Reg_En_8(NLW_U0_Dbg_Reg_En_8_UNCONNECTED[0:7]), - .Dbg_Reg_En_9(NLW_U0_Dbg_Reg_En_9_UNCONNECTED[0:7]), - .Dbg_Rst_0(Dbg_Rst_0), - .Dbg_Rst_1(NLW_U0_Dbg_Rst_1_UNCONNECTED), - .Dbg_Rst_10(NLW_U0_Dbg_Rst_10_UNCONNECTED), - .Dbg_Rst_11(NLW_U0_Dbg_Rst_11_UNCONNECTED), - .Dbg_Rst_12(NLW_U0_Dbg_Rst_12_UNCONNECTED), - .Dbg_Rst_13(NLW_U0_Dbg_Rst_13_UNCONNECTED), - .Dbg_Rst_14(NLW_U0_Dbg_Rst_14_UNCONNECTED), - .Dbg_Rst_15(NLW_U0_Dbg_Rst_15_UNCONNECTED), - .Dbg_Rst_16(NLW_U0_Dbg_Rst_16_UNCONNECTED), - .Dbg_Rst_17(NLW_U0_Dbg_Rst_17_UNCONNECTED), - .Dbg_Rst_18(NLW_U0_Dbg_Rst_18_UNCONNECTED), - .Dbg_Rst_19(NLW_U0_Dbg_Rst_19_UNCONNECTED), - .Dbg_Rst_2(NLW_U0_Dbg_Rst_2_UNCONNECTED), - .Dbg_Rst_20(NLW_U0_Dbg_Rst_20_UNCONNECTED), - .Dbg_Rst_21(NLW_U0_Dbg_Rst_21_UNCONNECTED), - .Dbg_Rst_22(NLW_U0_Dbg_Rst_22_UNCONNECTED), - .Dbg_Rst_23(NLW_U0_Dbg_Rst_23_UNCONNECTED), - .Dbg_Rst_24(NLW_U0_Dbg_Rst_24_UNCONNECTED), - .Dbg_Rst_25(NLW_U0_Dbg_Rst_25_UNCONNECTED), - .Dbg_Rst_26(NLW_U0_Dbg_Rst_26_UNCONNECTED), - .Dbg_Rst_27(NLW_U0_Dbg_Rst_27_UNCONNECTED), - .Dbg_Rst_28(NLW_U0_Dbg_Rst_28_UNCONNECTED), - .Dbg_Rst_29(NLW_U0_Dbg_Rst_29_UNCONNECTED), - .Dbg_Rst_3(NLW_U0_Dbg_Rst_3_UNCONNECTED), - .Dbg_Rst_30(NLW_U0_Dbg_Rst_30_UNCONNECTED), - .Dbg_Rst_31(NLW_U0_Dbg_Rst_31_UNCONNECTED), - .Dbg_Rst_4(NLW_U0_Dbg_Rst_4_UNCONNECTED), - .Dbg_Rst_5(NLW_U0_Dbg_Rst_5_UNCONNECTED), - .Dbg_Rst_6(NLW_U0_Dbg_Rst_6_UNCONNECTED), - .Dbg_Rst_7(NLW_U0_Dbg_Rst_7_UNCONNECTED), - .Dbg_Rst_8(NLW_U0_Dbg_Rst_8_UNCONNECTED), - .Dbg_Rst_9(NLW_U0_Dbg_Rst_9_UNCONNECTED), - .Dbg_Shift_0(Dbg_Shift_0), - .Dbg_Shift_1(NLW_U0_Dbg_Shift_1_UNCONNECTED), - .Dbg_Shift_10(NLW_U0_Dbg_Shift_10_UNCONNECTED), - .Dbg_Shift_11(NLW_U0_Dbg_Shift_11_UNCONNECTED), - .Dbg_Shift_12(NLW_U0_Dbg_Shift_12_UNCONNECTED), - .Dbg_Shift_13(NLW_U0_Dbg_Shift_13_UNCONNECTED), - .Dbg_Shift_14(NLW_U0_Dbg_Shift_14_UNCONNECTED), - .Dbg_Shift_15(NLW_U0_Dbg_Shift_15_UNCONNECTED), - .Dbg_Shift_16(NLW_U0_Dbg_Shift_16_UNCONNECTED), - .Dbg_Shift_17(NLW_U0_Dbg_Shift_17_UNCONNECTED), - .Dbg_Shift_18(NLW_U0_Dbg_Shift_18_UNCONNECTED), - .Dbg_Shift_19(NLW_U0_Dbg_Shift_19_UNCONNECTED), - .Dbg_Shift_2(NLW_U0_Dbg_Shift_2_UNCONNECTED), - .Dbg_Shift_20(NLW_U0_Dbg_Shift_20_UNCONNECTED), - .Dbg_Shift_21(NLW_U0_Dbg_Shift_21_UNCONNECTED), - .Dbg_Shift_22(NLW_U0_Dbg_Shift_22_UNCONNECTED), - .Dbg_Shift_23(NLW_U0_Dbg_Shift_23_UNCONNECTED), - .Dbg_Shift_24(NLW_U0_Dbg_Shift_24_UNCONNECTED), - .Dbg_Shift_25(NLW_U0_Dbg_Shift_25_UNCONNECTED), - .Dbg_Shift_26(NLW_U0_Dbg_Shift_26_UNCONNECTED), - .Dbg_Shift_27(NLW_U0_Dbg_Shift_27_UNCONNECTED), - .Dbg_Shift_28(NLW_U0_Dbg_Shift_28_UNCONNECTED), - .Dbg_Shift_29(NLW_U0_Dbg_Shift_29_UNCONNECTED), - .Dbg_Shift_3(NLW_U0_Dbg_Shift_3_UNCONNECTED), - .Dbg_Shift_30(NLW_U0_Dbg_Shift_30_UNCONNECTED), - .Dbg_Shift_31(NLW_U0_Dbg_Shift_31_UNCONNECTED), - .Dbg_Shift_4(NLW_U0_Dbg_Shift_4_UNCONNECTED), - .Dbg_Shift_5(NLW_U0_Dbg_Shift_5_UNCONNECTED), - .Dbg_Shift_6(NLW_U0_Dbg_Shift_6_UNCONNECTED), - .Dbg_Shift_7(NLW_U0_Dbg_Shift_7_UNCONNECTED), - .Dbg_Shift_8(NLW_U0_Dbg_Shift_8_UNCONNECTED), - .Dbg_Shift_9(NLW_U0_Dbg_Shift_9_UNCONNECTED), - .Dbg_TDI_0(Dbg_TDI_0), - .Dbg_TDI_1(NLW_U0_Dbg_TDI_1_UNCONNECTED), - .Dbg_TDI_10(NLW_U0_Dbg_TDI_10_UNCONNECTED), - .Dbg_TDI_11(NLW_U0_Dbg_TDI_11_UNCONNECTED), - .Dbg_TDI_12(NLW_U0_Dbg_TDI_12_UNCONNECTED), - .Dbg_TDI_13(NLW_U0_Dbg_TDI_13_UNCONNECTED), - .Dbg_TDI_14(NLW_U0_Dbg_TDI_14_UNCONNECTED), - .Dbg_TDI_15(NLW_U0_Dbg_TDI_15_UNCONNECTED), - .Dbg_TDI_16(NLW_U0_Dbg_TDI_16_UNCONNECTED), - .Dbg_TDI_17(NLW_U0_Dbg_TDI_17_UNCONNECTED), - .Dbg_TDI_18(NLW_U0_Dbg_TDI_18_UNCONNECTED), - .Dbg_TDI_19(NLW_U0_Dbg_TDI_19_UNCONNECTED), - .Dbg_TDI_2(NLW_U0_Dbg_TDI_2_UNCONNECTED), - .Dbg_TDI_20(NLW_U0_Dbg_TDI_20_UNCONNECTED), - .Dbg_TDI_21(NLW_U0_Dbg_TDI_21_UNCONNECTED), - .Dbg_TDI_22(NLW_U0_Dbg_TDI_22_UNCONNECTED), - .Dbg_TDI_23(NLW_U0_Dbg_TDI_23_UNCONNECTED), - .Dbg_TDI_24(NLW_U0_Dbg_TDI_24_UNCONNECTED), - .Dbg_TDI_25(NLW_U0_Dbg_TDI_25_UNCONNECTED), - .Dbg_TDI_26(NLW_U0_Dbg_TDI_26_UNCONNECTED), - .Dbg_TDI_27(NLW_U0_Dbg_TDI_27_UNCONNECTED), - .Dbg_TDI_28(NLW_U0_Dbg_TDI_28_UNCONNECTED), - .Dbg_TDI_29(NLW_U0_Dbg_TDI_29_UNCONNECTED), - .Dbg_TDI_3(NLW_U0_Dbg_TDI_3_UNCONNECTED), - .Dbg_TDI_30(NLW_U0_Dbg_TDI_30_UNCONNECTED), - .Dbg_TDI_31(NLW_U0_Dbg_TDI_31_UNCONNECTED), - .Dbg_TDI_4(NLW_U0_Dbg_TDI_4_UNCONNECTED), - .Dbg_TDI_5(NLW_U0_Dbg_TDI_5_UNCONNECTED), - .Dbg_TDI_6(NLW_U0_Dbg_TDI_6_UNCONNECTED), - .Dbg_TDI_7(NLW_U0_Dbg_TDI_7_UNCONNECTED), - .Dbg_TDI_8(NLW_U0_Dbg_TDI_8_UNCONNECTED), - .Dbg_TDI_9(NLW_U0_Dbg_TDI_9_UNCONNECTED), - .Dbg_TDO_0(Dbg_TDO_0), - .Dbg_TDO_1(1'b0), - .Dbg_TDO_10(1'b0), - .Dbg_TDO_11(1'b0), - .Dbg_TDO_12(1'b0), - .Dbg_TDO_13(1'b0), - .Dbg_TDO_14(1'b0), - .Dbg_TDO_15(1'b0), - .Dbg_TDO_16(1'b0), - .Dbg_TDO_17(1'b0), - .Dbg_TDO_18(1'b0), - .Dbg_TDO_19(1'b0), - .Dbg_TDO_2(1'b0), - .Dbg_TDO_20(1'b0), - .Dbg_TDO_21(1'b0), - .Dbg_TDO_22(1'b0), - .Dbg_TDO_23(1'b0), - .Dbg_TDO_24(1'b0), - .Dbg_TDO_25(1'b0), - .Dbg_TDO_26(1'b0), - .Dbg_TDO_27(1'b0), - .Dbg_TDO_28(1'b0), - .Dbg_TDO_29(1'b0), - .Dbg_TDO_3(1'b0), - .Dbg_TDO_30(1'b0), - .Dbg_TDO_31(1'b0), - .Dbg_TDO_4(1'b0), - .Dbg_TDO_5(1'b0), - .Dbg_TDO_6(1'b0), - .Dbg_TDO_7(1'b0), - .Dbg_TDO_8(1'b0), - .Dbg_TDO_9(1'b0), - .Dbg_TrClk_0(NLW_U0_Dbg_TrClk_0_UNCONNECTED), - .Dbg_TrClk_1(NLW_U0_Dbg_TrClk_1_UNCONNECTED), - .Dbg_TrClk_10(NLW_U0_Dbg_TrClk_10_UNCONNECTED), - .Dbg_TrClk_11(NLW_U0_Dbg_TrClk_11_UNCONNECTED), - .Dbg_TrClk_12(NLW_U0_Dbg_TrClk_12_UNCONNECTED), - .Dbg_TrClk_13(NLW_U0_Dbg_TrClk_13_UNCONNECTED), - .Dbg_TrClk_14(NLW_U0_Dbg_TrClk_14_UNCONNECTED), - .Dbg_TrClk_15(NLW_U0_Dbg_TrClk_15_UNCONNECTED), - .Dbg_TrClk_16(NLW_U0_Dbg_TrClk_16_UNCONNECTED), - .Dbg_TrClk_17(NLW_U0_Dbg_TrClk_17_UNCONNECTED), - .Dbg_TrClk_18(NLW_U0_Dbg_TrClk_18_UNCONNECTED), - .Dbg_TrClk_19(NLW_U0_Dbg_TrClk_19_UNCONNECTED), - .Dbg_TrClk_2(NLW_U0_Dbg_TrClk_2_UNCONNECTED), - .Dbg_TrClk_20(NLW_U0_Dbg_TrClk_20_UNCONNECTED), - .Dbg_TrClk_21(NLW_U0_Dbg_TrClk_21_UNCONNECTED), - .Dbg_TrClk_22(NLW_U0_Dbg_TrClk_22_UNCONNECTED), - .Dbg_TrClk_23(NLW_U0_Dbg_TrClk_23_UNCONNECTED), - .Dbg_TrClk_24(NLW_U0_Dbg_TrClk_24_UNCONNECTED), - .Dbg_TrClk_25(NLW_U0_Dbg_TrClk_25_UNCONNECTED), - .Dbg_TrClk_26(NLW_U0_Dbg_TrClk_26_UNCONNECTED), - .Dbg_TrClk_27(NLW_U0_Dbg_TrClk_27_UNCONNECTED), - .Dbg_TrClk_28(NLW_U0_Dbg_TrClk_28_UNCONNECTED), - .Dbg_TrClk_29(NLW_U0_Dbg_TrClk_29_UNCONNECTED), - .Dbg_TrClk_3(NLW_U0_Dbg_TrClk_3_UNCONNECTED), - .Dbg_TrClk_30(NLW_U0_Dbg_TrClk_30_UNCONNECTED), - .Dbg_TrClk_31(NLW_U0_Dbg_TrClk_31_UNCONNECTED), - .Dbg_TrClk_4(NLW_U0_Dbg_TrClk_4_UNCONNECTED), - .Dbg_TrClk_5(NLW_U0_Dbg_TrClk_5_UNCONNECTED), - .Dbg_TrClk_6(NLW_U0_Dbg_TrClk_6_UNCONNECTED), - .Dbg_TrClk_7(NLW_U0_Dbg_TrClk_7_UNCONNECTED), - .Dbg_TrClk_8(NLW_U0_Dbg_TrClk_8_UNCONNECTED), - .Dbg_TrClk_9(NLW_U0_Dbg_TrClk_9_UNCONNECTED), - .Dbg_TrData_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrData_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_TrReady_0(NLW_U0_Dbg_TrReady_0_UNCONNECTED), - .Dbg_TrReady_1(NLW_U0_Dbg_TrReady_1_UNCONNECTED), - .Dbg_TrReady_10(NLW_U0_Dbg_TrReady_10_UNCONNECTED), - .Dbg_TrReady_11(NLW_U0_Dbg_TrReady_11_UNCONNECTED), - .Dbg_TrReady_12(NLW_U0_Dbg_TrReady_12_UNCONNECTED), - .Dbg_TrReady_13(NLW_U0_Dbg_TrReady_13_UNCONNECTED), - .Dbg_TrReady_14(NLW_U0_Dbg_TrReady_14_UNCONNECTED), - .Dbg_TrReady_15(NLW_U0_Dbg_TrReady_15_UNCONNECTED), - .Dbg_TrReady_16(NLW_U0_Dbg_TrReady_16_UNCONNECTED), - .Dbg_TrReady_17(NLW_U0_Dbg_TrReady_17_UNCONNECTED), - .Dbg_TrReady_18(NLW_U0_Dbg_TrReady_18_UNCONNECTED), - .Dbg_TrReady_19(NLW_U0_Dbg_TrReady_19_UNCONNECTED), - .Dbg_TrReady_2(NLW_U0_Dbg_TrReady_2_UNCONNECTED), - .Dbg_TrReady_20(NLW_U0_Dbg_TrReady_20_UNCONNECTED), - .Dbg_TrReady_21(NLW_U0_Dbg_TrReady_21_UNCONNECTED), - .Dbg_TrReady_22(NLW_U0_Dbg_TrReady_22_UNCONNECTED), - .Dbg_TrReady_23(NLW_U0_Dbg_TrReady_23_UNCONNECTED), - .Dbg_TrReady_24(NLW_U0_Dbg_TrReady_24_UNCONNECTED), - .Dbg_TrReady_25(NLW_U0_Dbg_TrReady_25_UNCONNECTED), - .Dbg_TrReady_26(NLW_U0_Dbg_TrReady_26_UNCONNECTED), - .Dbg_TrReady_27(NLW_U0_Dbg_TrReady_27_UNCONNECTED), - .Dbg_TrReady_28(NLW_U0_Dbg_TrReady_28_UNCONNECTED), - .Dbg_TrReady_29(NLW_U0_Dbg_TrReady_29_UNCONNECTED), - .Dbg_TrReady_3(NLW_U0_Dbg_TrReady_3_UNCONNECTED), - .Dbg_TrReady_30(NLW_U0_Dbg_TrReady_30_UNCONNECTED), - .Dbg_TrReady_31(NLW_U0_Dbg_TrReady_31_UNCONNECTED), - .Dbg_TrReady_4(NLW_U0_Dbg_TrReady_4_UNCONNECTED), - .Dbg_TrReady_5(NLW_U0_Dbg_TrReady_5_UNCONNECTED), - .Dbg_TrReady_6(NLW_U0_Dbg_TrReady_6_UNCONNECTED), - .Dbg_TrReady_7(NLW_U0_Dbg_TrReady_7_UNCONNECTED), - .Dbg_TrReady_8(NLW_U0_Dbg_TrReady_8_UNCONNECTED), - .Dbg_TrReady_9(NLW_U0_Dbg_TrReady_9_UNCONNECTED), - .Dbg_TrValid_0(1'b0), - .Dbg_TrValid_1(1'b0), - .Dbg_TrValid_10(1'b0), - .Dbg_TrValid_11(1'b0), - .Dbg_TrValid_12(1'b0), - .Dbg_TrValid_13(1'b0), - .Dbg_TrValid_14(1'b0), - .Dbg_TrValid_15(1'b0), - .Dbg_TrValid_16(1'b0), - .Dbg_TrValid_17(1'b0), - .Dbg_TrValid_18(1'b0), - .Dbg_TrValid_19(1'b0), - .Dbg_TrValid_2(1'b0), - .Dbg_TrValid_20(1'b0), - .Dbg_TrValid_21(1'b0), - .Dbg_TrValid_22(1'b0), - .Dbg_TrValid_23(1'b0), - .Dbg_TrValid_24(1'b0), - .Dbg_TrValid_25(1'b0), - .Dbg_TrValid_26(1'b0), - .Dbg_TrValid_27(1'b0), - .Dbg_TrValid_28(1'b0), - .Dbg_TrValid_29(1'b0), - .Dbg_TrValid_3(1'b0), - .Dbg_TrValid_30(1'b0), - .Dbg_TrValid_31(1'b0), - .Dbg_TrValid_4(1'b0), - .Dbg_TrValid_5(1'b0), - .Dbg_TrValid_6(1'b0), - .Dbg_TrValid_7(1'b0), - .Dbg_TrValid_8(1'b0), - .Dbg_TrValid_9(1'b0), - .Dbg_Trig_Ack_In_0(NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_1(NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_10(NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_11(NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_12(NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_13(NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_14(NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_15(NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_16(NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_17(NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_18(NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_19(NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_2(NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_20(NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_21(NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_22(NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_23(NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_24(NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_25(NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_26(NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_27(NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_28(NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_29(NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_3(NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_30(NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_31(NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_4(NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_5(NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_6(NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_7(NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_8(NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_In_9(NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED[0:7]), - .Dbg_Trig_Ack_Out_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Ack_Out_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_In_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .Dbg_Trig_Out_0(NLW_U0_Dbg_Trig_Out_0_UNCONNECTED[0:7]), - .Dbg_Trig_Out_1(NLW_U0_Dbg_Trig_Out_1_UNCONNECTED[0:7]), - .Dbg_Trig_Out_10(NLW_U0_Dbg_Trig_Out_10_UNCONNECTED[0:7]), - .Dbg_Trig_Out_11(NLW_U0_Dbg_Trig_Out_11_UNCONNECTED[0:7]), - .Dbg_Trig_Out_12(NLW_U0_Dbg_Trig_Out_12_UNCONNECTED[0:7]), - .Dbg_Trig_Out_13(NLW_U0_Dbg_Trig_Out_13_UNCONNECTED[0:7]), - .Dbg_Trig_Out_14(NLW_U0_Dbg_Trig_Out_14_UNCONNECTED[0:7]), - .Dbg_Trig_Out_15(NLW_U0_Dbg_Trig_Out_15_UNCONNECTED[0:7]), - .Dbg_Trig_Out_16(NLW_U0_Dbg_Trig_Out_16_UNCONNECTED[0:7]), - .Dbg_Trig_Out_17(NLW_U0_Dbg_Trig_Out_17_UNCONNECTED[0:7]), - .Dbg_Trig_Out_18(NLW_U0_Dbg_Trig_Out_18_UNCONNECTED[0:7]), - .Dbg_Trig_Out_19(NLW_U0_Dbg_Trig_Out_19_UNCONNECTED[0:7]), - .Dbg_Trig_Out_2(NLW_U0_Dbg_Trig_Out_2_UNCONNECTED[0:7]), - .Dbg_Trig_Out_20(NLW_U0_Dbg_Trig_Out_20_UNCONNECTED[0:7]), - .Dbg_Trig_Out_21(NLW_U0_Dbg_Trig_Out_21_UNCONNECTED[0:7]), - .Dbg_Trig_Out_22(NLW_U0_Dbg_Trig_Out_22_UNCONNECTED[0:7]), - .Dbg_Trig_Out_23(NLW_U0_Dbg_Trig_Out_23_UNCONNECTED[0:7]), - .Dbg_Trig_Out_24(NLW_U0_Dbg_Trig_Out_24_UNCONNECTED[0:7]), - .Dbg_Trig_Out_25(NLW_U0_Dbg_Trig_Out_25_UNCONNECTED[0:7]), - .Dbg_Trig_Out_26(NLW_U0_Dbg_Trig_Out_26_UNCONNECTED[0:7]), - .Dbg_Trig_Out_27(NLW_U0_Dbg_Trig_Out_27_UNCONNECTED[0:7]), - .Dbg_Trig_Out_28(NLW_U0_Dbg_Trig_Out_28_UNCONNECTED[0:7]), - .Dbg_Trig_Out_29(NLW_U0_Dbg_Trig_Out_29_UNCONNECTED[0:7]), - .Dbg_Trig_Out_3(NLW_U0_Dbg_Trig_Out_3_UNCONNECTED[0:7]), - .Dbg_Trig_Out_30(NLW_U0_Dbg_Trig_Out_30_UNCONNECTED[0:7]), - .Dbg_Trig_Out_31(NLW_U0_Dbg_Trig_Out_31_UNCONNECTED[0:7]), - .Dbg_Trig_Out_4(NLW_U0_Dbg_Trig_Out_4_UNCONNECTED[0:7]), - .Dbg_Trig_Out_5(NLW_U0_Dbg_Trig_Out_5_UNCONNECTED[0:7]), - .Dbg_Trig_Out_6(NLW_U0_Dbg_Trig_Out_6_UNCONNECTED[0:7]), - .Dbg_Trig_Out_7(NLW_U0_Dbg_Trig_Out_7_UNCONNECTED[0:7]), - .Dbg_Trig_Out_8(NLW_U0_Dbg_Trig_Out_8_UNCONNECTED[0:7]), - .Dbg_Trig_Out_9(NLW_U0_Dbg_Trig_Out_9_UNCONNECTED[0:7]), - .Dbg_Update_0(Dbg_Update_0), - .Dbg_Update_1(NLW_U0_Dbg_Update_1_UNCONNECTED), - .Dbg_Update_10(NLW_U0_Dbg_Update_10_UNCONNECTED), - .Dbg_Update_11(NLW_U0_Dbg_Update_11_UNCONNECTED), - .Dbg_Update_12(NLW_U0_Dbg_Update_12_UNCONNECTED), - .Dbg_Update_13(NLW_U0_Dbg_Update_13_UNCONNECTED), - .Dbg_Update_14(NLW_U0_Dbg_Update_14_UNCONNECTED), - .Dbg_Update_15(NLW_U0_Dbg_Update_15_UNCONNECTED), - .Dbg_Update_16(NLW_U0_Dbg_Update_16_UNCONNECTED), - .Dbg_Update_17(NLW_U0_Dbg_Update_17_UNCONNECTED), - .Dbg_Update_18(NLW_U0_Dbg_Update_18_UNCONNECTED), - .Dbg_Update_19(NLW_U0_Dbg_Update_19_UNCONNECTED), - .Dbg_Update_2(NLW_U0_Dbg_Update_2_UNCONNECTED), - .Dbg_Update_20(NLW_U0_Dbg_Update_20_UNCONNECTED), - .Dbg_Update_21(NLW_U0_Dbg_Update_21_UNCONNECTED), - .Dbg_Update_22(NLW_U0_Dbg_Update_22_UNCONNECTED), - .Dbg_Update_23(NLW_U0_Dbg_Update_23_UNCONNECTED), - .Dbg_Update_24(NLW_U0_Dbg_Update_24_UNCONNECTED), - .Dbg_Update_25(NLW_U0_Dbg_Update_25_UNCONNECTED), - .Dbg_Update_26(NLW_U0_Dbg_Update_26_UNCONNECTED), - .Dbg_Update_27(NLW_U0_Dbg_Update_27_UNCONNECTED), - .Dbg_Update_28(NLW_U0_Dbg_Update_28_UNCONNECTED), - .Dbg_Update_29(NLW_U0_Dbg_Update_29_UNCONNECTED), - .Dbg_Update_3(NLW_U0_Dbg_Update_3_UNCONNECTED), - .Dbg_Update_30(NLW_U0_Dbg_Update_30_UNCONNECTED), - .Dbg_Update_31(NLW_U0_Dbg_Update_31_UNCONNECTED), - .Dbg_Update_4(NLW_U0_Dbg_Update_4_UNCONNECTED), - .Dbg_Update_5(NLW_U0_Dbg_Update_5_UNCONNECTED), - .Dbg_Update_6(NLW_U0_Dbg_Update_6_UNCONNECTED), - .Dbg_Update_7(NLW_U0_Dbg_Update_7_UNCONNECTED), - .Dbg_Update_8(NLW_U0_Dbg_Update_8_UNCONNECTED), - .Dbg_Update_9(NLW_U0_Dbg_Update_9_UNCONNECTED), - .Dbg_WDATA_0(NLW_U0_Dbg_WDATA_0_UNCONNECTED[31:0]), - .Dbg_WDATA_1(NLW_U0_Dbg_WDATA_1_UNCONNECTED[31:0]), - .Dbg_WDATA_10(NLW_U0_Dbg_WDATA_10_UNCONNECTED[31:0]), - .Dbg_WDATA_11(NLW_U0_Dbg_WDATA_11_UNCONNECTED[31:0]), - .Dbg_WDATA_12(NLW_U0_Dbg_WDATA_12_UNCONNECTED[31:0]), - .Dbg_WDATA_13(NLW_U0_Dbg_WDATA_13_UNCONNECTED[31:0]), - .Dbg_WDATA_14(NLW_U0_Dbg_WDATA_14_UNCONNECTED[31:0]), - .Dbg_WDATA_15(NLW_U0_Dbg_WDATA_15_UNCONNECTED[31:0]), - .Dbg_WDATA_16(NLW_U0_Dbg_WDATA_16_UNCONNECTED[31:0]), - .Dbg_WDATA_17(NLW_U0_Dbg_WDATA_17_UNCONNECTED[31:0]), - .Dbg_WDATA_18(NLW_U0_Dbg_WDATA_18_UNCONNECTED[31:0]), - .Dbg_WDATA_19(NLW_U0_Dbg_WDATA_19_UNCONNECTED[31:0]), - .Dbg_WDATA_2(NLW_U0_Dbg_WDATA_2_UNCONNECTED[31:0]), - .Dbg_WDATA_20(NLW_U0_Dbg_WDATA_20_UNCONNECTED[31:0]), - .Dbg_WDATA_21(NLW_U0_Dbg_WDATA_21_UNCONNECTED[31:0]), - .Dbg_WDATA_22(NLW_U0_Dbg_WDATA_22_UNCONNECTED[31:0]), - .Dbg_WDATA_23(NLW_U0_Dbg_WDATA_23_UNCONNECTED[31:0]), - .Dbg_WDATA_24(NLW_U0_Dbg_WDATA_24_UNCONNECTED[31:0]), - .Dbg_WDATA_25(NLW_U0_Dbg_WDATA_25_UNCONNECTED[31:0]), - .Dbg_WDATA_26(NLW_U0_Dbg_WDATA_26_UNCONNECTED[31:0]), - .Dbg_WDATA_27(NLW_U0_Dbg_WDATA_27_UNCONNECTED[31:0]), - .Dbg_WDATA_28(NLW_U0_Dbg_WDATA_28_UNCONNECTED[31:0]), - .Dbg_WDATA_29(NLW_U0_Dbg_WDATA_29_UNCONNECTED[31:0]), - .Dbg_WDATA_3(NLW_U0_Dbg_WDATA_3_UNCONNECTED[31:0]), - .Dbg_WDATA_30(NLW_U0_Dbg_WDATA_30_UNCONNECTED[31:0]), - .Dbg_WDATA_31(NLW_U0_Dbg_WDATA_31_UNCONNECTED[31:0]), - .Dbg_WDATA_4(NLW_U0_Dbg_WDATA_4_UNCONNECTED[31:0]), - .Dbg_WDATA_5(NLW_U0_Dbg_WDATA_5_UNCONNECTED[31:0]), - .Dbg_WDATA_6(NLW_U0_Dbg_WDATA_6_UNCONNECTED[31:0]), - .Dbg_WDATA_7(NLW_U0_Dbg_WDATA_7_UNCONNECTED[31:0]), - .Dbg_WDATA_8(NLW_U0_Dbg_WDATA_8_UNCONNECTED[31:0]), - .Dbg_WDATA_9(NLW_U0_Dbg_WDATA_9_UNCONNECTED[31:0]), - .Dbg_WREADY_0(1'b0), - .Dbg_WREADY_1(1'b0), - .Dbg_WREADY_10(1'b0), - .Dbg_WREADY_11(1'b0), - .Dbg_WREADY_12(1'b0), - .Dbg_WREADY_13(1'b0), - .Dbg_WREADY_14(1'b0), - .Dbg_WREADY_15(1'b0), - .Dbg_WREADY_16(1'b0), - .Dbg_WREADY_17(1'b0), - .Dbg_WREADY_18(1'b0), - .Dbg_WREADY_19(1'b0), - .Dbg_WREADY_2(1'b0), - .Dbg_WREADY_20(1'b0), - .Dbg_WREADY_21(1'b0), - .Dbg_WREADY_22(1'b0), - .Dbg_WREADY_23(1'b0), - .Dbg_WREADY_24(1'b0), - .Dbg_WREADY_25(1'b0), - .Dbg_WREADY_26(1'b0), - .Dbg_WREADY_27(1'b0), - .Dbg_WREADY_28(1'b0), - .Dbg_WREADY_29(1'b0), - .Dbg_WREADY_3(1'b0), - .Dbg_WREADY_30(1'b0), - .Dbg_WREADY_31(1'b0), - .Dbg_WREADY_4(1'b0), - .Dbg_WREADY_5(1'b0), - .Dbg_WREADY_6(1'b0), - .Dbg_WREADY_7(1'b0), - .Dbg_WREADY_8(1'b0), - .Dbg_WREADY_9(1'b0), - .Dbg_WVALID_0(NLW_U0_Dbg_WVALID_0_UNCONNECTED), - .Dbg_WVALID_1(NLW_U0_Dbg_WVALID_1_UNCONNECTED), - .Dbg_WVALID_10(NLW_U0_Dbg_WVALID_10_UNCONNECTED), - .Dbg_WVALID_11(NLW_U0_Dbg_WVALID_11_UNCONNECTED), - .Dbg_WVALID_12(NLW_U0_Dbg_WVALID_12_UNCONNECTED), - .Dbg_WVALID_13(NLW_U0_Dbg_WVALID_13_UNCONNECTED), - .Dbg_WVALID_14(NLW_U0_Dbg_WVALID_14_UNCONNECTED), - .Dbg_WVALID_15(NLW_U0_Dbg_WVALID_15_UNCONNECTED), - .Dbg_WVALID_16(NLW_U0_Dbg_WVALID_16_UNCONNECTED), - .Dbg_WVALID_17(NLW_U0_Dbg_WVALID_17_UNCONNECTED), - .Dbg_WVALID_18(NLW_U0_Dbg_WVALID_18_UNCONNECTED), - .Dbg_WVALID_19(NLW_U0_Dbg_WVALID_19_UNCONNECTED), - .Dbg_WVALID_2(NLW_U0_Dbg_WVALID_2_UNCONNECTED), - .Dbg_WVALID_20(NLW_U0_Dbg_WVALID_20_UNCONNECTED), - .Dbg_WVALID_21(NLW_U0_Dbg_WVALID_21_UNCONNECTED), - .Dbg_WVALID_22(NLW_U0_Dbg_WVALID_22_UNCONNECTED), - .Dbg_WVALID_23(NLW_U0_Dbg_WVALID_23_UNCONNECTED), - .Dbg_WVALID_24(NLW_U0_Dbg_WVALID_24_UNCONNECTED), - .Dbg_WVALID_25(NLW_U0_Dbg_WVALID_25_UNCONNECTED), - .Dbg_WVALID_26(NLW_U0_Dbg_WVALID_26_UNCONNECTED), - .Dbg_WVALID_27(NLW_U0_Dbg_WVALID_27_UNCONNECTED), - .Dbg_WVALID_28(NLW_U0_Dbg_WVALID_28_UNCONNECTED), - .Dbg_WVALID_29(NLW_U0_Dbg_WVALID_29_UNCONNECTED), - .Dbg_WVALID_3(NLW_U0_Dbg_WVALID_3_UNCONNECTED), - .Dbg_WVALID_30(NLW_U0_Dbg_WVALID_30_UNCONNECTED), - .Dbg_WVALID_31(NLW_U0_Dbg_WVALID_31_UNCONNECTED), - .Dbg_WVALID_4(NLW_U0_Dbg_WVALID_4_UNCONNECTED), - .Dbg_WVALID_5(NLW_U0_Dbg_WVALID_5_UNCONNECTED), - .Dbg_WVALID_6(NLW_U0_Dbg_WVALID_6_UNCONNECTED), - .Dbg_WVALID_7(NLW_U0_Dbg_WVALID_7_UNCONNECTED), - .Dbg_WVALID_8(NLW_U0_Dbg_WVALID_8_UNCONNECTED), - .Dbg_WVALID_9(NLW_U0_Dbg_WVALID_9_UNCONNECTED), - .Debug_SYS_Rst(Debug_SYS_Rst), - .Ext_BRK(NLW_U0_Ext_BRK_UNCONNECTED), - .Ext_JTAG_CAPTURE(NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED), - .Ext_JTAG_DRCK(NLW_U0_Ext_JTAG_DRCK_UNCONNECTED), - .Ext_JTAG_RESET(NLW_U0_Ext_JTAG_RESET_UNCONNECTED), - .Ext_JTAG_SEL(NLW_U0_Ext_JTAG_SEL_UNCONNECTED), - .Ext_JTAG_SHIFT(NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED), - .Ext_JTAG_TDI(NLW_U0_Ext_JTAG_TDI_UNCONNECTED), - .Ext_JTAG_TDO(1'b0), - .Ext_JTAG_UPDATE(NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED), - .Ext_NM_BRK(NLW_U0_Ext_NM_BRK_UNCONNECTED), - .Interrupt(NLW_U0_Interrupt_UNCONNECTED), - .LMB_Addr_Strobe_0(NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED), - .LMB_Addr_Strobe_1(NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED), - .LMB_Addr_Strobe_10(NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED), - .LMB_Addr_Strobe_11(NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED), - .LMB_Addr_Strobe_12(NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED), - .LMB_Addr_Strobe_13(NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED), - .LMB_Addr_Strobe_14(NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED), - .LMB_Addr_Strobe_15(NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED), - .LMB_Addr_Strobe_16(NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED), - .LMB_Addr_Strobe_17(NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED), - .LMB_Addr_Strobe_18(NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED), - .LMB_Addr_Strobe_19(NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED), - .LMB_Addr_Strobe_2(NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED), - .LMB_Addr_Strobe_20(NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED), - .LMB_Addr_Strobe_21(NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED), - .LMB_Addr_Strobe_22(NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED), - .LMB_Addr_Strobe_23(NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED), - .LMB_Addr_Strobe_24(NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED), - .LMB_Addr_Strobe_25(NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED), - .LMB_Addr_Strobe_26(NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED), - .LMB_Addr_Strobe_27(NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED), - .LMB_Addr_Strobe_28(NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED), - .LMB_Addr_Strobe_29(NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED), - .LMB_Addr_Strobe_3(NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED), - .LMB_Addr_Strobe_30(NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED), - .LMB_Addr_Strobe_31(NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED), - .LMB_Addr_Strobe_4(NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED), - .LMB_Addr_Strobe_5(NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED), - .LMB_Addr_Strobe_6(NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED), - .LMB_Addr_Strobe_7(NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED), - .LMB_Addr_Strobe_8(NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED), - .LMB_Addr_Strobe_9(NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED), - .LMB_Byte_Enable_0(NLW_U0_LMB_Byte_Enable_0_UNCONNECTED[0:3]), - .LMB_Byte_Enable_1(NLW_U0_LMB_Byte_Enable_1_UNCONNECTED[0:3]), - .LMB_Byte_Enable_10(NLW_U0_LMB_Byte_Enable_10_UNCONNECTED[0:3]), - .LMB_Byte_Enable_11(NLW_U0_LMB_Byte_Enable_11_UNCONNECTED[0:3]), - .LMB_Byte_Enable_12(NLW_U0_LMB_Byte_Enable_12_UNCONNECTED[0:3]), - .LMB_Byte_Enable_13(NLW_U0_LMB_Byte_Enable_13_UNCONNECTED[0:3]), - .LMB_Byte_Enable_14(NLW_U0_LMB_Byte_Enable_14_UNCONNECTED[0:3]), - .LMB_Byte_Enable_15(NLW_U0_LMB_Byte_Enable_15_UNCONNECTED[0:3]), - .LMB_Byte_Enable_16(NLW_U0_LMB_Byte_Enable_16_UNCONNECTED[0:3]), - .LMB_Byte_Enable_17(NLW_U0_LMB_Byte_Enable_17_UNCONNECTED[0:3]), - .LMB_Byte_Enable_18(NLW_U0_LMB_Byte_Enable_18_UNCONNECTED[0:3]), - .LMB_Byte_Enable_19(NLW_U0_LMB_Byte_Enable_19_UNCONNECTED[0:3]), - .LMB_Byte_Enable_2(NLW_U0_LMB_Byte_Enable_2_UNCONNECTED[0:3]), - .LMB_Byte_Enable_20(NLW_U0_LMB_Byte_Enable_20_UNCONNECTED[0:3]), - .LMB_Byte_Enable_21(NLW_U0_LMB_Byte_Enable_21_UNCONNECTED[0:3]), - .LMB_Byte_Enable_22(NLW_U0_LMB_Byte_Enable_22_UNCONNECTED[0:3]), - .LMB_Byte_Enable_23(NLW_U0_LMB_Byte_Enable_23_UNCONNECTED[0:3]), - .LMB_Byte_Enable_24(NLW_U0_LMB_Byte_Enable_24_UNCONNECTED[0:3]), - .LMB_Byte_Enable_25(NLW_U0_LMB_Byte_Enable_25_UNCONNECTED[0:3]), - .LMB_Byte_Enable_26(NLW_U0_LMB_Byte_Enable_26_UNCONNECTED[0:3]), - .LMB_Byte_Enable_27(NLW_U0_LMB_Byte_Enable_27_UNCONNECTED[0:3]), - .LMB_Byte_Enable_28(NLW_U0_LMB_Byte_Enable_28_UNCONNECTED[0:3]), - .LMB_Byte_Enable_29(NLW_U0_LMB_Byte_Enable_29_UNCONNECTED[0:3]), - .LMB_Byte_Enable_3(NLW_U0_LMB_Byte_Enable_3_UNCONNECTED[0:3]), - .LMB_Byte_Enable_30(NLW_U0_LMB_Byte_Enable_30_UNCONNECTED[0:3]), - .LMB_Byte_Enable_31(NLW_U0_LMB_Byte_Enable_31_UNCONNECTED[0:3]), - .LMB_Byte_Enable_4(NLW_U0_LMB_Byte_Enable_4_UNCONNECTED[0:3]), - .LMB_Byte_Enable_5(NLW_U0_LMB_Byte_Enable_5_UNCONNECTED[0:3]), - .LMB_Byte_Enable_6(NLW_U0_LMB_Byte_Enable_6_UNCONNECTED[0:3]), - .LMB_Byte_Enable_7(NLW_U0_LMB_Byte_Enable_7_UNCONNECTED[0:3]), - .LMB_Byte_Enable_8(NLW_U0_LMB_Byte_Enable_8_UNCONNECTED[0:3]), - .LMB_Byte_Enable_9(NLW_U0_LMB_Byte_Enable_9_UNCONNECTED[0:3]), - .LMB_CE_0(1'b0), - .LMB_CE_1(1'b0), - .LMB_CE_10(1'b0), - .LMB_CE_11(1'b0), - .LMB_CE_12(1'b0), - .LMB_CE_13(1'b0), - .LMB_CE_14(1'b0), - .LMB_CE_15(1'b0), - .LMB_CE_16(1'b0), - .LMB_CE_17(1'b0), - .LMB_CE_18(1'b0), - .LMB_CE_19(1'b0), - .LMB_CE_2(1'b0), - .LMB_CE_20(1'b0), - .LMB_CE_21(1'b0), - .LMB_CE_22(1'b0), - .LMB_CE_23(1'b0), - .LMB_CE_24(1'b0), - .LMB_CE_25(1'b0), - .LMB_CE_26(1'b0), - .LMB_CE_27(1'b0), - .LMB_CE_28(1'b0), - .LMB_CE_29(1'b0), - .LMB_CE_3(1'b0), - .LMB_CE_30(1'b0), - .LMB_CE_31(1'b0), - .LMB_CE_4(1'b0), - .LMB_CE_5(1'b0), - .LMB_CE_6(1'b0), - .LMB_CE_7(1'b0), - .LMB_CE_8(1'b0), - .LMB_CE_9(1'b0), - .LMB_Data_Addr_0(NLW_U0_LMB_Data_Addr_0_UNCONNECTED[0:31]), - .LMB_Data_Addr_1(NLW_U0_LMB_Data_Addr_1_UNCONNECTED[0:31]), - .LMB_Data_Addr_10(NLW_U0_LMB_Data_Addr_10_UNCONNECTED[0:31]), - .LMB_Data_Addr_11(NLW_U0_LMB_Data_Addr_11_UNCONNECTED[0:31]), - .LMB_Data_Addr_12(NLW_U0_LMB_Data_Addr_12_UNCONNECTED[0:31]), - .LMB_Data_Addr_13(NLW_U0_LMB_Data_Addr_13_UNCONNECTED[0:31]), - .LMB_Data_Addr_14(NLW_U0_LMB_Data_Addr_14_UNCONNECTED[0:31]), - .LMB_Data_Addr_15(NLW_U0_LMB_Data_Addr_15_UNCONNECTED[0:31]), - .LMB_Data_Addr_16(NLW_U0_LMB_Data_Addr_16_UNCONNECTED[0:31]), - .LMB_Data_Addr_17(NLW_U0_LMB_Data_Addr_17_UNCONNECTED[0:31]), - .LMB_Data_Addr_18(NLW_U0_LMB_Data_Addr_18_UNCONNECTED[0:31]), - .LMB_Data_Addr_19(NLW_U0_LMB_Data_Addr_19_UNCONNECTED[0:31]), - .LMB_Data_Addr_2(NLW_U0_LMB_Data_Addr_2_UNCONNECTED[0:31]), - .LMB_Data_Addr_20(NLW_U0_LMB_Data_Addr_20_UNCONNECTED[0:31]), - .LMB_Data_Addr_21(NLW_U0_LMB_Data_Addr_21_UNCONNECTED[0:31]), - .LMB_Data_Addr_22(NLW_U0_LMB_Data_Addr_22_UNCONNECTED[0:31]), - .LMB_Data_Addr_23(NLW_U0_LMB_Data_Addr_23_UNCONNECTED[0:31]), - .LMB_Data_Addr_24(NLW_U0_LMB_Data_Addr_24_UNCONNECTED[0:31]), - .LMB_Data_Addr_25(NLW_U0_LMB_Data_Addr_25_UNCONNECTED[0:31]), - .LMB_Data_Addr_26(NLW_U0_LMB_Data_Addr_26_UNCONNECTED[0:31]), - .LMB_Data_Addr_27(NLW_U0_LMB_Data_Addr_27_UNCONNECTED[0:31]), - .LMB_Data_Addr_28(NLW_U0_LMB_Data_Addr_28_UNCONNECTED[0:31]), - .LMB_Data_Addr_29(NLW_U0_LMB_Data_Addr_29_UNCONNECTED[0:31]), - .LMB_Data_Addr_3(NLW_U0_LMB_Data_Addr_3_UNCONNECTED[0:31]), - .LMB_Data_Addr_30(NLW_U0_LMB_Data_Addr_30_UNCONNECTED[0:31]), - .LMB_Data_Addr_31(NLW_U0_LMB_Data_Addr_31_UNCONNECTED[0:31]), - .LMB_Data_Addr_4(NLW_U0_LMB_Data_Addr_4_UNCONNECTED[0:31]), - .LMB_Data_Addr_5(NLW_U0_LMB_Data_Addr_5_UNCONNECTED[0:31]), - .LMB_Data_Addr_6(NLW_U0_LMB_Data_Addr_6_UNCONNECTED[0:31]), - .LMB_Data_Addr_7(NLW_U0_LMB_Data_Addr_7_UNCONNECTED[0:31]), - .LMB_Data_Addr_8(NLW_U0_LMB_Data_Addr_8_UNCONNECTED[0:31]), - .LMB_Data_Addr_9(NLW_U0_LMB_Data_Addr_9_UNCONNECTED[0:31]), - .LMB_Data_Read_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Read_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .LMB_Data_Write_0(NLW_U0_LMB_Data_Write_0_UNCONNECTED[0:31]), - .LMB_Data_Write_1(NLW_U0_LMB_Data_Write_1_UNCONNECTED[0:31]), - .LMB_Data_Write_10(NLW_U0_LMB_Data_Write_10_UNCONNECTED[0:31]), - .LMB_Data_Write_11(NLW_U0_LMB_Data_Write_11_UNCONNECTED[0:31]), - .LMB_Data_Write_12(NLW_U0_LMB_Data_Write_12_UNCONNECTED[0:31]), - .LMB_Data_Write_13(NLW_U0_LMB_Data_Write_13_UNCONNECTED[0:31]), - .LMB_Data_Write_14(NLW_U0_LMB_Data_Write_14_UNCONNECTED[0:31]), - .LMB_Data_Write_15(NLW_U0_LMB_Data_Write_15_UNCONNECTED[0:31]), - .LMB_Data_Write_16(NLW_U0_LMB_Data_Write_16_UNCONNECTED[0:31]), - .LMB_Data_Write_17(NLW_U0_LMB_Data_Write_17_UNCONNECTED[0:31]), - .LMB_Data_Write_18(NLW_U0_LMB_Data_Write_18_UNCONNECTED[0:31]), - .LMB_Data_Write_19(NLW_U0_LMB_Data_Write_19_UNCONNECTED[0:31]), - .LMB_Data_Write_2(NLW_U0_LMB_Data_Write_2_UNCONNECTED[0:31]), - .LMB_Data_Write_20(NLW_U0_LMB_Data_Write_20_UNCONNECTED[0:31]), - .LMB_Data_Write_21(NLW_U0_LMB_Data_Write_21_UNCONNECTED[0:31]), - .LMB_Data_Write_22(NLW_U0_LMB_Data_Write_22_UNCONNECTED[0:31]), - .LMB_Data_Write_23(NLW_U0_LMB_Data_Write_23_UNCONNECTED[0:31]), - .LMB_Data_Write_24(NLW_U0_LMB_Data_Write_24_UNCONNECTED[0:31]), - .LMB_Data_Write_25(NLW_U0_LMB_Data_Write_25_UNCONNECTED[0:31]), - .LMB_Data_Write_26(NLW_U0_LMB_Data_Write_26_UNCONNECTED[0:31]), - .LMB_Data_Write_27(NLW_U0_LMB_Data_Write_27_UNCONNECTED[0:31]), - .LMB_Data_Write_28(NLW_U0_LMB_Data_Write_28_UNCONNECTED[0:31]), - .LMB_Data_Write_29(NLW_U0_LMB_Data_Write_29_UNCONNECTED[0:31]), - .LMB_Data_Write_3(NLW_U0_LMB_Data_Write_3_UNCONNECTED[0:31]), - .LMB_Data_Write_30(NLW_U0_LMB_Data_Write_30_UNCONNECTED[0:31]), - .LMB_Data_Write_31(NLW_U0_LMB_Data_Write_31_UNCONNECTED[0:31]), - .LMB_Data_Write_4(NLW_U0_LMB_Data_Write_4_UNCONNECTED[0:31]), - .LMB_Data_Write_5(NLW_U0_LMB_Data_Write_5_UNCONNECTED[0:31]), - .LMB_Data_Write_6(NLW_U0_LMB_Data_Write_6_UNCONNECTED[0:31]), - .LMB_Data_Write_7(NLW_U0_LMB_Data_Write_7_UNCONNECTED[0:31]), - .LMB_Data_Write_8(NLW_U0_LMB_Data_Write_8_UNCONNECTED[0:31]), - .LMB_Data_Write_9(NLW_U0_LMB_Data_Write_9_UNCONNECTED[0:31]), - .LMB_Read_Strobe_0(NLW_U0_LMB_Read_Strobe_0_UNCONNECTED), - .LMB_Read_Strobe_1(NLW_U0_LMB_Read_Strobe_1_UNCONNECTED), - .LMB_Read_Strobe_10(NLW_U0_LMB_Read_Strobe_10_UNCONNECTED), - .LMB_Read_Strobe_11(NLW_U0_LMB_Read_Strobe_11_UNCONNECTED), - .LMB_Read_Strobe_12(NLW_U0_LMB_Read_Strobe_12_UNCONNECTED), - .LMB_Read_Strobe_13(NLW_U0_LMB_Read_Strobe_13_UNCONNECTED), - .LMB_Read_Strobe_14(NLW_U0_LMB_Read_Strobe_14_UNCONNECTED), - .LMB_Read_Strobe_15(NLW_U0_LMB_Read_Strobe_15_UNCONNECTED), - .LMB_Read_Strobe_16(NLW_U0_LMB_Read_Strobe_16_UNCONNECTED), - .LMB_Read_Strobe_17(NLW_U0_LMB_Read_Strobe_17_UNCONNECTED), - .LMB_Read_Strobe_18(NLW_U0_LMB_Read_Strobe_18_UNCONNECTED), - .LMB_Read_Strobe_19(NLW_U0_LMB_Read_Strobe_19_UNCONNECTED), - .LMB_Read_Strobe_2(NLW_U0_LMB_Read_Strobe_2_UNCONNECTED), - .LMB_Read_Strobe_20(NLW_U0_LMB_Read_Strobe_20_UNCONNECTED), - .LMB_Read_Strobe_21(NLW_U0_LMB_Read_Strobe_21_UNCONNECTED), - .LMB_Read_Strobe_22(NLW_U0_LMB_Read_Strobe_22_UNCONNECTED), - .LMB_Read_Strobe_23(NLW_U0_LMB_Read_Strobe_23_UNCONNECTED), - .LMB_Read_Strobe_24(NLW_U0_LMB_Read_Strobe_24_UNCONNECTED), - .LMB_Read_Strobe_25(NLW_U0_LMB_Read_Strobe_25_UNCONNECTED), - .LMB_Read_Strobe_26(NLW_U0_LMB_Read_Strobe_26_UNCONNECTED), - .LMB_Read_Strobe_27(NLW_U0_LMB_Read_Strobe_27_UNCONNECTED), - .LMB_Read_Strobe_28(NLW_U0_LMB_Read_Strobe_28_UNCONNECTED), - .LMB_Read_Strobe_29(NLW_U0_LMB_Read_Strobe_29_UNCONNECTED), - .LMB_Read_Strobe_3(NLW_U0_LMB_Read_Strobe_3_UNCONNECTED), - .LMB_Read_Strobe_30(NLW_U0_LMB_Read_Strobe_30_UNCONNECTED), - .LMB_Read_Strobe_31(NLW_U0_LMB_Read_Strobe_31_UNCONNECTED), - .LMB_Read_Strobe_4(NLW_U0_LMB_Read_Strobe_4_UNCONNECTED), - .LMB_Read_Strobe_5(NLW_U0_LMB_Read_Strobe_5_UNCONNECTED), - .LMB_Read_Strobe_6(NLW_U0_LMB_Read_Strobe_6_UNCONNECTED), - .LMB_Read_Strobe_7(NLW_U0_LMB_Read_Strobe_7_UNCONNECTED), - .LMB_Read_Strobe_8(NLW_U0_LMB_Read_Strobe_8_UNCONNECTED), - .LMB_Read_Strobe_9(NLW_U0_LMB_Read_Strobe_9_UNCONNECTED), - .LMB_Ready_0(1'b0), - .LMB_Ready_1(1'b0), - .LMB_Ready_10(1'b0), - .LMB_Ready_11(1'b0), - .LMB_Ready_12(1'b0), - .LMB_Ready_13(1'b0), - .LMB_Ready_14(1'b0), - .LMB_Ready_15(1'b0), - .LMB_Ready_16(1'b0), - .LMB_Ready_17(1'b0), - .LMB_Ready_18(1'b0), - .LMB_Ready_19(1'b0), - .LMB_Ready_2(1'b0), - .LMB_Ready_20(1'b0), - .LMB_Ready_21(1'b0), - .LMB_Ready_22(1'b0), - .LMB_Ready_23(1'b0), - .LMB_Ready_24(1'b0), - .LMB_Ready_25(1'b0), - .LMB_Ready_26(1'b0), - .LMB_Ready_27(1'b0), - .LMB_Ready_28(1'b0), - .LMB_Ready_29(1'b0), - .LMB_Ready_3(1'b0), - .LMB_Ready_30(1'b0), - .LMB_Ready_31(1'b0), - .LMB_Ready_4(1'b0), - .LMB_Ready_5(1'b0), - .LMB_Ready_6(1'b0), - .LMB_Ready_7(1'b0), - .LMB_Ready_8(1'b0), - .LMB_Ready_9(1'b0), - .LMB_UE_0(1'b0), - .LMB_UE_1(1'b0), - .LMB_UE_10(1'b0), - .LMB_UE_11(1'b0), - .LMB_UE_12(1'b0), - .LMB_UE_13(1'b0), - .LMB_UE_14(1'b0), - .LMB_UE_15(1'b0), - .LMB_UE_16(1'b0), - .LMB_UE_17(1'b0), - .LMB_UE_18(1'b0), - .LMB_UE_19(1'b0), - .LMB_UE_2(1'b0), - .LMB_UE_20(1'b0), - .LMB_UE_21(1'b0), - .LMB_UE_22(1'b0), - .LMB_UE_23(1'b0), - .LMB_UE_24(1'b0), - .LMB_UE_25(1'b0), - .LMB_UE_26(1'b0), - .LMB_UE_27(1'b0), - .LMB_UE_28(1'b0), - .LMB_UE_29(1'b0), - .LMB_UE_3(1'b0), - .LMB_UE_30(1'b0), - .LMB_UE_31(1'b0), - .LMB_UE_4(1'b0), - .LMB_UE_5(1'b0), - .LMB_UE_6(1'b0), - .LMB_UE_7(1'b0), - .LMB_UE_8(1'b0), - .LMB_UE_9(1'b0), - .LMB_Wait_0(1'b0), - .LMB_Wait_1(1'b0), - .LMB_Wait_10(1'b0), - .LMB_Wait_11(1'b0), - .LMB_Wait_12(1'b0), - .LMB_Wait_13(1'b0), - .LMB_Wait_14(1'b0), - .LMB_Wait_15(1'b0), - .LMB_Wait_16(1'b0), - .LMB_Wait_17(1'b0), - .LMB_Wait_18(1'b0), - .LMB_Wait_19(1'b0), - .LMB_Wait_2(1'b0), - .LMB_Wait_20(1'b0), - .LMB_Wait_21(1'b0), - .LMB_Wait_22(1'b0), - .LMB_Wait_23(1'b0), - .LMB_Wait_24(1'b0), - .LMB_Wait_25(1'b0), - .LMB_Wait_26(1'b0), - .LMB_Wait_27(1'b0), - .LMB_Wait_28(1'b0), - .LMB_Wait_29(1'b0), - .LMB_Wait_3(1'b0), - .LMB_Wait_30(1'b0), - .LMB_Wait_31(1'b0), - .LMB_Wait_4(1'b0), - .LMB_Wait_5(1'b0), - .LMB_Wait_6(1'b0), - .LMB_Wait_7(1'b0), - .LMB_Wait_8(1'b0), - .LMB_Wait_9(1'b0), - .LMB_Write_Strobe_0(NLW_U0_LMB_Write_Strobe_0_UNCONNECTED), - .LMB_Write_Strobe_1(NLW_U0_LMB_Write_Strobe_1_UNCONNECTED), - .LMB_Write_Strobe_10(NLW_U0_LMB_Write_Strobe_10_UNCONNECTED), - .LMB_Write_Strobe_11(NLW_U0_LMB_Write_Strobe_11_UNCONNECTED), - .LMB_Write_Strobe_12(NLW_U0_LMB_Write_Strobe_12_UNCONNECTED), - .LMB_Write_Strobe_13(NLW_U0_LMB_Write_Strobe_13_UNCONNECTED), - .LMB_Write_Strobe_14(NLW_U0_LMB_Write_Strobe_14_UNCONNECTED), - .LMB_Write_Strobe_15(NLW_U0_LMB_Write_Strobe_15_UNCONNECTED), - .LMB_Write_Strobe_16(NLW_U0_LMB_Write_Strobe_16_UNCONNECTED), - .LMB_Write_Strobe_17(NLW_U0_LMB_Write_Strobe_17_UNCONNECTED), - .LMB_Write_Strobe_18(NLW_U0_LMB_Write_Strobe_18_UNCONNECTED), - .LMB_Write_Strobe_19(NLW_U0_LMB_Write_Strobe_19_UNCONNECTED), - .LMB_Write_Strobe_2(NLW_U0_LMB_Write_Strobe_2_UNCONNECTED), - .LMB_Write_Strobe_20(NLW_U0_LMB_Write_Strobe_20_UNCONNECTED), - .LMB_Write_Strobe_21(NLW_U0_LMB_Write_Strobe_21_UNCONNECTED), - .LMB_Write_Strobe_22(NLW_U0_LMB_Write_Strobe_22_UNCONNECTED), - .LMB_Write_Strobe_23(NLW_U0_LMB_Write_Strobe_23_UNCONNECTED), - .LMB_Write_Strobe_24(NLW_U0_LMB_Write_Strobe_24_UNCONNECTED), - .LMB_Write_Strobe_25(NLW_U0_LMB_Write_Strobe_25_UNCONNECTED), - .LMB_Write_Strobe_26(NLW_U0_LMB_Write_Strobe_26_UNCONNECTED), - .LMB_Write_Strobe_27(NLW_U0_LMB_Write_Strobe_27_UNCONNECTED), - .LMB_Write_Strobe_28(NLW_U0_LMB_Write_Strobe_28_UNCONNECTED), - .LMB_Write_Strobe_29(NLW_U0_LMB_Write_Strobe_29_UNCONNECTED), - .LMB_Write_Strobe_3(NLW_U0_LMB_Write_Strobe_3_UNCONNECTED), - .LMB_Write_Strobe_30(NLW_U0_LMB_Write_Strobe_30_UNCONNECTED), - .LMB_Write_Strobe_31(NLW_U0_LMB_Write_Strobe_31_UNCONNECTED), - .LMB_Write_Strobe_4(NLW_U0_LMB_Write_Strobe_4_UNCONNECTED), - .LMB_Write_Strobe_5(NLW_U0_LMB_Write_Strobe_5_UNCONNECTED), - .LMB_Write_Strobe_6(NLW_U0_LMB_Write_Strobe_6_UNCONNECTED), - .LMB_Write_Strobe_7(NLW_U0_LMB_Write_Strobe_7_UNCONNECTED), - .LMB_Write_Strobe_8(NLW_U0_LMB_Write_Strobe_8_UNCONNECTED), - .LMB_Write_Strobe_9(NLW_U0_LMB_Write_Strobe_9_UNCONNECTED), - .M_AXIS_ACLK(1'b0), - .M_AXIS_ARESETN(1'b0), - .M_AXIS_TDATA(NLW_U0_M_AXIS_TDATA_UNCONNECTED[31:0]), - .M_AXIS_TID(NLW_U0_M_AXIS_TID_UNCONNECTED[6:0]), - .M_AXIS_TREADY(1'b1), - .M_AXIS_TVALID(NLW_U0_M_AXIS_TVALID_UNCONNECTED), - .M_AXI_ACLK(1'b0), - .M_AXI_ARADDR(NLW_U0_M_AXI_ARADDR_UNCONNECTED[31:0]), - .M_AXI_ARBURST(NLW_U0_M_AXI_ARBURST_UNCONNECTED[1:0]), - .M_AXI_ARCACHE(NLW_U0_M_AXI_ARCACHE_UNCONNECTED[3:0]), - .M_AXI_ARESETN(1'b0), - .M_AXI_ARID(NLW_U0_M_AXI_ARID_UNCONNECTED[0]), - .M_AXI_ARLEN(NLW_U0_M_AXI_ARLEN_UNCONNECTED[7:0]), - .M_AXI_ARLOCK(NLW_U0_M_AXI_ARLOCK_UNCONNECTED), - .M_AXI_ARPROT(NLW_U0_M_AXI_ARPROT_UNCONNECTED[2:0]), - .M_AXI_ARQOS(NLW_U0_M_AXI_ARQOS_UNCONNECTED[3:0]), - .M_AXI_ARREADY(1'b0), - .M_AXI_ARSIZE(NLW_U0_M_AXI_ARSIZE_UNCONNECTED[2:0]), - .M_AXI_ARVALID(NLW_U0_M_AXI_ARVALID_UNCONNECTED), - .M_AXI_AWADDR(NLW_U0_M_AXI_AWADDR_UNCONNECTED[31:0]), - .M_AXI_AWBURST(NLW_U0_M_AXI_AWBURST_UNCONNECTED[1:0]), - .M_AXI_AWCACHE(NLW_U0_M_AXI_AWCACHE_UNCONNECTED[3:0]), - .M_AXI_AWID(NLW_U0_M_AXI_AWID_UNCONNECTED[0]), - .M_AXI_AWLEN(NLW_U0_M_AXI_AWLEN_UNCONNECTED[7:0]), - .M_AXI_AWLOCK(NLW_U0_M_AXI_AWLOCK_UNCONNECTED), - .M_AXI_AWPROT(NLW_U0_M_AXI_AWPROT_UNCONNECTED[2:0]), - .M_AXI_AWQOS(NLW_U0_M_AXI_AWQOS_UNCONNECTED[3:0]), - .M_AXI_AWREADY(1'b0), - .M_AXI_AWSIZE(NLW_U0_M_AXI_AWSIZE_UNCONNECTED[2:0]), - .M_AXI_AWVALID(NLW_U0_M_AXI_AWVALID_UNCONNECTED), - .M_AXI_BID(1'b0), - .M_AXI_BREADY(NLW_U0_M_AXI_BREADY_UNCONNECTED), - .M_AXI_BRESP({1'b0,1'b0}), - .M_AXI_BVALID(1'b0), - .M_AXI_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .M_AXI_RID(1'b0), - .M_AXI_RLAST(1'b0), - .M_AXI_RREADY(NLW_U0_M_AXI_RREADY_UNCONNECTED), - .M_AXI_RRESP({1'b0,1'b0}), - .M_AXI_RVALID(1'b0), - .M_AXI_WDATA(NLW_U0_M_AXI_WDATA_UNCONNECTED[31:0]), - .M_AXI_WLAST(NLW_U0_M_AXI_WLAST_UNCONNECTED), - .M_AXI_WREADY(1'b0), - .M_AXI_WSTRB(NLW_U0_M_AXI_WSTRB_UNCONNECTED[3:0]), - .M_AXI_WVALID(NLW_U0_M_AXI_WVALID_UNCONNECTED), - .S_AXI_ACLK(1'b0), - .S_AXI_ARADDR({1'b0,1'b0,1'b0,1'b0}), - .S_AXI_ARESETN(1'b0), - .S_AXI_ARREADY(NLW_U0_S_AXI_ARREADY_UNCONNECTED), - .S_AXI_ARVALID(1'b0), - .S_AXI_AWADDR({1'b0,1'b0,1'b0,1'b0}), - .S_AXI_AWREADY(NLW_U0_S_AXI_AWREADY_UNCONNECTED), - .S_AXI_AWVALID(1'b0), - .S_AXI_BREADY(1'b0), - .S_AXI_BRESP(NLW_U0_S_AXI_BRESP_UNCONNECTED[1:0]), - .S_AXI_BVALID(NLW_U0_S_AXI_BVALID_UNCONNECTED), - .S_AXI_RDATA(NLW_U0_S_AXI_RDATA_UNCONNECTED[31:0]), - .S_AXI_RREADY(1'b0), - .S_AXI_RRESP(NLW_U0_S_AXI_RRESP_UNCONNECTED[1:0]), - .S_AXI_RVALID(NLW_U0_S_AXI_RVALID_UNCONNECTED), - .S_AXI_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .S_AXI_WREADY(NLW_U0_S_AXI_WREADY_UNCONNECTED), - .S_AXI_WSTRB({1'b0,1'b0,1'b0,1'b0}), - .S_AXI_WVALID(1'b0), - .Scan_En(1'b0), - .Scan_Reset(1'b0), - .Scan_Reset_Sel(1'b0), - .TRACE_CLK(1'b0), - .TRACE_CLK_OUT(NLW_U0_TRACE_CLK_OUT_UNCONNECTED), - .TRACE_CTL(NLW_U0_TRACE_CTL_UNCONNECTED), - .TRACE_DATA(NLW_U0_TRACE_DATA_UNCONNECTED[31:0]), - .Trig_Ack_In_0(NLW_U0_Trig_Ack_In_0_UNCONNECTED), - .Trig_Ack_In_1(NLW_U0_Trig_Ack_In_1_UNCONNECTED), - .Trig_Ack_In_2(NLW_U0_Trig_Ack_In_2_UNCONNECTED), - .Trig_Ack_In_3(NLW_U0_Trig_Ack_In_3_UNCONNECTED), - .Trig_Ack_Out_0(1'b0), - .Trig_Ack_Out_1(1'b0), - .Trig_Ack_Out_2(1'b0), - .Trig_Ack_Out_3(1'b0), - .Trig_In_0(1'b0), - .Trig_In_1(1'b0), - .Trig_In_2(1'b0), - .Trig_In_3(1'b0), - .Trig_Out_0(NLW_U0_Trig_Out_0_UNCONNECTED), - .Trig_Out_1(NLW_U0_Trig_Out_1_UNCONNECTED), - .Trig_Out_2(NLW_U0_Trig_Out_2_UNCONNECTED), - .Trig_Out_3(NLW_U0_Trig_Out_3_UNCONNECTED), - .bscan_ext_bscanid_en(1'b0), - .bscan_ext_capture(1'b0), - .bscan_ext_drck(1'b0), - .bscan_ext_reset(1'b0), - .bscan_ext_sel(1'b0), - .bscan_ext_shift(1'b0), - .bscan_ext_tck(1'b0), - .bscan_ext_tdi(1'b0), - .bscan_ext_tdo(NLW_U0_bscan_ext_tdo_UNCONNECTED), - .bscan_ext_update(1'b0)); -endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.vhdl index 211adda1..45edf371 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:15 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_mdm_0 -prefix --- system_bd_mdm_0_ system_bd_mdm_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:54 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.vhdl -- Design : system_bd_mdm_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -42,6 +42,8 @@ entity system_bd_mdm_0_MB_BSCANE2 is Dbg_TDO_0 : in STD_LOGIC; \Use_Serial_Unified_Completion.completion_status_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_MB_BSCANE2 : entity is "MB_BSCANE2"; end system_bd_mdm_0_MB_BSCANE2; architecture STRUCTURE of system_bd_mdm_0_MB_BSCANE2 is @@ -170,6 +172,8 @@ entity system_bd_mdm_0_MB_BUFG is Ext_JTAG_DRCK : out STD_LOGIC; DRCK : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_MB_BUFG : entity is "MB_BUFG"; end system_bd_mdm_0_MB_BUFG; architecture STRUCTURE of system_bd_mdm_0_MB_BUFG is @@ -240,6 +244,8 @@ entity system_bd_mdm_0_MB_FDC_1 is Debug_SYS_Rst : in STD_LOGIC; Ext_NM_BRK : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_MB_FDC_1 : entity is "MB_FDC_1"; end system_bd_mdm_0_MB_FDC_1; architecture STRUCTURE of system_bd_mdm_0_MB_FDC_1 is @@ -854,6 +860,8 @@ entity system_bd_mdm_0_MB_FDRE_1 is Dbg_Shift_0_3 : in STD_LOGIC; Dbg_Shift_0_4 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_MB_FDRE_1 : entity is "MB_FDRE_1"; end system_bd_mdm_0_MB_FDRE_1; architecture STRUCTURE of system_bd_mdm_0_MB_FDRE_1 is @@ -910,6 +918,8 @@ entity system_bd_mdm_0_MB_SRL16E is \Use_E2.BSCANE2_I_i_4_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); config_TDO_2 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_MB_SRL16E : entity is "MB_SRL16E"; end system_bd_mdm_0_MB_SRL16E; architecture STRUCTURE of system_bd_mdm_0_MB_SRL16E is @@ -1149,6 +1159,8 @@ entity system_bd_mdm_0_JTAG_CONTROL is \Use_Serial_Unified_Completion.count_reg[5]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \shift_Count_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_JTAG_CONTROL : entity is "JTAG_CONTROL"; end system_bd_mdm_0_JTAG_CONTROL; architecture STRUCTURE of system_bd_mdm_0_JTAG_CONTROL is @@ -2682,6 +2694,8 @@ entity system_bd_mdm_0_MDM_Core is AR : in STD_LOGIC_VECTOR ( 0 to 0 ); \Use_Serial_Unified_Completion.count_reg[5]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_MDM_Core : entity is "MDM_Core"; end system_bd_mdm_0_MDM_Core; architecture STRUCTURE of system_bd_mdm_0_MDM_Core is @@ -4853,6 +4867,8 @@ entity system_bd_mdm_0_MDM is attribute C_USE_CROSS_TRIGGER of system_bd_mdm_0_MDM : entity is 0; attribute C_USE_UART : integer; attribute C_USE_UART of system_bd_mdm_0_MDM : entity is 0; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_mdm_0_MDM : entity is "MDM"; end system_bd_mdm_0_MDM; architecture STRUCTURE of system_bd_mdm_0_MDM is diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v index 6613942d..04f84fb0 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:15 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_mdm_0 -prefix -// system_bd_mdm_0_ system_bd_mdm_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:53 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v // Design : system_bd_mdm_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl index 381239c0..330973d2 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:15 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_mdm_0 -prefix --- system_bd_mdm_0_ system_bd_mdm_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:53 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl -- Design : system_bd_mdm_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/data/mb_bootloop_le.elf b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/data/mb_bootloop_le.elf old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.dcp index 815f27ac..75e8668d 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.xml index 9e79fb6c..b326ac55 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.xml @@ -13931,7 +13931,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -13949,7 +13949,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -13969,7 +13969,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -13989,7 +13989,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -14009,7 +14009,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:54 UTC 2023 outputProductCRC @@ -14027,7 +14027,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:56:18 UTC 2023 outputProductCRC @@ -25472,6 +25472,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_microblaze_ps_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_microblaze_ps_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_microblaze_ps_0_sim_netlist.v verilogSource @@ -25486,18 +25498,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_microblaze_ps_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_microblaze_ps_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.v index f4a8af8e..d4a8c2eb 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:31 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_microblaze_ps_0 -prefix -// system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:17 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.v // Design : system_bd_microblaze_ps_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -1028,6 +1028,7 @@ module system_bd_microblaze_ps_0 .Write_Strobe(Write_Strobe)); endmodule +(* ORIG_REF_NAME = "ALU" *) module system_bd_microblaze_ps_0_ALU (LO, \EX_Op2_reg[0] , @@ -1708,6 +1709,7 @@ module system_bd_microblaze_ps_0_ALU .lopt_3(lopt_74)); endmodule +(* ORIG_REF_NAME = "ALU_Bit" *) module system_bd_microblaze_ps_0_ALU_Bit (EX_CarryOut, \EX_Op2_reg[10] , @@ -3951,6 +3953,7 @@ module system_bd_microblaze_ps_0_ALU_Bit__parameterized2 .lopt(lopt)); endmodule +(* ORIG_REF_NAME = "Byte_Doublet_Handle_gti" *) module system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti (\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0 , wb_read_msb_doublet_sel, @@ -4289,6 +4292,7 @@ module system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti .R(sync_reset)); endmodule +(* ORIG_REF_NAME = "DAXI_interface" *) module system_bd_microblaze_ps_0_DAXI_interface (active_access_d1, active_access, @@ -5257,6 +5261,7 @@ module system_bd_microblaze_ps_0_DAXI_interface .R(sync_reset)); endmodule +(* ORIG_REF_NAME = "Data_Flow_Logic" *) module system_bd_microblaze_ps_0_Data_Flow_Logic (\Using_FPGA.Native , MEM_Fwd, @@ -5707,6 +5712,7 @@ module system_bd_microblaze_ps_0_Data_Flow_Logic .R(SR)); endmodule +(* ORIG_REF_NAME = "Data_Flow_gti" *) module system_bd_microblaze_ps_0_Data_Flow_gti (\EX_Op1_reg[0] , out, @@ -6544,6 +6550,7 @@ module system_bd_microblaze_ps_0_Data_Flow_gti .wb_piperun(wb_piperun)); endmodule +(* ORIG_REF_NAME = "Debug" *) module system_bd_microblaze_ps_0_Debug (LOCKSTEP_Master_Out, \Serial_Dbg_Intf.force_stop_cmd_i_reg_0 , @@ -9720,6 +9727,7 @@ module system_bd_microblaze_ps_0_Debug .R(1'b0)); endmodule +(* ORIG_REF_NAME = "Decode_gti" *) module system_bd_microblaze_ps_0_Decode_gti (of_pause_reg_0, D, @@ -14494,6 +14502,7 @@ module system_bd_microblaze_ps_0_Decode_gti .R(1'b0)); endmodule +(* ORIG_REF_NAME = "MB_AND2B1L" *) module system_bd_microblaze_ps_0_MB_AND2B1L (D, E, @@ -14515,6 +14524,7 @@ module system_bd_microblaze_ps_0_MB_AND2B1L .SRI(SRI)); endmodule +(* ORIG_REF_NAME = "MB_FDE" *) module system_bd_microblaze_ps_0_MB_FDE (\Using_FPGA.Native_0 , \Using_FPGA.Native_1 , @@ -15410,6 +15420,7 @@ module system_bd_microblaze_ps_0_MB_FDE_401 .R(1'b0)); endmodule +(* ORIG_REF_NAME = "MB_FDR" *) module system_bd_microblaze_ps_0_MB_FDR (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg , sync_reset, @@ -15496,6 +15507,7 @@ module system_bd_microblaze_ps_0_MB_FDR .O(of_set_MSR_EE1)); endmodule +(* ORIG_REF_NAME = "MB_FDRE" *) module system_bd_microblaze_ps_0_MB_FDRE (D, sync_reset, @@ -25629,6 +25641,7 @@ module system_bd_microblaze_ps_0_MB_FDR_306 .O(\Using_FPGA.Native_0 )); endmodule +(* ORIG_REF_NAME = "MB_FDS" *) module system_bd_microblaze_ps_0_MB_FDS (\Using_FPGA.Native_0 , I041_out, @@ -26188,6 +26201,7 @@ module system_bd_microblaze_ps_0_MB_FDS .O(I0_1)); endmodule +(* ORIG_REF_NAME = "MB_LUT4" *) module system_bd_microblaze_ps_0_MB_LUT4 (S, Q, @@ -26217,6 +26231,7 @@ module system_bd_microblaze_ps_0_MB_LUT4 .O(S)); endmodule +(* ORIG_REF_NAME = "MB_LUT6" *) module system_bd_microblaze_ps_0_MB_LUT6 (sel_input_iii_3, if_sel_input, @@ -26359,6 +26374,7 @@ module system_bd_microblaze_ps_0_MB_LUT6_118 .O(sel_input_iii_0)); endmodule +(* ORIG_REF_NAME = "MB_LUT6_2" *) module system_bd_microblaze_ps_0_MB_LUT6_2 (DI, S, @@ -29827,6 +29843,7 @@ module system_bd_microblaze_ps_0_MB_LUT6__parameterized8_84 .O(of_read_mem_write_op3_conflict_part1)); endmodule +(* ORIG_REF_NAME = "MB_MULT_AND" *) module system_bd_microblaze_ps_0_MB_MULT_AND (DI, I0, @@ -29850,6 +29867,7 @@ module system_bd_microblaze_ps_0_MB_MULT_AND .O(DI)); endmodule +(* ORIG_REF_NAME = "MB_MUXCY" *) module system_bd_microblaze_ps_0_MB_MUXCY (carry_7, SRL16_Sel_7, @@ -32283,6 +32301,7 @@ module system_bd_microblaze_ps_0_MB_MUXCY_99 .O(if_valid)); endmodule +(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) module system_bd_microblaze_ps_0_MB_MUXCY_XORCY (O56_out, Q, @@ -36376,6 +36395,7 @@ module system_bd_microblaze_ps_0_MB_MUXCY_XORCY_580 assign \EX_Op2_reg[0]_0 = lopt_1; endmodule +(* ORIG_REF_NAME = "MB_MUXF7" *) module system_bd_microblaze_ps_0_MB_MUXF7 (sel_input_i_1, I4_0, @@ -39971,6 +39991,7 @@ module system_bd_microblaze_ps_0_MB_MUXF7_455 .O(swap_result)); endmodule +(* ORIG_REF_NAME = "MB_RAM32M" *) module system_bd_microblaze_ps_0_MB_RAM32M (GPR_Op1, GPR_Op2, @@ -40930,6 +40951,7 @@ module system_bd_microblaze_ps_0_MB_RAM32M_423 .WE(\EX_Branch_CMP_Op1_reg[18] )); endmodule +(* ORIG_REF_NAME = "MB_SRL16E" *) module system_bd_microblaze_ps_0_MB_SRL16E (Q_0, Q, @@ -41480,6 +41502,7 @@ module system_bd_microblaze_ps_0_MB_SRL16E__parameterized9 .Q(Q1_in)); endmodule +(* ORIG_REF_NAME = "MB_SRLC16E" *) module system_bd_microblaze_ps_0_MB_SRLC16E (SRL16_Sel_7, which_pc__0, @@ -41863,7 +41886,7 @@ endmodule (* C_USE_HW_MUL = "0" *) (* C_USE_ICACHE = "0" *) (* C_USE_INTERRUPT = "0" *) (* C_USE_MMU = "0" *) (* C_USE_MSR_INSTR = "0" *) (* C_USE_NON_SECURE = "0" *) (* C_USE_PCMP_INSTR = "0" *) (* C_USE_REORDER_INSTR = "1" *) (* C_USE_STACK_PROTECTION = "0" *) -(* downgradeipidentifiedwarnings = "yes" *) +(* ORIG_REF_NAME = "MicroBlaze" *) (* downgradeipidentifiedwarnings = "yes" *) module system_bd_microblaze_ps_0_MicroBlaze (RAM_To, RAM_From, @@ -54508,6 +54531,7 @@ module system_bd_microblaze_ps_0_MicroBlaze (.P(\ )); endmodule +(* ORIG_REF_NAME = "MicroBlaze_Core" *) module system_bd_microblaze_ps_0_MicroBlaze_Core (of_pause_reg, \Using_FPGA.Native , @@ -54730,6 +54754,7 @@ module system_bd_microblaze_ps_0_MicroBlaze_Core .O(reset_temp__0)); endmodule +(* ORIG_REF_NAME = "MicroBlaze_GTi" *) module system_bd_microblaze_ps_0_MicroBlaze_GTi (E, \Using_FPGA.Native , @@ -56261,6 +56286,7 @@ module system_bd_microblaze_ps_0_MicroBlaze_GTi .R(1'b0)); endmodule +(* ORIG_REF_NAME = "Operand_Select_gti" *) module system_bd_microblaze_ps_0_Operand_Select_gti (ex_load_alu_carry_reg, Q, @@ -57894,6 +57920,7 @@ module system_bd_microblaze_ps_0_Operand_Select_gti .O(in0)); endmodule +(* ORIG_REF_NAME = "PC_Module_gti" *) module system_bd_microblaze_ps_0_PC_Module_gti (D, O56_out, @@ -60194,6 +60221,7 @@ module system_bd_microblaze_ps_0_PC_Module_gti .R(sync_reset)); endmodule +(* ORIG_REF_NAME = "PreFetch_Buffer_gti" *) module system_bd_microblaze_ps_0_PreFetch_Buffer_gti (\Using_FPGA.Native , \Using_FPGA.Native_0 , @@ -62878,6 +62906,7 @@ module system_bd_microblaze_ps_0_PreFetch_Buffer_gti .Q(p_1_in164_in)); endmodule +(* ORIG_REF_NAME = "Register_File_gti" *) module system_bd_microblaze_ps_0_Register_File_gti (GPR_Op1, GPR_Op2, @@ -63134,6 +63163,7 @@ module system_bd_microblaze_ps_0_Register_File_gti .of_imm_data(of_imm_data)); endmodule +(* ORIG_REF_NAME = "Shift_Logic_Module_gti" *) module system_bd_microblaze_ps_0_Shift_Logic_Module_gti (out, \EX_Op1_reg[24] , @@ -63153,6 +63183,7 @@ module system_bd_microblaze_ps_0_Shift_Logic_Module_gti assign sign_doublet = \Using_FPGA.Native ; endmodule +(* ORIG_REF_NAME = "Zero_Detect_gti" *) module system_bd_microblaze_ps_0_Zero_Detect_gti (ex_op1_zero, ex_op1_cmp_equal, @@ -63303,6 +63334,7 @@ module system_bd_microblaze_ps_0_Zero_Detect_gti .zero_CI_6(zero_CI_6)); endmodule +(* ORIG_REF_NAME = "address_hit" *) module system_bd_microblaze_ps_0_address_hit (Hit, single_Step_N_reg, @@ -63540,6 +63572,7 @@ module system_bd_microblaze_ps_0_address_hit .single_Step_N_reg(single_Step_N_reg)); endmodule +(* ORIG_REF_NAME = "carry_and" *) module system_bd_microblaze_ps_0_carry_and (of_PipeRun_carry_1, use_Reg_Neg_S_reg, @@ -64216,6 +64249,7 @@ module system_bd_microblaze_ps_0_carry_and_89 .wb_valid_reg_0(wb_valid_reg_0)); endmodule +(* ORIG_REF_NAME = "carry_or" *) module system_bd_microblaze_ps_0_carry_or (mem_wait_on_ready_N, MEM_DataBus_Ready, @@ -64278,6 +64312,7 @@ module system_bd_microblaze_ps_0_carry_or .mem_wait_on_ready_N(mem_wait_on_ready_N)); endmodule +(* ORIG_REF_NAME = "exception_registers_gti" *) module system_bd_microblaze_ps_0_exception_registers_gti (DI, \Using_FPGA.Native , @@ -65375,6 +65410,7 @@ module system_bd_microblaze_ps_0_exception_registers_gti .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0 )); endmodule +(* ORIG_REF_NAME = "instr_mux" *) module system_bd_microblaze_ps_0_instr_mux (I139_out, Y, @@ -65409,6 +65445,7 @@ module system_bd_microblaze_ps_0_instr_mux .in(in)); endmodule +(* ORIG_REF_NAME = "jump_logic" *) module system_bd_microblaze_ps_0_jump_logic (ex_jump, ex_op1_cmp_equal, @@ -65882,6 +65919,7 @@ module system_bd_microblaze_ps_0_jump_logic .R(reset_bool_for_rst)); endmodule +(* ORIG_REF_NAME = "mb_sync_bit" *) module system_bd_microblaze_ps_0_mb_sync_bit (out, reset_temp, @@ -66867,6 +66905,7 @@ module system_bd_microblaze_ps_0_mb_sync_bit__parameterized4_30 .R(sync_reset)); endmodule +(* ORIG_REF_NAME = "mb_sync_vec" *) module system_bd_microblaze_ps_0_mb_sync_vec (D, dbg_hit, @@ -67037,6 +67076,7 @@ module system_bd_microblaze_ps_0_mb_sync_vec__parameterized1 .sync_reset(sync_reset)); endmodule +(* ORIG_REF_NAME = "msr_reg_gti" *) module system_bd_microblaze_ps_0_msr_reg_gti (ex_MSR, MEM_Fwd, @@ -67174,6 +67214,7 @@ module system_bd_microblaze_ps_0_msr_reg_gti .R(sync_reset)); endmodule +(* ORIG_REF_NAME = "mux_bus" *) module system_bd_microblaze_ps_0_mux_bus (I139_out, Y, diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.vhdl index 82753e98..9a8c1705 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:31 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_microblaze_ps_0 -prefix --- system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:18 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.vhdl -- Design : system_bd_microblaze_ps_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -32,6 +32,8 @@ entity system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti is mem_byte_access : in STD_LOGIC; mem_doublet_access : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti : entity is "Byte_Doublet_Handle_gti"; end system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti is @@ -471,6 +473,8 @@ entity system_bd_microblaze_ps_0_DAXI_interface is M_AXI_DP_BVALID : in STD_LOGIC; M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_DAXI_interface : entity is "DAXI_interface"; end system_bd_microblaze_ps_0_DAXI_interface; architecture STRUCTURE of system_bd_microblaze_ps_0_DAXI_interface is @@ -1602,6 +1606,8 @@ entity system_bd_microblaze_ps_0_MB_AND2B1L is E : in STD_LOGIC_VECTOR ( 0 to 0 ); SRI : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_AND2B1L : entity is "MB_AND2B1L"; end system_bd_microblaze_ps_0_MB_AND2B1L; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_AND2B1L is @@ -1629,6 +1635,8 @@ entity system_bd_microblaze_ps_0_MB_FDE is \Using_FPGA.Native_2\ : in STD_LOGIC; Clk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDE : entity is "MB_FDE"; end system_bd_microblaze_ps_0_MB_FDE; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDE is @@ -2689,6 +2697,8 @@ entity system_bd_microblaze_ps_0_MB_FDR is E : in STD_LOGIC_VECTOR ( 0 to 0 ); \Using_FPGA.Native_3\ : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDR : entity is "MB_FDR"; end system_bd_microblaze_ps_0_MB_FDR; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDR is @@ -2775,6 +2785,8 @@ entity system_bd_microblaze_ps_0_MB_FDRE is Clk : in STD_LOGIC; mem_exception_from_ex : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDRE : entity is "MB_FDRE"; end system_bd_microblaze_ps_0_MB_FDRE; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDRE is @@ -13137,6 +13149,8 @@ entity system_bd_microblaze_ps_0_MB_FDS is \Using_FPGA.Native_16\ : in STD_LOGIC; \Using_FPGA.Native_17\ : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDS : entity is "MB_FDS"; end system_bd_microblaze_ps_0_MB_FDS; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDS is @@ -13646,6 +13660,8 @@ entity system_bd_microblaze_ps_0_MB_LUT4 is I2 : in STD_LOGIC; alu_AddSub_1 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_LUT4 : entity is "MB_LUT4"; end system_bd_microblaze_ps_0_MB_LUT4; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_LUT4 is @@ -13677,6 +13693,8 @@ entity system_bd_microblaze_ps_0_MB_LUT6 is \Using_FPGA.Native_1\ : in STD_LOGIC; I5 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_LUT6 : entity is "MB_LUT6"; end system_bd_microblaze_ps_0_MB_LUT6; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_LUT6 is @@ -13817,6 +13835,8 @@ entity system_bd_microblaze_ps_0_MB_LUT6_2 is EX_ALU_Sel_Logic : in STD_LOGIC; EX_Enable_ALU : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_LUT6_2 : entity is "MB_LUT6_2"; end system_bd_microblaze_ps_0_MB_LUT6_2; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_LUT6_2 is @@ -17332,6 +17352,8 @@ entity system_bd_microblaze_ps_0_MB_MULT_AND is I0 : in STD_LOGIC; \Using_FPGA.Native_I1\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MULT_AND : entity is "MB_MULT_AND"; end system_bd_microblaze_ps_0_MB_MULT_AND; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MULT_AND is @@ -17371,6 +17393,8 @@ entity system_bd_microblaze_ps_0_MB_MUXCY is lopt_7 : in STD_LOGIC; lopt_8 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MUXCY : entity is "MB_MUXCY"; end system_bd_microblaze_ps_0_MB_MUXCY; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MUXCY is @@ -19960,6 +19984,8 @@ entity system_bd_microblaze_ps_0_MB_MUXCY_XORCY is Q : in STD_LOGIC_VECTOR ( 0 to 0 ); LO : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MUXCY_XORCY : entity is "MB_MUXCY_XORCY"; end system_bd_microblaze_ps_0_MB_MUXCY_XORCY; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MUXCY_XORCY is @@ -24167,6 +24193,8 @@ entity system_bd_microblaze_ps_0_MB_MUXF7 is wb_exception : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MUXF7 : entity is "MB_MUXF7"; end system_bd_microblaze_ps_0_MB_MUXF7; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MUXF7 is @@ -27950,6 +27978,8 @@ entity system_bd_microblaze_ps_0_MB_RAM32M is of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 ); \EX_Branch_CMP_Op1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_RAM32M : entity is "MB_RAM32M"; end system_bd_microblaze_ps_0_MB_RAM32M; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_RAM32M is @@ -28917,6 +28947,8 @@ entity system_bd_microblaze_ps_0_MB_SRL16E is Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); Dbg_Clk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_SRL16E : entity is "MB_SRL16E"; end system_bd_microblaze_ps_0_MB_SRL16E; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_SRL16E is @@ -29559,6 +29591,8 @@ entity system_bd_microblaze_ps_0_MB_SRLC16E is Dbg_Clk : in STD_LOGIC; Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_SRLC16E : entity is "MB_SRLC16E"; end system_bd_microblaze_ps_0_MB_SRLC16E; architecture STRUCTURE of system_bd_microblaze_ps_0_MB_SRLC16E is @@ -29895,6 +29929,8 @@ entity system_bd_microblaze_ps_0_Shift_Logic_Module_gti is in0 : in STD_LOGIC; \Using_FPGA.Native\ : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Shift_Logic_Module_gti : entity is "Shift_Logic_Module_gti"; end system_bd_microblaze_ps_0_Shift_Logic_Module_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_Shift_Logic_Module_gti is @@ -29919,6 +29955,8 @@ entity system_bd_microblaze_ps_0_mb_sync_bit is reset_temp : in STD_LOGIC; Clk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_mb_sync_bit : entity is "mb_sync_bit"; end system_bd_microblaze_ps_0_mb_sync_bit; architecture STRUCTURE of system_bd_microblaze_ps_0_mb_sync_bit is @@ -31065,6 +31103,8 @@ entity system_bd_microblaze_ps_0_ALU_Bit is lopt_10 : out STD_LOGIC; lopt_11 : out STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_ALU_Bit : entity is "ALU_Bit"; end system_bd_microblaze_ps_0_ALU_Bit; architecture STRUCTURE of system_bd_microblaze_ps_0_ALU_Bit is @@ -32856,6 +32896,8 @@ entity system_bd_microblaze_ps_0_Data_Flow_Logic is \WB_MEM_Result_reg[0]_0\ : in STD_LOGIC; \WB_MEM_Result_reg[0]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Data_Flow_Logic : entity is "Data_Flow_Logic"; end system_bd_microblaze_ps_0_Data_Flow_Logic; architecture STRUCTURE of system_bd_microblaze_ps_0_Data_Flow_Logic is @@ -33490,6 +33532,8 @@ entity system_bd_microblaze_ps_0_Operand_Select_gti is \EX_Op2_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \EX_Op3_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Operand_Select_gti : entity is "Operand_Select_gti"; end system_bd_microblaze_ps_0_Operand_Select_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_Operand_Select_gti is @@ -35415,6 +35459,8 @@ entity system_bd_microblaze_ps_0_PC_Module_gti is lopt_2 : out STD_LOGIC; lopt_3 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_PC_Module_gti : entity is "PC_Module_gti"; end system_bd_microblaze_ps_0_PC_Module_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_PC_Module_gti is @@ -38318,6 +38364,8 @@ entity system_bd_microblaze_ps_0_PreFetch_Buffer_gti is \EX_Op1_reg[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); ex_MSR : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_PreFetch_Buffer_gti : entity is "PreFetch_Buffer_gti"; end system_bd_microblaze_ps_0_PreFetch_Buffer_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_PreFetch_Buffer_gti is @@ -40839,6 +40887,8 @@ entity system_bd_microblaze_ps_0_Register_File_gti is \EX_Branch_CMP_Op1_reg[28]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \EX_Branch_CMP_Op1_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Register_File_gti : entity is "Register_File_gti"; end system_bd_microblaze_ps_0_Register_File_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_Register_File_gti is @@ -41115,6 +41165,8 @@ entity system_bd_microblaze_ps_0_Zero_Detect_gti is lopt_1 : in STD_LOGIC; lopt_2 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Zero_Detect_gti : entity is "Zero_Detect_gti"; end system_bd_microblaze_ps_0_Zero_Detect_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_Zero_Detect_gti is @@ -41300,6 +41352,8 @@ entity system_bd_microblaze_ps_0_address_hit is Address : in STD_LOGIC_VECTOR ( 0 to 31 ); Dbg_Clk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_address_hit : entity is "address_hit"; end system_bd_microblaze_ps_0_address_hit; architecture STRUCTURE of system_bd_microblaze_ps_0_address_hit is @@ -41547,6 +41601,8 @@ entity system_bd_microblaze_ps_0_carry_and is lopt : in STD_LOGIC; lopt_1 : out STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_carry_and : entity is "carry_and"; end system_bd_microblaze_ps_0_carry_and; architecture STRUCTURE of system_bd_microblaze_ps_0_carry_and is @@ -42095,6 +42151,8 @@ entity system_bd_microblaze_ps_0_carry_or is lopt_7 : in STD_LOGIC; lopt_8 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_carry_or : entity is "carry_or"; end system_bd_microblaze_ps_0_carry_or; architecture STRUCTURE of system_bd_microblaze_ps_0_carry_or is @@ -42178,6 +42236,8 @@ entity system_bd_microblaze_ps_0_exception_registers_gti is \LOCKSTEP_Out_reg[3025]\ : in STD_LOGIC; \LOCKSTEP_Out_reg[3023]\ : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_exception_registers_gti : entity is "exception_registers_gti"; end system_bd_microblaze_ps_0_exception_registers_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_exception_registers_gti is @@ -43466,6 +43526,8 @@ entity system_bd_microblaze_ps_0_jump_logic is lopt_1 : out STD_LOGIC; lopt_2 : out STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_jump_logic : entity is "jump_logic"; end system_bd_microblaze_ps_0_jump_logic; architecture STRUCTURE of system_bd_microblaze_ps_0_jump_logic is @@ -43732,6 +43794,8 @@ entity system_bd_microblaze_ps_0_mb_sync_vec is Dbg_Clk : in STD_LOGIC; \Single_Synchronize.use_async_reset.sync_reg\ : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_mb_sync_vec : entity is "mb_sync_vec"; end system_bd_microblaze_ps_0_mb_sync_vec; architecture STRUCTURE of system_bd_microblaze_ps_0_mb_sync_vec is @@ -43897,6 +43961,8 @@ entity system_bd_microblaze_ps_0_msr_reg_gti is \Using_FPGA.Native_2\ : in STD_LOGIC; wb_piperun : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_msr_reg_gti : entity is "msr_reg_gti"; end system_bd_microblaze_ps_0_msr_reg_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_msr_reg_gti is @@ -44044,6 +44110,8 @@ entity system_bd_microblaze_ps_0_mux_bus is Instr : in STD_LOGIC_VECTOR ( 0 to 31 ); LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 32 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_mux_bus : entity is "mux_bus"; end system_bd_microblaze_ps_0_mux_bus; architecture STRUCTURE of system_bd_microblaze_ps_0_mux_bus is @@ -44243,6 +44311,8 @@ entity system_bd_microblaze_ps_0_ALU is lopt_3 : out STD_LOGIC; lopt_4 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_ALU : entity is "ALU"; end system_bd_microblaze_ps_0_ALU; architecture STRUCTURE of system_bd_microblaze_ps_0_ALU is @@ -45008,6 +45078,8 @@ entity system_bd_microblaze_ps_0_Debug is \Serial_Dbg_Intf.status_reg_reg[22]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); dbg_stop_i : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Debug : entity is "Debug"; end system_bd_microblaze_ps_0_Debug; architecture STRUCTURE of system_bd_microblaze_ps_0_Debug is @@ -49197,6 +49269,8 @@ entity system_bd_microblaze_ps_0_Decode_gti is lopt_1 : out STD_LOGIC; lopt_2 : out STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Decode_gti : entity is "Decode_gti"; end system_bd_microblaze_ps_0_Decode_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_Decode_gti is @@ -54781,6 +54855,8 @@ entity system_bd_microblaze_ps_0_instr_mux is Instr : in STD_LOGIC_VECTOR ( 0 to 31 ); LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 32 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_instr_mux : entity is "instr_mux"; end system_bd_microblaze_ps_0_instr_mux; architecture STRUCTURE of system_bd_microblaze_ps_0_instr_mux is @@ -54982,6 +55058,8 @@ entity system_bd_microblaze_ps_0_Data_Flow_gti is lopt_1 : in STD_LOGIC; lopt_2 : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Data_Flow_gti : entity is "Data_Flow_gti"; end system_bd_microblaze_ps_0_Data_Flow_gti; architecture STRUCTURE of system_bd_microblaze_ps_0_Data_Flow_gti is @@ -55565,6 +55643,8 @@ entity system_bd_microblaze_ps_0_MicroBlaze_GTi is Dbg_TDI : in STD_LOGIC; Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MicroBlaze_GTi : entity is "MicroBlaze_GTi"; end system_bd_microblaze_ps_0_MicroBlaze_GTi; architecture STRUCTURE of system_bd_microblaze_ps_0_MicroBlaze_GTi is @@ -57969,6 +58049,8 @@ entity system_bd_microblaze_ps_0_MicroBlaze_Core is Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 ); Wakeup : in STD_LOGIC_VECTOR ( 0 to 1 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MicroBlaze_Core : entity is "MicroBlaze_Core"; end system_bd_microblaze_ps_0_MicroBlaze_Core; architecture STRUCTURE of system_bd_microblaze_ps_0_MicroBlaze_Core is @@ -58846,6 +58928,8 @@ entity system_bd_microblaze_ps_0_MicroBlaze is attribute C_USE_REORDER_INSTR of system_bd_microblaze_ps_0_MicroBlaze : entity is 1; attribute C_USE_STACK_PROTECTION : integer; attribute C_USE_STACK_PROTECTION of system_bd_microblaze_ps_0_MicroBlaze : entity is 0; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MicroBlaze : entity is "MicroBlaze"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_bd_microblaze_ps_0_MicroBlaze : entity is "yes"; end system_bd_microblaze_ps_0_MicroBlaze; diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.v index e727e58c..84c0da3d 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:31 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_microblaze_ps_0 -prefix -// system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:17 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.v // Design : system_bd_microblaze_ps_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.vhdl index 123bd283..93c458dd 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:31 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_microblaze_ps_0 -prefix --- system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:17 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.vhdl -- Design : system_bd_microblaze_ps_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.dcp index 348c6040..4d0b0cc8 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.xml index a8a25c0f..f491f521 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.xml @@ -385,7 +385,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -403,7 +403,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -423,7 +423,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -446,7 +446,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -466,7 +466,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -484,7 +484,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:51:55 UTC 2023 outputProductCRC @@ -502,7 +502,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:56:15 UTC 2023 outputProductCRC @@ -834,6 +834,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_rst_clk_wiz_25M_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_rst_clk_wiz_25M_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_rst_clk_wiz_25M_0_sim_netlist.v verilogSource @@ -848,18 +860,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_rst_clk_wiz_25M_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_rst_clk_wiz_25M_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - Processor Reset System diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.v index 371c4c7c..2bdffbdc 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:09 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_rst_clk_wiz_25M_0 -prefix -// system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:15 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.v // Design : system_bd_rst_clk_wiz_25M_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,6 +12,64 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_rst_clk_wiz_25M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_rst_clk_wiz_25M_0 + (slowest_sync_clk, + ext_reset_in, + aux_reset_in, + mb_debug_sys_rst, + dcm_locked, + mb_reset, + bus_struct_reset, + peripheral_reset, + interconnect_aresetn, + peripheral_aresetn); + (* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input slowest_sync_clk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst; + input dcm_locked; + (* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn; + + wire aux_reset_in; + wire [0:0]bus_struct_reset; + wire dcm_locked; + wire ext_reset_in; + wire [0:0]interconnect_aresetn; + wire mb_debug_sys_rst; + wire mb_reset; + wire [0:0]peripheral_aresetn; + wire [0:0]peripheral_reset; + wire slowest_sync_clk; + + (* C_AUX_RESET_HIGH = "1'b0" *) + (* C_AUX_RST_WIDTH = "4" *) + (* C_EXT_RESET_HIGH = "1'b0" *) + (* C_EXT_RST_WIDTH = "4" *) + (* C_FAMILY = "kintex7" *) + (* C_NUM_BUS_RST = "1" *) + (* C_NUM_INTERCONNECT_ARESETN = "1" *) + (* C_NUM_PERP_ARESETN = "1" *) + (* C_NUM_PERP_RST = "1" *) + system_bd_rst_clk_wiz_25M_0_proc_sys_reset U0 + (.aux_reset_in(aux_reset_in), + .bus_struct_reset(bus_struct_reset), + .dcm_locked(dcm_locked), + .ext_reset_in(ext_reset_in), + .interconnect_aresetn(interconnect_aresetn), + .mb_debug_sys_rst(mb_debug_sys_rst), + .mb_reset(mb_reset), + .peripheral_aresetn(peripheral_aresetn), + .peripheral_reset(peripheral_reset), + .slowest_sync_clk(slowest_sync_clk)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) module system_bd_rst_clk_wiz_25M_0_cdc_sync (lpf_asr_reg, scndry_out, @@ -193,6 +251,7 @@ module system_bd_rst_clk_wiz_25M_0_cdc_sync_0 .O(lpf_exr_reg)); endmodule +(* ORIG_REF_NAME = "lpf" *) module system_bd_rst_clk_wiz_25M_0_lpf (lpf_int, slowest_sync_clk, @@ -341,6 +400,7 @@ endmodule (* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *) (* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "kintex7" *) (* C_NUM_BUS_RST = "1" *) (* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *) +(* ORIG_REF_NAME = "proc_sys_reset" *) module system_bd_rst_clk_wiz_25M_0_proc_sys_reset (slowest_sync_clk, ext_reset_in, @@ -457,6 +517,7 @@ module system_bd_rst_clk_wiz_25M_0_proc_sys_reset .slowest_sync_clk(slowest_sync_clk)); endmodule +(* ORIG_REF_NAME = "sequence_psr" *) module system_bd_rst_clk_wiz_25M_0_sequence_psr (MB_out, Bsr_out, @@ -697,63 +758,7 @@ module system_bd_rst_clk_wiz_25M_0_sequence_psr .R(lpf_int)); endmodule -(* CHECK_LICENSE_TYPE = "system_bd_rst_clk_wiz_25M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_rst_clk_wiz_25M_0 - (slowest_sync_clk, - ext_reset_in, - aux_reset_in, - mb_debug_sys_rst, - dcm_locked, - mb_reset, - bus_struct_reset, - peripheral_reset, - interconnect_aresetn, - peripheral_aresetn); - (* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input slowest_sync_clk; - (* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in; - (* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in; - (* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst; - input dcm_locked; - (* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset; - (* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset; - (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset; - (* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn; - (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn; - - wire aux_reset_in; - wire [0:0]bus_struct_reset; - wire dcm_locked; - wire ext_reset_in; - wire [0:0]interconnect_aresetn; - wire mb_debug_sys_rst; - wire mb_reset; - wire [0:0]peripheral_aresetn; - wire [0:0]peripheral_reset; - wire slowest_sync_clk; - - (* C_AUX_RESET_HIGH = "1'b0" *) - (* C_AUX_RST_WIDTH = "4" *) - (* C_EXT_RESET_HIGH = "1'b0" *) - (* C_EXT_RST_WIDTH = "4" *) - (* C_FAMILY = "kintex7" *) - (* C_NUM_BUS_RST = "1" *) - (* C_NUM_INTERCONNECT_ARESETN = "1" *) - (* C_NUM_PERP_ARESETN = "1" *) - (* C_NUM_PERP_RST = "1" *) - system_bd_rst_clk_wiz_25M_0_proc_sys_reset U0 - (.aux_reset_in(aux_reset_in), - .bus_struct_reset(bus_struct_reset), - .dcm_locked(dcm_locked), - .ext_reset_in(ext_reset_in), - .interconnect_aresetn(interconnect_aresetn), - .mb_debug_sys_rst(mb_debug_sys_rst), - .mb_reset(mb_reset), - .peripheral_aresetn(peripheral_aresetn), - .peripheral_reset(peripheral_reset), - .slowest_sync_clk(slowest_sync_clk)); -endmodule - +(* ORIG_REF_NAME = "upcnt_n" *) module system_bd_rst_clk_wiz_25M_0_upcnt_n (Q, seq_clr, diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl index 0d6632ad..859f3632 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:09 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_rst_clk_wiz_25M_0 -prefix --- system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:15 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl -- Design : system_bd_rst_clk_wiz_25M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -25,6 +25,8 @@ entity system_bd_rst_clk_wiz_25M_0_cdc_sync is aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_cdc_sync : entity is "cdc_sync"; end system_bd_rst_clk_wiz_25M_0_cdc_sync; architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_cdc_sync is @@ -233,6 +235,8 @@ entity system_bd_rst_clk_wiz_25M_0_upcnt_n is seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_upcnt_n : entity is "upcnt_n"; end system_bd_rst_clk_wiz_25M_0_upcnt_n; architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_upcnt_n is @@ -397,6 +401,8 @@ entity system_bd_rst_clk_wiz_25M_0_lpf is ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_lpf : entity is "lpf"; end system_bd_rst_clk_wiz_25M_0_lpf; architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_lpf is @@ -578,6 +584,8 @@ entity system_bd_rst_clk_wiz_25M_0_sequence_psr is lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_sequence_psr : entity is "sequence_psr"; end system_bd_rst_clk_wiz_25M_0_sequence_psr; architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_sequence_psr is @@ -916,6 +924,8 @@ entity system_bd_rst_clk_wiz_25M_0_proc_sys_reset is attribute C_NUM_PERP_ARESETN of system_bd_rst_clk_wiz_25M_0_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of system_bd_rst_clk_wiz_25M_0_proc_sys_reset : entity is 1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_proc_sys_reset : entity is "proc_sys_reset"; end system_bd_rst_clk_wiz_25M_0_proc_sys_reset; architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_proc_sys_reset is diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.v index 181cbda1..797e2886 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:09 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_rst_clk_wiz_25M_0 -prefix -// system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:15 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.v // Design : system_bd_rst_clk_wiz_25M_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.vhdl index fa007bff..a8cde448 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:09 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_rst_clk_wiz_25M_0 -prefix --- system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:15 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.vhdl -- Design : system_bd_rst_clk_wiz_25M_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.dcp index 3d92f39e..3cb7843d 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xml index 766df6ab..662a8890 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xml @@ -369,7 +369,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -400,7 +400,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -419,7 +419,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -439,7 +439,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -457,7 +457,7 @@ GENtimestamp - Sat Mar 18 16:32:53 UTC 2023 + Wed Mar 22 14:55:52 UTC 2023 outputProductCRC @@ -869,6 +869,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_spi_engine_execution_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_spi_engine_execution_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_spi_engine_execution_0_sim_netlist.v verilogSource @@ -883,18 +895,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_spi_engine_execution_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_spi_engine_execution_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - spi_engine_execution_v1_0 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.v index 617b9c8e..24fce8ef 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_spi_engine_execution_0 -prefix -// system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:52 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.v // Design : system_bd_spi_engine_execution_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,6 +12,100 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_spi_engine_execution_0,spi_engine_execution,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *) +(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_spi_engine_execution_0 + (clk, + resetn, + active, + cmd_ready, + cmd_valid, + cmd, + sdo_data_valid, + sdo_data_ready, + sdo_data, + sdi_data_ready, + sdi_data_valid, + sdi_data, + sync_ready, + sync_valid, + sync, + sclk, + sdo, + sdo_t, + sdi, + cs, + three_wire); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input clk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input resetn; + output active; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *) output cmd_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *) input cmd_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *) input [15:0]cmd; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *) input sdo_data_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *) output sdo_data_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *) input [7:0]sdo_data; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *) input sdi_data_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *) output sdi_data_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *) output [7:0]sdi_data; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *) input sync_ready; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *) output sync_valid; + (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *) output [7:0]sync; + (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *) output sclk; + (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *) output sdo; + (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *) output sdo_t; + (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *) input [0:0]sdi; + (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *) output [2:0]cs; + (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *) output three_wire; + + wire active; + wire clk; + wire [15:0]cmd; + wire cmd_ready; + wire cmd_valid; + wire [2:0]cs; + wire resetn; + wire sclk; + wire [0:0]sdi; + wire [7:0]sdi_data; + wire sdi_data_ready; + wire sdi_data_valid; + wire sdo; + wire [7:0]sdo_data; + wire sdo_data_ready; + wire sdo_data_valid; + wire sdo_t; + wire [7:0]sync; + wire sync_ready; + wire sync_valid; + wire three_wire; + + system_bd_spi_engine_execution_0_spi_engine_execution inst + (.active(active), + .clk(clk), + .cmd({cmd[13:12],cmd[9:0]}), + .cmd_valid(cmd_valid), + .cs(cs), + .idle_reg_0(cmd_ready), + .resetn(resetn), + .sclk(sclk), + .sdi(sdi), + .sdi_data(sdi_data), + .sdi_data_ready(sdi_data_ready), + .sdi_data_valid(sdi_data_valid), + .sdo(sdo), + .sdo_data(sdo_data), + .sdo_data_ready(sdo_data_ready), + .sdo_data_valid(sdo_data_valid), + .sdo_t(sdo_t), + .sync(sync), + .sync_ready(sync_ready), + .sync_valid(sync_valid), + .three_wire(three_wire)); +endmodule + +(* ORIG_REF_NAME = "spi_engine_execution" *) module system_bd_spi_engine_execution_0_spi_engine_execution (idle_reg_0, sync, @@ -2351,99 +2445,6 @@ module system_bd_spi_engine_execution_0_spi_engine_execution .Q(word_length[7]), .R(active_i_1_n_0)); endmodule - -(* CHECK_LICENSE_TYPE = "system_bd_spi_engine_execution_0,spi_engine_execution,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *) -(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_spi_engine_execution_0 - (clk, - resetn, - active, - cmd_ready, - cmd_valid, - cmd, - sdo_data_valid, - sdo_data_ready, - sdo_data, - sdi_data_ready, - sdi_data_valid, - sdi_data, - sync_ready, - sync_valid, - sync, - sclk, - sdo, - sdo_t, - sdi, - cs, - three_wire); - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input clk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input resetn; - output active; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *) output cmd_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *) input cmd_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *) input [15:0]cmd; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *) input sdo_data_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *) output sdo_data_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *) input [7:0]sdo_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *) input sdi_data_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *) output sdi_data_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *) output [7:0]sdi_data; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *) input sync_ready; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *) output sync_valid; - (* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *) output [7:0]sync; - (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *) output sclk; - (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *) output sdo; - (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *) output sdo_t; - (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *) input [0:0]sdi; - (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *) output [2:0]cs; - (* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *) output three_wire; - - wire active; - wire clk; - wire [15:0]cmd; - wire cmd_ready; - wire cmd_valid; - wire [2:0]cs; - wire resetn; - wire sclk; - wire [0:0]sdi; - wire [7:0]sdi_data; - wire sdi_data_ready; - wire sdi_data_valid; - wire sdo; - wire [7:0]sdo_data; - wire sdo_data_ready; - wire sdo_data_valid; - wire sdo_t; - wire [7:0]sync; - wire sync_ready; - wire sync_valid; - wire three_wire; - - system_bd_spi_engine_execution_0_spi_engine_execution inst - (.active(active), - .clk(clk), - .cmd({cmd[13:12],cmd[9:0]}), - .cmd_valid(cmd_valid), - .cs(cs), - .idle_reg_0(cmd_ready), - .resetn(resetn), - .sclk(sclk), - .sdi(sdi), - .sdi_data(sdi_data), - .sdi_data_ready(sdi_data_ready), - .sdi_data_valid(sdi_data_valid), - .sdo(sdo), - .sdo_data(sdo_data), - .sdo_data_ready(sdo_data_ready), - .sdo_data_valid(sdo_data_valid), - .sdo_t(sdo_t), - .sync(sync), - .sync_ready(sync_ready), - .sync_valid(sync_valid), - .three_wire(three_wire)); -endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.vhdl index 007c0c3c..81bd8cd5 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_spi_engine_execution_0 -prefix --- system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:52 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.vhdl -- Design : system_bd_spi_engine_execution_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -38,6 +38,8 @@ entity system_bd_spi_engine_execution_0_spi_engine_execution is sdi_data_ready : in STD_LOGIC; sdo_data : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_spi_engine_execution_0_spi_engine_execution : entity is "spi_engine_execution"; end system_bd_spi_engine_execution_0_spi_engine_execution; architecture STRUCTURE of system_bd_spi_engine_execution_0_spi_engine_execution is diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v index cd615d1b..1d49ea38 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:10 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_spi_engine_execution_0 -prefix -// system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:55:52 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v // Design : system_bd_spi_engine_execution_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl index 6bb3e735..d016bb74 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:10 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_spi_engine_execution_0 -prefix --- system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:55:52 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl -- Design : system_bd_spi_engine_execution_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.dcp b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.dcp index cbe1c7cc..fa917405 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.dcp and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.dcp differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xml index 994e011c..6f5707ef 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xml @@ -26554,7 +26554,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -26572,7 +26572,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -26592,7 +26592,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -26627,7 +26627,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -26647,7 +26647,7 @@ GENtimestamp - Sat Mar 18 16:32:52 UTC 2023 + Wed Mar 22 14:51:51 UTC 2023 outputProductCRC @@ -26665,7 +26665,7 @@ GENtimestamp - Sat Mar 18 16:32:54 UTC 2023 + Wed Mar 22 14:56:06 UTC 2023 outputProductCRC @@ -29180,6 +29180,18 @@ USED_IN_synthesis xil_defaultlib + + system_bd_xbar_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + system_bd_xbar_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + system_bd_xbar_0_sim_netlist.v verilogSource @@ -29194,18 +29206,6 @@ USED_IN_single_language xil_defaultlib - - system_bd_xbar_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - system_bd_xbar_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - The AXI Crossbar IP provides the infrastructure to connect multiple AXI4/AXI3/AXI4-Lite masters and slaves. diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.v index 978068d2..7e4bfda3 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:17 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -rename_top system_bd_xbar_0 -prefix -// system_bd_xbar_0_ system_bd_xbar_0_sim_netlist.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:06 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode funcsim +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.v // Design : system_bd_xbar_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -12,6 +12,300 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps +(* CHECK_LICENSE_TYPE = "system_bd_xbar_0,axi_crossbar_v2_1_20_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_20_axi_crossbar,Vivado 2019.1.3" *) +(* NotValidForBitStream *) +module system_bd_xbar_0 + (aclk, + aresetn, + s_axi_awaddr, + s_axi_awprot, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arprot, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + m_axi_awaddr, + m_axi_awprot, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wvalid, + m_axi_wready, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_araddr, + m_axi_arprot, + m_axi_arvalid, + m_axi_arready, + m_axi_rdata, + m_axi_rresp, + m_axi_rvalid, + m_axi_rready); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [2:0]m_axi_rready; + + wire aclk; + wire aresetn; + wire [95:0]m_axi_araddr; + wire [8:0]m_axi_arprot; + wire [2:0]m_axi_arready; + wire [2:0]m_axi_arvalid; + wire [95:0]m_axi_awaddr; + wire [8:0]m_axi_awprot; + wire [2:0]m_axi_awready; + wire [2:0]m_axi_awvalid; + wire [2:0]m_axi_bready; + wire [5:0]m_axi_bresp; + wire [2:0]m_axi_bvalid; + wire [95:0]m_axi_rdata; + wire [2:0]m_axi_rready; + wire [5:0]m_axi_rresp; + wire [2:0]m_axi_rvalid; + wire [95:0]m_axi_wdata; + wire [2:0]m_axi_wready; + wire [11:0]m_axi_wstrb; + wire [2:0]m_axi_wvalid; + wire [31:0]s_axi_araddr; + wire [2:0]s_axi_arprot; + wire [0:0]s_axi_arready; + wire [0:0]s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [2:0]s_axi_awprot; + wire [0:0]s_axi_awready; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_bready; + wire [1:0]s_axi_bresp; + wire [0:0]s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire [0:0]s_axi_rready; + wire [1:0]s_axi_rresp; + wire [0:0]s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire [0:0]s_axi_wready; + wire [3:0]s_axi_wstrb; + wire [0:0]s_axi_wvalid; + wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED; + wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED; + wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED; + wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED; + wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED; + wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED; + wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED; + wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED; + wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED; + + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "32" *) + (* C_AXI_ID_WIDTH = "1" *) + (* C_AXI_PROTOCOL = "2" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_CONNECTIVITY_MODE = "0" *) + (* C_DEBUG = "1" *) + (* C_FAMILY = "kintex7" *) + (* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000" *) + (* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000100101000000000000000000000" *) + (* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_NUM_ADDR_RANGES = "1" *) + (* C_NUM_MASTER_SLOTS = "3" *) + (* C_NUM_SLAVE_SLOTS = "1" *) + (* C_R_REGISTER = "1" *) + (* C_S_AXI_ARB_PRIORITY = "0" *) + (* C_S_AXI_BASE_ID = "0" *) + (* C_S_AXI_READ_ACCEPTANCE = "1" *) + (* C_S_AXI_SINGLE_THREAD = "1" *) + (* C_S_AXI_THREAD_ID_WIDTH = "0" *) + (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) + (* DowngradeIPIdentifiedWarnings = "yes" *) + (* P_ADDR_DECODE = "1" *) + (* P_AXI3 = "1" *) + (* P_AXI4 = "0" *) + (* P_AXILITE = "2" *) + (* P_AXILITE_SIZE = "3'b010" *) + (* P_FAMILY = "kintex7" *) + (* P_INCR = "2'b01" *) + (* P_LEN = "8" *) + (* P_LOCK = "1" *) + (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* P_M_AXI_SUPPORTS_READ = "3'b111" *) + (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) + (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) + (* P_RANGE_CHECK = "1" *) + (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* P_S_AXI_SUPPORTS_READ = "1'b1" *) + (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) + system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar inst + (.aclk(aclk), + .aresetn(aresetn), + .m_axi_araddr(m_axi_araddr), + .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]), + .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]), + .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]), + .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]), + .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]), + .m_axi_arprot(m_axi_arprot), + .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]), + .m_axi_arready(m_axi_arready), + .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]), + .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]), + .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]), + .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]), + .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]), + .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]), + .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]), + .m_axi_awprot(m_axi_awprot), + .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]), + .m_axi_awready(m_axi_awready), + .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]), + .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]), + .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bid({1'b0,1'b0,1'b0}), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser({1'b0,1'b0,1'b0}), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rid({1'b0,1'b0,1'b0}), + .m_axi_rlast({1'b1,1'b1,1'b1}), + .m_axi_rready(m_axi_rready), + .m_axi_rresp(m_axi_rresp), + .m_axi_ruser({1'b0,1'b0,1'b0}), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]), + .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]), + .m_axi_wvalid(m_axi_wvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid(1'b0), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlock(1'b0), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(s_axi_arready), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid(1'b0), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock(1'b0), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(s_axi_awready), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]), + .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wid(1'b0), + .s_axi_wlast(1'b1), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wuser(1'b0), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_addr_arbiter_sasd" *) module system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd (aa_grant_any, m_valid_i, @@ -1081,13 +1375,13 @@ endmodule (* C_NUM_MASTER_SLOTS = "3" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *) (* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *) (* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *) -(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *) -(* P_FAMILY = "kintex7" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *) -(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "3'b111" *) -(* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *) -(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *) -(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_20_axi_crossbar" *) (* P_ADDR_DECODE = "1" *) +(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *) +(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "kintex7" *) (* P_INCR = "2'b01" *) +(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* P_M_AXI_SUPPORTS_READ = "3'b111" *) (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) +(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) +(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) module system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar (aclk, aresetn, @@ -1567,6 +1861,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar .s_axi_wvalid(s_axi_wvalid)); endmodule +(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_crossbar_sasd" *) module system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd (Q, \m_payload_i_reg[34] , @@ -1886,6 +2181,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd .s_axi_wvalid_0_sp_1(splitter_aw_n_0)); endmodule +(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_decerr_slave" *) module system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave (\m_ready_d_reg[2] , m_axi_awready_2_sp_1, @@ -2105,6 +2401,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave .O(m_axi_wready_1_sn_1)); endmodule +(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_splitter" *) module system_bd_xbar_0_axi_crossbar_v2_1_20_splitter (s_axi_wvalid_0_sp_1, m_ready_d, @@ -2272,6 +2569,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_splitter__parameterized0 .R(1'b0)); endmodule +(* ORIG_REF_NAME = "axi_register_slice_v2_1_19_axic_register_slice" *) module system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice (sr_rvalid, aa_rready, @@ -3495,299 +3793,6 @@ module system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice .Q(\skid_buffer_reg_n_0_[9] ), .R(1'b0)); endmodule - -(* CHECK_LICENSE_TYPE = "system_bd_xbar_0,axi_crossbar_v2_1_20_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_20_axi_crossbar,Vivado 2019.1.3" *) -(* NotValidForBitStream *) -module system_bd_xbar_0 - (aclk, - aresetn, - s_axi_awaddr, - s_axi_awprot, - s_axi_awvalid, - s_axi_awready, - s_axi_wdata, - s_axi_wstrb, - s_axi_wvalid, - s_axi_wready, - s_axi_bresp, - s_axi_bvalid, - s_axi_bready, - s_axi_araddr, - s_axi_arprot, - s_axi_arvalid, - s_axi_arready, - s_axi_rdata, - s_axi_rresp, - s_axi_rvalid, - s_axi_rready, - m_axi_awaddr, - m_axi_awprot, - m_axi_awvalid, - m_axi_awready, - m_axi_wdata, - m_axi_wstrb, - m_axi_wvalid, - m_axi_wready, - m_axi_bresp, - m_axi_bvalid, - m_axi_bready, - m_axi_araddr, - m_axi_arprot, - m_axi_arvalid, - m_axi_arready, - m_axi_rdata, - m_axi_rresp, - m_axi_rvalid, - m_axi_rready); - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [2:0]m_axi_rready; - - wire aclk; - wire aresetn; - wire [95:0]m_axi_araddr; - wire [8:0]m_axi_arprot; - wire [2:0]m_axi_arready; - wire [2:0]m_axi_arvalid; - wire [95:0]m_axi_awaddr; - wire [8:0]m_axi_awprot; - wire [2:0]m_axi_awready; - wire [2:0]m_axi_awvalid; - wire [2:0]m_axi_bready; - wire [5:0]m_axi_bresp; - wire [2:0]m_axi_bvalid; - wire [95:0]m_axi_rdata; - wire [2:0]m_axi_rready; - wire [5:0]m_axi_rresp; - wire [2:0]m_axi_rvalid; - wire [95:0]m_axi_wdata; - wire [2:0]m_axi_wready; - wire [11:0]m_axi_wstrb; - wire [2:0]m_axi_wvalid; - wire [31:0]s_axi_araddr; - wire [2:0]s_axi_arprot; - wire [0:0]s_axi_arready; - wire [0:0]s_axi_arvalid; - wire [31:0]s_axi_awaddr; - wire [2:0]s_axi_awprot; - wire [0:0]s_axi_awready; - wire [0:0]s_axi_awvalid; - wire [0:0]s_axi_bready; - wire [1:0]s_axi_bresp; - wire [0:0]s_axi_bvalid; - wire [31:0]s_axi_rdata; - wire [0:0]s_axi_rready; - wire [1:0]s_axi_rresp; - wire [0:0]s_axi_rvalid; - wire [31:0]s_axi_wdata; - wire [0:0]s_axi_wready; - wire [3:0]s_axi_wstrb; - wire [0:0]s_axi_wvalid; - wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED; - wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED; - wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED; - wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED; - wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED; - wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED; - wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED; - wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED; - wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED; - wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED; - wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED; - wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED; - wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED; - wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED; - wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED; - - (* C_AXI_ADDR_WIDTH = "32" *) - (* C_AXI_ARUSER_WIDTH = "1" *) - (* C_AXI_AWUSER_WIDTH = "1" *) - (* C_AXI_BUSER_WIDTH = "1" *) - (* C_AXI_DATA_WIDTH = "32" *) - (* C_AXI_ID_WIDTH = "1" *) - (* C_AXI_PROTOCOL = "2" *) - (* C_AXI_RUSER_WIDTH = "1" *) - (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) - (* C_AXI_WUSER_WIDTH = "1" *) - (* C_CONNECTIVITY_MODE = "0" *) - (* C_DEBUG = "1" *) - (* C_FAMILY = "kintex7" *) - (* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000" *) - (* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000100101000000000000000000000" *) - (* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) - (* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) - (* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) - (* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) - (* C_NUM_ADDR_RANGES = "1" *) - (* C_NUM_MASTER_SLOTS = "3" *) - (* C_NUM_SLAVE_SLOTS = "1" *) - (* C_R_REGISTER = "1" *) - (* C_S_AXI_ARB_PRIORITY = "0" *) - (* C_S_AXI_BASE_ID = "0" *) - (* C_S_AXI_READ_ACCEPTANCE = "1" *) - (* C_S_AXI_SINGLE_THREAD = "1" *) - (* C_S_AXI_THREAD_ID_WIDTH = "0" *) - (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) - (* DowngradeIPIdentifiedWarnings = "yes" *) - (* P_ADDR_DECODE = "1" *) - (* P_AXI3 = "1" *) - (* P_AXI4 = "0" *) - (* P_AXILITE = "2" *) - (* P_AXILITE_SIZE = "3'b010" *) - (* P_FAMILY = "kintex7" *) - (* P_INCR = "2'b01" *) - (* P_LEN = "8" *) - (* P_LOCK = "1" *) - (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* P_M_AXI_SUPPORTS_READ = "3'b111" *) - (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) - (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) - (* P_RANGE_CHECK = "1" *) - (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) - (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) - (* P_S_AXI_SUPPORTS_READ = "1'b1" *) - (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) - system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar inst - (.aclk(aclk), - .aresetn(aresetn), - .m_axi_araddr(m_axi_araddr), - .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]), - .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]), - .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]), - .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]), - .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]), - .m_axi_arprot(m_axi_arprot), - .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]), - .m_axi_arready(m_axi_arready), - .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]), - .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]), - .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_awaddr(m_axi_awaddr), - .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]), - .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]), - .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]), - .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]), - .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]), - .m_axi_awprot(m_axi_awprot), - .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]), - .m_axi_awready(m_axi_awready), - .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]), - .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]), - .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]), - .m_axi_awvalid(m_axi_awvalid), - .m_axi_bid({1'b0,1'b0,1'b0}), - .m_axi_bready(m_axi_bready), - .m_axi_bresp(m_axi_bresp), - .m_axi_buser({1'b0,1'b0,1'b0}), - .m_axi_bvalid(m_axi_bvalid), - .m_axi_rdata(m_axi_rdata), - .m_axi_rid({1'b0,1'b0,1'b0}), - .m_axi_rlast({1'b1,1'b1,1'b1}), - .m_axi_rready(m_axi_rready), - .m_axi_rresp(m_axi_rresp), - .m_axi_ruser({1'b0,1'b0,1'b0}), - .m_axi_rvalid(m_axi_rvalid), - .m_axi_wdata(m_axi_wdata), - .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]), - .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]), - .m_axi_wready(m_axi_wready), - .m_axi_wstrb(m_axi_wstrb), - .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]), - .m_axi_wvalid(m_axi_wvalid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arburst({1'b0,1'b0}), - .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arid(1'b0), - .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_arlock(1'b0), - .s_axi_arprot(s_axi_arprot), - .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), - .s_axi_arready(s_axi_arready), - .s_axi_arsize({1'b0,1'b0,1'b0}), - .s_axi_aruser(1'b0), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awburst({1'b0,1'b0}), - .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awid(1'b0), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlock(1'b0), - .s_axi_awprot(s_axi_awprot), - .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(s_axi_awready), - .s_axi_awsize({1'b0,1'b0,1'b0}), - .s_axi_awuser(1'b0), - .s_axi_awvalid(s_axi_awvalid), - .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]), - .s_axi_bready(s_axi_bready), - .s_axi_bresp(s_axi_bresp), - .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]), - .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata(s_axi_rdata), - .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]), - .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]), - .s_axi_rready(s_axi_rready), - .s_axi_rresp(s_axi_rresp), - .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]), - .s_axi_rvalid(s_axi_rvalid), - .s_axi_wdata(s_axi_wdata), - .s_axi_wid(1'b0), - .s_axi_wlast(1'b1), - .s_axi_wready(s_axi_wready), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wuser(1'b0), - .s_axi_wvalid(s_axi_wvalid)); -endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.vhdl index fa36e0bd..bfde54c0 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:17 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode funcsim -rename_top system_bd_xbar_0 -prefix --- system_bd_xbar_0_ system_bd_xbar_0_sim_netlist.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:06 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode funcsim +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.vhdl -- Design : system_bd_xbar_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -66,6 +66,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd is s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_20_addr_arbiter_sasd"; end system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd; architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd is @@ -1338,6 +1340,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave is \gen_axilite.s_axi_bvalid_i_reg_2\ : in STD_LOGIC; aa_rready : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave : entity is "axi_crossbar_v2_1_20_decerr_slave"; end system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave; architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave is @@ -1552,6 +1556,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_splitter is \m_ready_d_reg[2]_1\ : in STD_LOGIC; aclk : in STD_LOGIC ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_splitter : entity is "axi_crossbar_v2_1_20_splitter"; end system_bd_xbar_0_axi_crossbar_v2_1_20_splitter; architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_splitter is @@ -1747,6 +1753,8 @@ entity system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice is SR : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice : entity is "axi_register_slice_v2_1_19_axic_register_slice"; end system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice; architecture STRUCTURE of system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice is @@ -3325,6 +3333,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd is s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd : entity is "axi_crossbar_v2_1_20_crossbar_sasd"; end system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd; architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd is @@ -3748,6 +3758,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar is attribute C_S_AXI_WRITE_ACCEPTANCE of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is 1; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is "yes"; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is "axi_crossbar_v2_1_20_axi_crossbar"; attribute P_ADDR_DECODE : integer; attribute P_ADDR_DECODE of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is 1; attribute P_AXI3 : integer; diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.v index 11d9e8f0..b5b41fba 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -// Date : Sat Mar 18 23:57:17 2023 -// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -rename_top system_bd_xbar_0 -prefix -// system_bd_xbar_0_ system_bd_xbar_0_stub.v +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Mar 22 22:56:06 2023 +// Host : localhost.localdomain running 64-bit unknown +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.v // Design : system_bd_xbar_0 // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.vhdl b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.vhdl index 913bca78..020d2c9d 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.vhdl +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 --- Date : Sat Mar 18 23:57:17 2023 --- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) --- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_xbar_0 -prefix --- system_bd_xbar_0_ system_bd_xbar_0_stub.vhdl +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Mar 22 22:56:06 2023 +-- Host : localhost.localdomain running 64-bit unknown +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.vhdl -- Design : system_bd_xbar_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1cb1/axi_spi_engine.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1cb1/axi_spi_engine.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/simulation/fifo_generator_vlog_beh.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/simulation/fifo_generator_vlog_beh.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v old mode 100644 new mode 100755 index 2cca3d2a..26ef1e9d --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v @@ -102,303 +102,303 @@ endmodule // tdm_sample `default_nettype wire -// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved. -// -- -// -- This file contains confidential and proprietary information -// -- of Xilinx, Inc. and is protected under U.S. and -// -- international copyright and other intellectual property -// -- laws. -// -- -// -- DISCLAIMER -// -- This disclaimer is not a license and does not grant any -// -- rights to the materials distributed herewith. Except as -// -- otherwise provided in a valid license issued to you by -// -- Xilinx, and to the maximum extent permitted by applicable -// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// -- (2) Xilinx shall not be liable (whether in contract or tort, -// -- including negligence, or under any other theory of -// -- liability) for any loss or damage of any kind or nature -// -- related to, arising under or in connection with these -// -- materials, including for any direct, or any indirect, -// -- special, incidental, or consequential loss or damage -// -- (including loss of data, profits, goodwill, or any type of -// -- loss or damage suffered as a result of any action brought -// -- by a third party) even if such damage or loss was -// -- reasonably foreseeable or Xilinx had been advised of the -// -- possibility of the same. -// -- -// -- CRITICAL APPLICATIONS -// -- Xilinx products are not designed or intended to be fail- -// -- safe, or for use in any application requiring fail-safe -// -- performance, such as life-support or safety devices or -// -- systems, Class III medical devices, nuclear facilities, -// -- applications related to the deployment of airbags, or any -// -- other applications that could lead to death, personal -// -- injury, or severe property or environmental damage -// -- (individually and collectively, "Critical -// -- Applications"). Customer assumes the sole risk and -// -- liability of any use of Xilinx products in Critical -// -- Applications, subject only to applicable laws and -// -- regulations governing limitations on product liability. -// -- -// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// -- PART OF THIS FILE AT ALL TIMES. -//----------------------------------------------------------------------------- - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -(* autopipeline_module="yes" *) -module axi_register_slice_v2_1_19_auto_slr # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ARESETN, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - wire handshake_pipe; - wire ready_pipe; - wire [C_DATA_WIDTH-1:0] payload_pipe; - (* keep="true" *) reg s_aclear = 1'b0; - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0; - (* autopipeline_group="resp" *) reg s_areset_resp = 1'b0; - (* keep="true" *) reg s_areset_resp2 = 1'b0; - (* keep="true" *) reg m_aclear = 1'b0; - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0; - (* autopipeline_group="resp" *) reg m_areset_resp = 1'b0; - (* keep="true" *) reg m_areset_resp2 = 1'b0; - - // Global Reset pipelining - - always @(posedge ACLK) begin - s_aclear <= ~ARESETN; - s_areset_fwd <= ~ARESETN; - s_areset_resp <= s_areset_fwd; // Auto-pipeline - s_areset_resp2 <= s_areset_resp; // Auto-pipeline - end - - always @(posedge ACLK) begin - m_aclear <= ~ARESETN; - m_areset_fwd <= ~ARESETN; - m_areset_resp <= m_areset_fwd; // Auto-pipeline - m_areset_resp2 <= m_areset_resp; // Auto-pipeline - end - - // Source-side submodule - - axi_register_slice_v2_1_19_auto_src # - ( - .C_DATA_WIDTH (C_DATA_WIDTH) - ) - slr_auto_src - ( - .ACLK (ACLK), - .s_aclear (s_aclear), - .s_areset_resp2 (s_areset_resp2), - .S_VALID (S_VALID), - .S_READY (S_READY), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .ready_pipe (ready_pipe), - .handshake_pipe (handshake_pipe), - .payload_pipe (payload_pipe) - ); - - // Destination-side submodule - - axi_register_slice_v2_1_19_auto_dest # - ( - .C_DATA_WIDTH (C_DATA_WIDTH) - ) - slr_auto_dest - ( - .ACLK (ACLK), - .m_aclear (m_aclear), - .m_areset_resp2 (m_areset_resp2), - .M_READY (M_READY), - .M_VALID (M_VALID), - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .handshake_pipe (handshake_pipe), - .ready_pipe (ready_pipe), - .payload_pipe (payload_pipe) - ); - -endmodule // auto_slr - -module axi_register_slice_v2_1_19_auto_src # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - input wire ACLK, - input wire s_aclear, - input wire s_areset_resp2, - input wire S_VALID, - input wire ready_pipe, - output wire S_READY, - output wire handshake_pipe, - output wire [C_DATA_WIDTH-1:0] payload_pipe, - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA - ); - - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r; - (* keep="true" *) reg s_areset_resp3 = 1'b0; - wire s_aresetn_d; - wire s_aresetn_q; - wire s_handshake_d; - wire s_ready_i; - - assign S_READY = s_ready_i & s_aresetn_q; - assign s_aresetn_d = (~s_areset_resp2 & s_areset_resp3) | s_aresetn_q; - assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q; - assign payload_pipe = payload_pipe_r; - - always @(posedge ACLK) begin - s_areset_resp3 <= s_areset_resp2; - end - - always @(posedge ACLK) begin - payload_pipe_r <= S_PAYLOAD_DATA; - end - - // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2. - FDCE #( - .INIT(1'b0) - ) reset_asyncclear ( - .Q (s_aresetn_q), - .C (ACLK), - .CE (1'b1), - .CLR (s_aclear), - .D (s_aresetn_d) - ); - - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) - FDCE #( - .INIT(1'b0) - ) handshake_asyncclear ( - .Q (handshake_pipe), - .C (ACLK), - .CE (1'b1), - .CLR (s_aclear), - .D (s_handshake_d) - ); - - FDCE #( - .INIT(1'b0) - ) ready_asyncclear ( - .Q (s_ready_i), - .C (ACLK), - .CE (1'b1), - .CLR (s_aclear), - .D (ready_pipe) - ); - -endmodule // auto_src - -module axi_register_slice_v2_1_19_auto_dest # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - input wire ACLK, - input wire m_aclear, - input wire m_areset_resp2, - input wire M_READY, - input wire handshake_pipe, - output wire ready_pipe, - output wire M_VALID, - input wire [C_DATA_WIDTH-1:0] payload_pipe, - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA - ); - - (* keep="true" *) reg m_areset_resp3 = 1'b0; - wire m_aresetn_d; - wire m_aresetn_q; - wire m_valid_i; - wire pop; - wire m_ready_d; - wire m_handshake_q; - reg [C_DATA_WIDTH-1:0] m_payload_q; - - assign M_VALID = m_valid_i; - assign m_aresetn_d = (~m_areset_resp2 & m_areset_resp3) | m_aresetn_q; - assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q; - assign pop = M_READY & m_valid_i; - - always @(posedge ACLK) begin - m_areset_resp3 <= m_areset_resp2; - end - - always @(posedge ACLK) begin - m_payload_q <= payload_pipe; - end - - // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2. - FDCE #( - .INIT(1'b0) - ) reset_asyncclear ( - .Q (m_aresetn_q), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (m_aresetn_d) - ); - - FDCE #( - .INIT(1'b0) - ) handshake_asyncclear ( - .Q (m_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (handshake_pipe) - ); - - (* autopipeline_group="resp" *) - FDCE #( - .INIT(1'b0) - ) ready_asyncclear ( - .Q (ready_pipe), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (m_ready_d) - ); - - axi_register_slice_v2_1_19_axic_reg_srl_fifo # - ( - .C_FIFO_WIDTH (C_DATA_WIDTH), - .C_FIFO_SIZE (5) - ) - srl_fifo - ( - .aclk (ACLK), - .areset (~m_aresetn_q), - .aclear (m_aclear), - .s_mesg (m_payload_q), - .s_valid (m_handshake_q), - .m_mesg (M_PAYLOAD_DATA), - .m_valid (m_valid_i), - .m_ready (pop) - ); - -endmodule // auto_dest - +// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- + +`timescale 1ps/1ps +(* DowngradeIPIdentifiedWarnings="yes" *) +(* autopipeline_module="yes" *) +module axi_register_slice_v2_1_19_auto_slr # + ( + parameter integer C_DATA_WIDTH = 32 + ) + ( + // System Signals + input wire ACLK, + input wire ARESETN, + + // Slave side + input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, + input wire S_VALID, + output wire S_READY, + + // Master side + output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, + output wire M_VALID, + input wire M_READY + ); + + wire handshake_pipe; + wire ready_pipe; + wire [C_DATA_WIDTH-1:0] payload_pipe; + (* keep="true" *) reg s_aclear = 1'b0; + (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0; + (* autopipeline_group="resp" *) reg s_areset_resp = 1'b0; + (* keep="true" *) reg s_areset_resp2 = 1'b0; + (* keep="true" *) reg m_aclear = 1'b0; + (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0; + (* autopipeline_group="resp" *) reg m_areset_resp = 1'b0; + (* keep="true" *) reg m_areset_resp2 = 1'b0; + + // Global Reset pipelining + + always @(posedge ACLK) begin + s_aclear <= ~ARESETN; + s_areset_fwd <= ~ARESETN; + s_areset_resp <= s_areset_fwd; // Auto-pipeline + s_areset_resp2 <= s_areset_resp; // Auto-pipeline + end + + always @(posedge ACLK) begin + m_aclear <= ~ARESETN; + m_areset_fwd <= ~ARESETN; + m_areset_resp <= m_areset_fwd; // Auto-pipeline + m_areset_resp2 <= m_areset_resp; // Auto-pipeline + end + + // Source-side submodule + + axi_register_slice_v2_1_19_auto_src # + ( + .C_DATA_WIDTH (C_DATA_WIDTH) + ) + slr_auto_src + ( + .ACLK (ACLK), + .s_aclear (s_aclear), + .s_areset_resp2 (s_areset_resp2), + .S_VALID (S_VALID), + .S_READY (S_READY), + .S_PAYLOAD_DATA (S_PAYLOAD_DATA), + .ready_pipe (ready_pipe), + .handshake_pipe (handshake_pipe), + .payload_pipe (payload_pipe) + ); + + // Destination-side submodule + + axi_register_slice_v2_1_19_auto_dest # + ( + .C_DATA_WIDTH (C_DATA_WIDTH) + ) + slr_auto_dest + ( + .ACLK (ACLK), + .m_aclear (m_aclear), + .m_areset_resp2 (m_areset_resp2), + .M_READY (M_READY), + .M_VALID (M_VALID), + .M_PAYLOAD_DATA (M_PAYLOAD_DATA), + .handshake_pipe (handshake_pipe), + .ready_pipe (ready_pipe), + .payload_pipe (payload_pipe) + ); + +endmodule // auto_slr + +module axi_register_slice_v2_1_19_auto_src # + ( + parameter integer C_DATA_WIDTH = 32 + ) + ( + input wire ACLK, + input wire s_aclear, + input wire s_areset_resp2, + input wire S_VALID, + input wire ready_pipe, + output wire S_READY, + output wire handshake_pipe, + output wire [C_DATA_WIDTH-1:0] payload_pipe, + input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA + ); + + (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r; + (* keep="true" *) reg s_areset_resp3 = 1'b0; + wire s_aresetn_d; + wire s_aresetn_q; + wire s_handshake_d; + wire s_ready_i; + + assign S_READY = s_ready_i & s_aresetn_q; + assign s_aresetn_d = (~s_areset_resp2 & s_areset_resp3) | s_aresetn_q; + assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q; + assign payload_pipe = payload_pipe_r; + + always @(posedge ACLK) begin + s_areset_resp3 <= s_areset_resp2; + end + + always @(posedge ACLK) begin + payload_pipe_r <= S_PAYLOAD_DATA; + end + + // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2. + FDCE #( + .INIT(1'b0) + ) reset_asyncclear ( + .Q (s_aresetn_q), + .C (ACLK), + .CE (1'b1), + .CLR (s_aclear), + .D (s_aresetn_d) + ); + + (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) + FDCE #( + .INIT(1'b0) + ) handshake_asyncclear ( + .Q (handshake_pipe), + .C (ACLK), + .CE (1'b1), + .CLR (s_aclear), + .D (s_handshake_d) + ); + + FDCE #( + .INIT(1'b0) + ) ready_asyncclear ( + .Q (s_ready_i), + .C (ACLK), + .CE (1'b1), + .CLR (s_aclear), + .D (ready_pipe) + ); + +endmodule // auto_src + +module axi_register_slice_v2_1_19_auto_dest # + ( + parameter integer C_DATA_WIDTH = 32 + ) + ( + input wire ACLK, + input wire m_aclear, + input wire m_areset_resp2, + input wire M_READY, + input wire handshake_pipe, + output wire ready_pipe, + output wire M_VALID, + input wire [C_DATA_WIDTH-1:0] payload_pipe, + output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA + ); + + (* keep="true" *) reg m_areset_resp3 = 1'b0; + wire m_aresetn_d; + wire m_aresetn_q; + wire m_valid_i; + wire pop; + wire m_ready_d; + wire m_handshake_q; + reg [C_DATA_WIDTH-1:0] m_payload_q; + + assign M_VALID = m_valid_i; + assign m_aresetn_d = (~m_areset_resp2 & m_areset_resp3) | m_aresetn_q; + assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q; + assign pop = M_READY & m_valid_i; + + always @(posedge ACLK) begin + m_areset_resp3 <= m_areset_resp2; + end + + always @(posedge ACLK) begin + m_payload_q <= payload_pipe; + end + + // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2. + FDCE #( + .INIT(1'b0) + ) reset_asyncclear ( + .Q (m_aresetn_q), + .C (ACLK), + .CE (1'b1), + .CLR (m_aclear), + .D (m_aresetn_d) + ); + + FDCE #( + .INIT(1'b0) + ) handshake_asyncclear ( + .Q (m_handshake_q), + .C (ACLK), + .CE (1'b1), + .CLR (m_aclear), + .D (handshake_pipe) + ); + + (* autopipeline_group="resp" *) + FDCE #( + .INIT(1'b0) + ) ready_asyncclear ( + .Q (ready_pipe), + .C (ACLK), + .CE (1'b1), + .CLR (m_aclear), + .D (m_ready_d) + ); + + axi_register_slice_v2_1_19_axic_reg_srl_fifo # + ( + .C_FIFO_WIDTH (C_DATA_WIDTH), + .C_FIFO_SIZE (5) + ) + srl_fifo + ( + .aclk (ACLK), + .areset (~m_aresetn_q), + .aclear (m_aclear), + .s_mesg (m_payload_q), + .s_valid (m_handshake_q), + .m_mesg (M_PAYLOAD_DATA), + .m_valid (m_valid_i), + .m_ready (pop) + ); + +endmodule // auto_dest + // -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved. diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/550e/hdl/mdm_v3_2_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/550e/hdl/mdm_v3_2_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/5b9c/hdl/axi_data_fifo_v2_1_vl_rfs.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/5b9c/hdl/axi_data_fifo_v2_1_vl_rfs.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/6335/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/6335/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/78eb/hdl/lmb_v10_v3_0_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/78eb/hdl/lmb_v10_v3_0_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/802c/spi_engine_execution.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/802c/spi_engine_execution.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c001/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c001/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c001/simulation/blk_mem_gen_v8_4.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c001/simulation/blk_mem_gen_v8_4.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_mmcm.vh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_mmcm.vh old mode 100644 new mode 100755 index 652d7d11..481cd2d0 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_mmcm.vh +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_mmcm.vh @@ -1,671 +1,671 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing -// Date: 7/30/2014 -// Design Name: MMCME2 DRP -// Module Name: mmcme2_drp_func.h -// Version: 1.04 -// Target Devices: 7 Series || MMCM -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 MMCM. -// -// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_0111_00, - 10'b0010_1011_00, - 10'b0010_1101_00, - 10'b0010_0011_00, - 10'b0010_0101_00, - 10'b0010_0101_00, - 10'b0010_1001_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0100_1111_00, - 10'b0101_1011_00, - 10'b0111_0111_00, - 10'b1101_0111_00, - 10'b1110_1011_00, - 10'b1110_1101_00, - 10'b1111_0011_00, - 10'b1110_0101_00, - 10'b1111_0101_00, - 10'b1111_1001_00, - 10'b1101_0001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_1001_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0011_0100_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0111_0001_00, - 10'b0111_0001_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0110_0001_00, - 10'b0110_0001_00, - 10'b0101_0110_00, - 10'b0101_0110_00, - 10'b0101_0110_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0100_1010_00, - 10'b0011_1100_00, - 10'b0011_1100_00 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_pll.vh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_pll.vh old mode 100644 new mode 100755 index 6a3e7c08..d34dbe72 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_pll.vh +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_7s_pll.vh @@ -1,531 +1,531 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing -// Date: 7/30/2014 -// Design Name: PLLE2 DRP -// Module Name: plle2_drp_func.h -// Version: 2.00 -// Target Devices: 7 Series || PLL -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 PLL. -// Updated for CR663854. -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - -`ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); -`endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end -`ifdef DEBUG - $display("round_frac: %h", round_frac); -`endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - -`ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); -`endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - -`ifdef DEBUG - $display("temp: %h", temp); -`endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the PLL -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_00, - 10'b0010_1111_00, - 10'b0010_0111_00, - 10'b0010_1101_00, - 10'b0010_0101_00, - 10'b0010_0101_00, - 10'b0010_1001_00, - 10'b0010_1110_00, - 10'b0010_1110_00, - 10'b0010_0001_00, - 10'b0010_0001_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_0110_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1010_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_1100_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0010_0010_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0011_1100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0011_0111_00, - 10'b0011_0111_00, - 10'b0101_1111_00, - 10'b0111_1111_00, - 10'b0111_1011_00, - 10'b1101_0111_00, - 10'b1110_1011_00, - 10'b1110_1101_00, - 10'b1111_1101_00, - 10'b1111_0111_00, - 10'b1111_1011_00, - 10'b1111_1101_00, - 10'b1111_0011_00, - 10'b1110_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b1111_0101_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0111_0110_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b0101_1100_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b1100_0001_00, - 10'b0100_0010_00, - 10'b0100_0010_00, - 10'b0100_0010_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0011_0100_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0010_1000_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0100_1100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00, - 10'b0010_0100_00 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); -`endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - -`ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); -`endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_mmcm.vh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_mmcm.vh old mode 100644 new mode 100755 index 2cffa9a7..811d4338 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_mmcm.vh +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_mmcm.vh @@ -1,671 +1,671 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa -// Date: 7/30/2014 -// Design Name: MMCME2 DRP -// Module Name: mmcme2_drp_func.h -// Version: 1.04 -// Target Devices: UltraScale Architecture || MMCM -// Tool versions: 2014.3 -// Description: This header provides the functions necessary to -// calculate the DRP register values for the V6 MMCM. -// -// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2010 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages durring elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development -// only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_pll_phase-divide:%d,phase:%d", - divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [6:0] divide // Max divide is 64 - ); - - reg [2559:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b00110_00110_1111101000_1111101001_0000000001, - 40'b01000_01000_1111101000_1111101001_0000000001, - 40'b01011_01011_1111101000_1111101001_0000000001, - 40'b01110_01110_1111101000_1111101001_0000000001, - 40'b10001_10001_1111101000_1111101001_0000000001, - 40'b10011_10011_1111101000_1111101001_0000000001, - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [6:0] divide, // Max divide is 64 - input [8*9:0] BANDWIDTH - ); - - reg [639:0] lookup_low; - reg [639:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_0111_11, - 10'b0010_0111_11, - 10'b0010_0111_11, - 10'b0010_1101_11, - 10'b0010_1101_11, - 10'b0010_1101_11, - 10'b0010_0011_11, - 10'b0010_0101_11, - 10'b0010_0101_11, - 10'b0010_0101_11, - 10'b0010_1001_11, - 10'b0010_1001_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_1110_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0001_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_0110_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1010_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11, - 10'b0010_1100_11 - }; - - lookup_high = { - // CP_RES_LFHF - 10'b0010_1111_11, - 10'b0010_1111_11, - 10'b0010_1011_11, - 10'b0011_1111_11, - 10'b0100_1111_11, - 10'b0100_1111_11, - 10'b0101_1111_11, - 10'b0110_1111_11, - 10'b0111_1111_11, - 10'b0111_1111_11, - 10'b1100_1111_11, - 10'b1101_1111_11, - 10'b1110_1111_11, - 10'b1111_1111_11, - 10'b1111_1111_11, - 10'b1110_0111_11, - 10'b1110_1011_11, - 10'b1111_0111_11, - 10'b1111_1011_11, - 10'b1111_1011_11, - 10'b1110_1101_11, - 10'b1111_1101_11, - 10'b1111_1101_11, - 10'b1111_0011_11, - 10'b1111_0011_11, - 10'b1111_0011_11, - 10'b1110_0101_11, - 10'b1110_0101_11, - 10'b1110_0101_11, - 10'b1111_0101_11, - 10'b1111_0101_11, - 10'b1111_0101_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1110_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1111_1110_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1110_0001_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_0110_11, - 10'b1100_1010_11, - 10'b1100_1010_11, - 10'b1100_1010_11, - 10'b1100_1010_11 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 1,000 - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_pll.vh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_pll.vh old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_plus_mmcm.vh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_plus_mmcm.vh old mode 100644 new mode 100755 index 61edf85c..ebf87be0 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_plus_mmcm.vh +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -1,861 +1,861 @@ -/////////////////////////////////////////////////////////////////////////////// -// -// Company: Xilinx -// Engineer: Jim Tatsukawa. Updated by Ralf Krueger -// Date: 7/30/2014 -// Design Name: MMCME4 DRP -// Module Name: mmcme4_drp_func.h -// Version: 1.31 -// Target Devices: UltraScale Plus Architecture -// Tool versions: 2017.1 -// Description: This header provides the functions necessary to -// calculate the DRP register values for UltraScal+ MMCM. -// -// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) -// 4/13 - Fractional divide function in mmcm_frac_count_calc function -// 2/28/17 - Updated for Ultrascale Plus -// -// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR -// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING -// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -// APPLICATION OR STANDARD, XILINX IS MAKING NO -// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE -// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY -// REQUIRE FOR YOUR IMPLEMENTATION. XILINX -// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH -// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, -// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES -// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE. -// -// (c) Copyright 2009-2017 Xilinx, Inc. -// All rights reserved. -// -/////////////////////////////////////////////////////////////////////////////// - -// These are user functions that should not be modified. Changes to the defines -// or code within the functions may alter the accuracy of the calculations. - -// Define debug to provide extra messages during elaboration -//`define DEBUG 1 - -// FRAC_PRECISION describes the width of the fractional portion of the fixed -// point numbers. These should not be modified, they are for development only -`define FRAC_PRECISION 10 -// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). -// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs -// greater than 32 -`define FIXED_WIDTH 32 - -// This function takes a fixed point number and rounds it to the nearest -// fractional precision bit. -function [`FIXED_WIDTH:1] round_frac - ( - // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number - input [`FIXED_WIDTH:1] decimal, - - // This describes the precision of the fraction, for example a value - // of 1 would modify the fractional so that instead of being a .16 - // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) - input [`FIXED_WIDTH:1] precision - ); - - begin - - `ifdef DEBUG - $display("round_frac - decimal: %h, precision: %h", decimal, precision); - `endif - // If the fractional precision bit is high then round up - if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin - round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); - end else begin - round_frac = decimal; - end - `ifdef DEBUG - $display("round_frac: %h", round_frac); - `endif - end -endfunction - -// This function calculates high_time, low_time, w_edge, and no_count -// of a non-fractional counter based on the divide and duty cycle -// -// NOTE: high_time and low_time are returned as integers between 0 and 63 -// inclusive. 64 should equal 6'b000000 (in other words it is okay to -// ignore the overflow) -function [13:0] mmcm_pll_divider - ( - input [7:0] divide, // Max divide is 128 - input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 - ); - - reg [`FIXED_WIDTH:1] duty_cycle_fix; - - // High/Low time is initially calculated with a wider integer to prevent a - // calculation error when it overflows to 64. - reg [6:0] high_time; - reg [6:0] low_time; - reg w_edge; - reg no_count; - - reg [`FIXED_WIDTH:1] temp; - - begin - // Duty Cycle must be between 0 and 1,000 - if(duty_cycle <=0 || duty_cycle >= 100000) begin -`ifndef SYNTHESIS - $display("ERROR: duty_cycle: %d is invalid", duty_cycle); - `endif - $finish; - end - - // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point - duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; - - `ifdef DEBUG - $display("duty_cycle_fix: %h", duty_cycle_fix); - `endif - - // If the divide is 1 nothing needs to be set except the no_count bit. - // Other values are dummies - if(divide == 7'h01) begin - high_time = 7'h01; - w_edge = 1'b0; - low_time = 7'h01; - no_count = 1'b1; - end else begin - temp = round_frac(duty_cycle_fix*divide, 1); - - // comes from above round_frac - high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; - // If the duty cycle * divide rounded is .5 or greater then this bit - // is set. - w_edge = temp[`FRAC_PRECISION]; // comes from round_frac - - // If the high time comes out to 0, it needs to be set to at least 1 - // and w_edge set to 0 - if(high_time == 7'h00) begin - high_time = 7'h01; - w_edge = 1'b0; - end - - if(high_time == divide) begin - high_time = divide - 1; - w_edge = 1'b1; - end - - // Calculate low_time based on the divide setting and set no_count to - // 0 as it is only used when divide is 1. - low_time = divide - high_time; - no_count = 1'b0; - end - - // Set the return value. - mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; - end -endfunction - -// This function calculates mx, delay_time, and phase_mux -// of a non-fractional counter based on the divide and phase -// -// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux -// is used. -function [10:0] mmcm_pll_phase - ( - // divide must be an integer (use fractional if not) - // assumed that divide already checked to be valid - input [7:0] divide, // Max divide is 128 - - // Phase is given in degrees (-360,000 to 360,000) - input signed [31:0] phase - ); - - reg [`FIXED_WIDTH:1] phase_in_cycles; - reg [`FIXED_WIDTH:1] phase_fixed; - reg [1:0] mx; - reg [5:0] delay_time; - reg [2:0] phase_mux; - - reg [`FIXED_WIDTH:1] temp; - - begin -`ifdef DEBUG - $display("mmcm_phase-divide:%d,phase:%d", divide, phase); -`endif - - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - // If phase is less than 0, convert it to a positive phase shift - // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point - if(phase < 0) begin - phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; - end else begin - phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; - end - - // Put phase in terms of decimal number of vco clock cycles - phase_in_cycles = ( phase_fixed * divide ) / 360; - -`ifdef DEBUG - $display("phase_in_cycles: %h", phase_in_cycles); -`endif - - temp = round_frac(phase_in_cycles, 3); - - // set mx to 2'b00 that the phase mux from the VCO is enabled - mx = 2'b00; - phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; - delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; - - `ifdef DEBUG - $display("temp: %h", temp); - `endif - - // Setup the return value - mmcm_pll_phase={mx, phase_mux, delay_time}; - end -endfunction - -// This function takes the divide value and outputs the necessary lock values -function [39:0] mmcm_pll_lock_lookup - ( - input [7:0] divide // Max M divide is 128 in UltrascalePlus - ); - - reg [5119:0] lookup; - - begin - lookup = { - // This table is composed of: - // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt - 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) - 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 - 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 - 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 - 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 - 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 - 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 - 40'b10110_10110_1111101000_1111101001_0000000001, - 40'b11001_11001_1111101000_1111101001_0000000001, - 40'b11100_11100_1111101000_1111101001_0000000001, - 40'b11111_11111_1110000100_1111101001_0000000001, - 40'b11111_11111_1100111001_1111101001_0000000001, - 40'b11111_11111_1011101110_1111101001_0000000001, - 40'b11111_11111_1010111100_1111101001_0000000001, - 40'b11111_11111_1010001010_1111101001_0000000001, - 40'b11111_11111_1001110001_1111101001_0000000001, - 40'b11111_11111_1000111111_1111101001_0000000001, - 40'b11111_11111_1000100110_1111101001_0000000001, - 40'b11111_11111_1000001101_1111101001_0000000001, - 40'b11111_11111_0111110100_1111101001_0000000001, - 40'b11111_11111_0111011011_1111101001_0000000001, - 40'b11111_11111_0111000010_1111101001_0000000001, - 40'b11111_11111_0110101001_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0110010000_1111101001_0000000001, - 40'b11111_11111_0101110111_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101011110_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0101000101_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100101100_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0100010011_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, - 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 - 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 - }; - - // Set lookup_entry with the explicit bits from lookup with a part select - mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; - `ifdef DEBUG - $display("lock_lookup: %b", mmcm_pll_lock_lookup); - `endif - end -endfunction - -// This function takes the divide value and the bandwidth setting of the MMCM -// and outputs the digital filter settings necessary. -function [9:0] mmcm_pll_filter_lookup - ( - input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus - input [8*9:0] BANDWIDTH - ); - - reg [1279:0] lookup_low; - reg [1279:0] lookup_high; - - reg [9:0] lookup_entry; - - begin - lookup_low = { - // CP_RES_LFHF - 10'b0011_1111_11, // M=1 - not legal - 10'b0011_1111_11, // M=2 - 10'b0011_1101_11, // M=3 - 10'b0011_0101_11, // M=4 - 10'b0011_1001_11, // M=5 - 10'b0011_1110_11, // M=6 - 10'b0011_1110_11, // M=7 - 10'b0011_0001_11, - 10'b0011_0110_11, - 10'b0011_0110_11, - 10'b0011_0110_11, - 10'b0011_1010_11, - 10'b0011_1010_11, - 10'b0011_1010_11, - 10'b0100_0110_11, - 10'b0011_1100_11, - 10'b1110_0110_11, - 10'b1111_0110_11, - 10'b1110_1010_11, - 10'b1110_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, // M=127 - 10'b1101_1000_11 // M=128 -}; - - lookup_high = { - // CP_RES_LFHF - 10'b0111_1111_11, // M=1 - not legal - 10'b0111_1111_11, // M=2 - 10'b1110_1111_11, // M=3 - 10'b1111_1111_11, // M=4 - 10'b1111_1011_11, // M=5 - 10'b1111_1101_11, // M=6 - 10'b1111_0011_11, // M=7 - 10'b1110_0101_11, - 10'b1111_1001_11, - 10'b1111_1001_11, - 10'b1110_1110_11, - 10'b1111_1110_11, - 10'b1111_0001_11, - 10'b1111_0001_11, - 10'b1111_0001_11, - 10'b1110_0110_11, - 10'b1110_0110_11, - 10'b1111_0110_11, - 10'b1110_1010_11, - 10'b1110_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1111_1010_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1101_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1110_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1111_1100_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1110_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1111_0010_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1100_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1101_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1110_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1111_0100_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11, - 10'b1101_1000_11 // M=128 -}; - - // Set lookup_entry with the explicit bits from lookup with a part select - if(BANDWIDTH == "LOW") begin - // Low Bandwidth - mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; - end else begin - // High or optimized bandwidth - mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; - end - - `ifdef DEBUG - $display("filter_lookup: %b", mmcm_pll_filter_lookup); - `endif - end -endfunction - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -function [37:0] mmcm_pll_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle // Multiplied by 100,000 - ); - - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] - div_calc = mmcm_pll_divider(divide, duty_cycle); - // mx[10:9], pm[8:6], dt[5:0] - phase_calc = mmcm_pll_phase(divide, phase); - - // Return value is the upper and lower address of counter - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - `ifdef DEBUG - $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", - divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], - div_calc[13], div_calc[12], - phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); - `endif - - mmcm_pll_count_calc = - { - // Upper Address - 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], - // Lower Address - phase_calc[8:6], 1'b0, div_calc[11:0] - }; - end -endfunction - - -// This function takes in the divide, phase, and duty cycle -// setting to calculate the upper and lower counter registers. -// for fractional multiply/divide functions. -// -// -function [37:0] mmcm_frac_count_calc - ( - input [7:0] divide, // Max divide is 128 - input signed [31:0] phase, - input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional - input [9:0] frac // Multiplied by 1000 - ); - - //Required for fractional divide calculations - reg [7:0] lt_frac; - reg [7:0] ht_frac; - - reg /*[7:0]*/ wf_fall_frac; - reg /*[7:0]*/ wf_rise_frac; - - reg [31:0] a; - reg [7:0] pm_rise_frac_filtered ; - reg [7:0] pm_fall_frac_filtered ; - reg [7:0] clkout0_divide_int; - reg [2:0] clkout0_divide_frac; - reg [7:0] even_part_high; - reg [7:0] even_part_low; - - reg [7:0] odd; - reg [7:0] odd_and_frac; - - reg [7:0] pm_fall; - reg [7:0] pm_rise; - reg [7:0] dt; - reg [7:0] dt_int; - reg [63:0] dt_calc; - - reg [7:0] pm_rise_frac; - reg [7:0] pm_fall_frac; - - reg [31:0] a_per_in_octets; - reg [31:0] a_phase_in_cycles; - - parameter precision = 0.125; - - reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 - reg [31: 0] phase_pos; - reg [31: 0] phase_vco; - reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 - reg [13:0] div_calc; - reg [16:0] phase_calc; - - begin - `ifdef DEBUG - $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", - divide, phase, duty_cycle); - `endif - - //convert phase to fixed - if ((phase < -360000) || (phase > 360000)) begin -`ifndef SYNTHESIS - $display("ERROR: phase of $phase is not between -360000 and 360000"); - `endif - $finish; - end - - - // Return value is - // Transfer data - // RESERVED [37:36] - // FRAC_TIME [35:33] - // FRAC_WF_FALL [32] - // Upper address is: - // RESERVED [31:26] - // MX [25:24] - // EDGE [23] - // NOCOUNT [22] - // DELAY_TIME [21:16] - // Lower Address is: - // PHASE_MUX [15:13] - // RESERVED [12] - // HIGH_TIME [11:6] - // LOW_TIME [5:0] - - - - clkout0_divide_frac = frac / 125; - clkout0_divide_int = divide; - - even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); - even_part_low = even_part_high; - - odd = clkout0_divide_int - even_part_high - even_part_low; - odd_and_frac = (8*odd) + clkout0_divide_frac; - - lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) - ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) - - pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 - pm_rise = 0; //0 - - wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) - wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) - - - - //Calculate phase in fractional cycles - a_per_in_octets = (8 * divide) + (frac / 125) ; - a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors - pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; - - dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) - dt = dt_calc[7:0]; - - pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; - - dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) - pm_fall_frac = pm_fall + pm_rise_frac; - pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; - - div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] - phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} - - mmcm_frac_count_calc[37:0] = - { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, - 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], - pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] - } ; - - `ifdef DEBUG - $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); - `endif - - end -endfunction - +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_plus_pll.vh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c923/mmcm_pll_drp_func_us_plus_pll.vh old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_bits.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_bits.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_data.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_data.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_event.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_event.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_gray.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cb53/sync_gray.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cf62/address_gray_pipelined.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cf62/address_gray_pipelined.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cf62/address_sync.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cf62/address_sync.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cf62/util_axis_fifo.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/cf62/util_axis_fifo.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/common/ad_mem.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/common/ad_mem.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/f8c3/hdl/microblaze_v11_0_vh_rfs.vhd b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/f8c3/hdl/microblaze_v11_0_vh_rfs.vhd old mode 100644 new mode 100755 diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.protoinst b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.protoinst index 10fbb71a..464080d3 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.protoinst +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.protoinst @@ -160,38 +160,22 @@ "ports": { "ACLK": { "actual": "M_ACLK"}, "ARADDR": { "actual": "M_AXI_araddr"}, - "ARBURST": { "actual": "M_AXI_arburst"}, - "ARCACHE": { "actual": "M_AXI_arcache"}, "ARESETN": { "actual": "M_ARESETN"}, - "ARLEN": { "actual": "M_AXI_arlen"}, - "ARLOCK": { "actual": "M_AXI_arlock"}, "ARPROT": { "actual": "M_AXI_arprot"}, - "ARQOS": { "actual": "M_AXI_arqos"}, "ARREADY": { "actual": "M_AXI_arready"}, - "ARREGION": { "actual": "M_AXI_arregion"}, - "ARSIZE": { "actual": "M_AXI_arsize"}, "ARVALID": { "actual": "M_AXI_arvalid"}, "AWADDR": { "actual": "M_AXI_awaddr"}, - "AWBURST": { "actual": "M_AXI_awburst"}, - "AWCACHE": { "actual": "M_AXI_awcache"}, - "AWLEN": { "actual": "M_AXI_awlen"}, - "AWLOCK": { "actual": "M_AXI_awlock"}, "AWPROT": { "actual": "M_AXI_awprot"}, - "AWQOS": { "actual": "M_AXI_awqos"}, "AWREADY": { "actual": "M_AXI_awready"}, - "AWREGION": { "actual": "M_AXI_awregion"}, - "AWSIZE": { "actual": "M_AXI_awsize"}, "AWVALID": { "actual": "M_AXI_awvalid"}, "BREADY": { "actual": "M_AXI_bready"}, "BRESP": { "actual": "M_AXI_bresp"}, "BVALID": { "actual": "M_AXI_bvalid"}, "RDATA": { "actual": "M_AXI_rdata"}, - "RLAST": { "actual": "M_AXI_rlast"}, "RREADY": { "actual": "M_AXI_rready"}, "RRESP": { "actual": "M_AXI_rresp"}, "RVALID": { "actual": "M_AXI_rvalid"}, "WDATA": { "actual": "M_AXI_wdata"}, - "WLAST": { "actual": "M_AXI_wlast"}, "WREADY": { "actual": "M_AXI_wready"}, "WSTRB": { "actual": "M_AXI_wstrb"}, "WVALID": { "actual": "M_AXI_wvalid"} @@ -202,38 +186,22 @@ "ports": { "ACLK": { "actual": "S_ACLK"}, "ARADDR": { "actual": "S_AXI_araddr"}, - "ARBURST": { "actual": "S_AXI_arburst"}, - "ARCACHE": { "actual": "S_AXI_arcache"}, "ARESETN": { "actual": "S_ARESETN"}, - "ARLEN": { "actual": "S_AXI_arlen"}, - "ARLOCK": { "actual": "S_AXI_arlock"}, "ARPROT": { "actual": "S_AXI_arprot"}, - "ARQOS": { "actual": "S_AXI_arqos"}, "ARREADY": { "actual": "S_AXI_arready"}, - "ARREGION": { "actual": "S_AXI_arregion"}, - "ARSIZE": { "actual": "S_AXI_arsize"}, "ARVALID": { "actual": "S_AXI_arvalid"}, "AWADDR": { "actual": "S_AXI_awaddr"}, - "AWBURST": { "actual": "S_AXI_awburst"}, - "AWCACHE": { "actual": "S_AXI_awcache"}, - "AWLEN": { "actual": "S_AXI_awlen"}, - "AWLOCK": { "actual": "S_AXI_awlock"}, "AWPROT": { "actual": "S_AXI_awprot"}, - "AWQOS": { "actual": "S_AXI_awqos"}, "AWREADY": { "actual": "S_AXI_awready"}, - "AWREGION": { "actual": "S_AXI_awregion"}, - "AWSIZE": { "actual": "S_AXI_awsize"}, "AWVALID": { "actual": "S_AXI_awvalid"}, "BREADY": { "actual": "S_AXI_bready"}, "BRESP": { "actual": "S_AXI_bresp"}, "BVALID": { "actual": "S_AXI_bvalid"}, "RDATA": { "actual": "S_AXI_rdata"}, - "RLAST": { "actual": "S_AXI_rlast"}, "RREADY": { "actual": "S_AXI_rready"}, "RRESP": { "actual": "S_AXI_rresp"}, "RVALID": { "actual": "S_AXI_rvalid"}, "WDATA": { "actual": "S_AXI_wdata"}, - "WLAST": { "actual": "S_AXI_wlast"}, "WREADY": { "actual": "S_AXI_wready"}, "WSTRB": { "actual": "S_AXI_wstrb"}, "WVALID": { "actual": "S_AXI_wvalid"} diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.v index 960df9b9..446eda28 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/sim/system_bd.v @@ -1,8 +1,8 @@ //Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- -//Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -//Date : Sun Mar 19 00:32:52 2023 -//Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +//Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +//Date : Wed Mar 22 22:51:50 2023 +//Host : localhost.localdomain running 64-bit unknown //Command : generate_target system_bd.bd //Design : system_bd //Purpose : IP block netlist @@ -356,212 +356,117 @@ module m01_couplers_imp_SHET14 (M_ACLK, M_ARESETN, M_AXI_araddr, - M_AXI_arburst, - M_AXI_arcache, - M_AXI_arlen, - M_AXI_arlock, M_AXI_arprot, - M_AXI_arqos, M_AXI_arready, - M_AXI_arregion, - M_AXI_arsize, M_AXI_arvalid, M_AXI_awaddr, - M_AXI_awburst, - M_AXI_awcache, - M_AXI_awlen, - M_AXI_awlock, M_AXI_awprot, - M_AXI_awqos, M_AXI_awready, - M_AXI_awregion, - M_AXI_awsize, M_AXI_awvalid, M_AXI_bready, M_AXI_bresp, M_AXI_bvalid, M_AXI_rdata, - M_AXI_rlast, M_AXI_rready, M_AXI_rresp, M_AXI_rvalid, M_AXI_wdata, - M_AXI_wlast, M_AXI_wready, M_AXI_wstrb, M_AXI_wvalid, S_ACLK, S_ARESETN, S_AXI_araddr, - S_AXI_arburst, - S_AXI_arcache, - S_AXI_arlen, - S_AXI_arlock, S_AXI_arprot, - S_AXI_arqos, S_AXI_arready, - S_AXI_arregion, - S_AXI_arsize, S_AXI_arvalid, S_AXI_awaddr, - S_AXI_awburst, - S_AXI_awcache, - S_AXI_awlen, - S_AXI_awlock, S_AXI_awprot, - S_AXI_awqos, S_AXI_awready, - S_AXI_awregion, - S_AXI_awsize, S_AXI_awvalid, S_AXI_bready, S_AXI_bresp, S_AXI_bvalid, S_AXI_rdata, - S_AXI_rlast, S_AXI_rready, S_AXI_rresp, S_AXI_rvalid, S_AXI_wdata, - S_AXI_wlast, S_AXI_wready, S_AXI_wstrb, S_AXI_wvalid); input M_ACLK; input M_ARESETN; output M_AXI_araddr; - output M_AXI_arburst; - output M_AXI_arcache; - output M_AXI_arlen; - output M_AXI_arlock; output M_AXI_arprot; - output M_AXI_arqos; input M_AXI_arready; - output M_AXI_arregion; - output M_AXI_arsize; output M_AXI_arvalid; output M_AXI_awaddr; - output M_AXI_awburst; - output M_AXI_awcache; - output M_AXI_awlen; - output M_AXI_awlock; output M_AXI_awprot; - output M_AXI_awqos; input M_AXI_awready; - output M_AXI_awregion; - output M_AXI_awsize; output M_AXI_awvalid; output M_AXI_bready; input M_AXI_bresp; input M_AXI_bvalid; input M_AXI_rdata; - input M_AXI_rlast; output M_AXI_rready; input M_AXI_rresp; input M_AXI_rvalid; output M_AXI_wdata; - output M_AXI_wlast; input M_AXI_wready; output M_AXI_wstrb; output M_AXI_wvalid; input S_ACLK; input S_ARESETN; input S_AXI_araddr; - input S_AXI_arburst; - input S_AXI_arcache; - input S_AXI_arlen; - input S_AXI_arlock; input S_AXI_arprot; - input S_AXI_arqos; output S_AXI_arready; - input S_AXI_arregion; - input S_AXI_arsize; input S_AXI_arvalid; input S_AXI_awaddr; - input S_AXI_awburst; - input S_AXI_awcache; - input S_AXI_awlen; - input S_AXI_awlock; input S_AXI_awprot; - input S_AXI_awqos; output S_AXI_awready; - input S_AXI_awregion; - input S_AXI_awsize; input S_AXI_awvalid; input S_AXI_bready; output S_AXI_bresp; output S_AXI_bvalid; output S_AXI_rdata; - output S_AXI_rlast; input S_AXI_rready; output S_AXI_rresp; output S_AXI_rvalid; input S_AXI_wdata; - input S_AXI_wlast; output S_AXI_wready; input S_AXI_wstrb; input S_AXI_wvalid; wire m01_couplers_to_m01_couplers_ARADDR; - wire m01_couplers_to_m01_couplers_ARBURST; - wire m01_couplers_to_m01_couplers_ARCACHE; - wire m01_couplers_to_m01_couplers_ARLEN; - wire m01_couplers_to_m01_couplers_ARLOCK; wire m01_couplers_to_m01_couplers_ARPROT; - wire m01_couplers_to_m01_couplers_ARQOS; wire m01_couplers_to_m01_couplers_ARREADY; - wire m01_couplers_to_m01_couplers_ARREGION; - wire m01_couplers_to_m01_couplers_ARSIZE; wire m01_couplers_to_m01_couplers_ARVALID; wire m01_couplers_to_m01_couplers_AWADDR; - wire m01_couplers_to_m01_couplers_AWBURST; - wire m01_couplers_to_m01_couplers_AWCACHE; - wire m01_couplers_to_m01_couplers_AWLEN; - wire m01_couplers_to_m01_couplers_AWLOCK; wire m01_couplers_to_m01_couplers_AWPROT; - wire m01_couplers_to_m01_couplers_AWQOS; wire m01_couplers_to_m01_couplers_AWREADY; - wire m01_couplers_to_m01_couplers_AWREGION; - wire m01_couplers_to_m01_couplers_AWSIZE; wire m01_couplers_to_m01_couplers_AWVALID; wire m01_couplers_to_m01_couplers_BREADY; wire m01_couplers_to_m01_couplers_BRESP; wire m01_couplers_to_m01_couplers_BVALID; wire m01_couplers_to_m01_couplers_RDATA; - wire m01_couplers_to_m01_couplers_RLAST; wire m01_couplers_to_m01_couplers_RREADY; wire m01_couplers_to_m01_couplers_RRESP; wire m01_couplers_to_m01_couplers_RVALID; wire m01_couplers_to_m01_couplers_WDATA; - wire m01_couplers_to_m01_couplers_WLAST; wire m01_couplers_to_m01_couplers_WREADY; wire m01_couplers_to_m01_couplers_WSTRB; wire m01_couplers_to_m01_couplers_WVALID; assign M_AXI_araddr = m01_couplers_to_m01_couplers_ARADDR; - assign M_AXI_arburst = m01_couplers_to_m01_couplers_ARBURST; - assign M_AXI_arcache = m01_couplers_to_m01_couplers_ARCACHE; - assign M_AXI_arlen = m01_couplers_to_m01_couplers_ARLEN; - assign M_AXI_arlock = m01_couplers_to_m01_couplers_ARLOCK; assign M_AXI_arprot = m01_couplers_to_m01_couplers_ARPROT; - assign M_AXI_arqos = m01_couplers_to_m01_couplers_ARQOS; - assign M_AXI_arregion = m01_couplers_to_m01_couplers_ARREGION; - assign M_AXI_arsize = m01_couplers_to_m01_couplers_ARSIZE; assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID; assign M_AXI_awaddr = m01_couplers_to_m01_couplers_AWADDR; - assign M_AXI_awburst = m01_couplers_to_m01_couplers_AWBURST; - assign M_AXI_awcache = m01_couplers_to_m01_couplers_AWCACHE; - assign M_AXI_awlen = m01_couplers_to_m01_couplers_AWLEN; - assign M_AXI_awlock = m01_couplers_to_m01_couplers_AWLOCK; assign M_AXI_awprot = m01_couplers_to_m01_couplers_AWPROT; - assign M_AXI_awqos = m01_couplers_to_m01_couplers_AWQOS; - assign M_AXI_awregion = m01_couplers_to_m01_couplers_AWREGION; - assign M_AXI_awsize = m01_couplers_to_m01_couplers_AWSIZE; assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID; assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY; assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY; assign M_AXI_wdata = m01_couplers_to_m01_couplers_WDATA; - assign M_AXI_wlast = m01_couplers_to_m01_couplers_WLAST; assign M_AXI_wstrb = m01_couplers_to_m01_couplers_WSTRB; assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID; assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY; @@ -569,42 +474,25 @@ module m01_couplers_imp_SHET14 assign S_AXI_bresp = m01_couplers_to_m01_couplers_BRESP; assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID; assign S_AXI_rdata = m01_couplers_to_m01_couplers_RDATA; - assign S_AXI_rlast = m01_couplers_to_m01_couplers_RLAST; assign S_AXI_rresp = m01_couplers_to_m01_couplers_RRESP; assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID; assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY; assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr; - assign m01_couplers_to_m01_couplers_ARBURST = S_AXI_arburst; - assign m01_couplers_to_m01_couplers_ARCACHE = S_AXI_arcache; - assign m01_couplers_to_m01_couplers_ARLEN = S_AXI_arlen; - assign m01_couplers_to_m01_couplers_ARLOCK = S_AXI_arlock; assign m01_couplers_to_m01_couplers_ARPROT = S_AXI_arprot; - assign m01_couplers_to_m01_couplers_ARQOS = S_AXI_arqos; assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready; - assign m01_couplers_to_m01_couplers_ARREGION = S_AXI_arregion; - assign m01_couplers_to_m01_couplers_ARSIZE = S_AXI_arsize; assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid; assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr; - assign m01_couplers_to_m01_couplers_AWBURST = S_AXI_awburst; - assign m01_couplers_to_m01_couplers_AWCACHE = S_AXI_awcache; - assign m01_couplers_to_m01_couplers_AWLEN = S_AXI_awlen; - assign m01_couplers_to_m01_couplers_AWLOCK = S_AXI_awlock; assign m01_couplers_to_m01_couplers_AWPROT = S_AXI_awprot; - assign m01_couplers_to_m01_couplers_AWQOS = S_AXI_awqos; assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready; - assign m01_couplers_to_m01_couplers_AWREGION = S_AXI_awregion; - assign m01_couplers_to_m01_couplers_AWSIZE = S_AXI_awsize; assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid; assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready; assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp; assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid; assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata; - assign m01_couplers_to_m01_couplers_RLAST = M_AXI_rlast; assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready; assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp; assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid; assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata; - assign m01_couplers_to_m01_couplers_WLAST = S_AXI_wlast; assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready; assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb; assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid; @@ -1311,7 +1199,6 @@ module system_bd .M01_AXI_bresp(1'b0), .M01_AXI_bvalid(1'b0), .M01_AXI_rdata(1'b0), - .M01_AXI_rlast(1'b0), .M01_AXI_rresp(1'b0), .M01_AXI_rvalid(1'b0), .M01_AXI_wready(1'b0), @@ -1514,37 +1401,21 @@ module system_bd_axi_interconnect_0 M01_ACLK, M01_ARESETN, M01_AXI_araddr, - M01_AXI_arburst, - M01_AXI_arcache, - M01_AXI_arlen, - M01_AXI_arlock, M01_AXI_arprot, - M01_AXI_arqos, M01_AXI_arready, - M01_AXI_arregion, - M01_AXI_arsize, M01_AXI_arvalid, M01_AXI_awaddr, - M01_AXI_awburst, - M01_AXI_awcache, - M01_AXI_awlen, - M01_AXI_awlock, M01_AXI_awprot, - M01_AXI_awqos, M01_AXI_awready, - M01_AXI_awregion, - M01_AXI_awsize, M01_AXI_awvalid, M01_AXI_bready, M01_AXI_bresp, M01_AXI_bvalid, M01_AXI_rdata, - M01_AXI_rlast, M01_AXI_rready, M01_AXI_rresp, M01_AXI_rvalid, M01_AXI_wdata, - M01_AXI_wlast, M01_AXI_wready, M01_AXI_wstrb, M01_AXI_wvalid, @@ -1614,37 +1485,21 @@ module system_bd_axi_interconnect_0 input M01_ACLK; input M01_ARESETN; output M01_AXI_araddr; - output M01_AXI_arburst; - output M01_AXI_arcache; - output M01_AXI_arlen; - output M01_AXI_arlock; output M01_AXI_arprot; - output M01_AXI_arqos; input M01_AXI_arready; - output M01_AXI_arregion; - output M01_AXI_arsize; output M01_AXI_arvalid; output M01_AXI_awaddr; - output M01_AXI_awburst; - output M01_AXI_awcache; - output M01_AXI_awlen; - output M01_AXI_awlock; output M01_AXI_awprot; - output M01_AXI_awqos; input M01_AXI_awready; - output M01_AXI_awregion; - output M01_AXI_awsize; output M01_AXI_awvalid; output M01_AXI_bready; input M01_AXI_bresp; input M01_AXI_bvalid; input M01_AXI_rdata; - input M01_AXI_rlast; output M01_AXI_rready; input M01_AXI_rresp; input M01_AXI_rvalid; output M01_AXI_wdata; - output M01_AXI_wlast; input M01_AXI_wready; output M01_AXI_wstrb; output M01_AXI_wvalid; @@ -1730,37 +1585,21 @@ module system_bd_axi_interconnect_0 wire [3:0]m00_couplers_to_axi_interconnect_WSTRB; wire m00_couplers_to_axi_interconnect_WVALID; wire m01_couplers_to_axi_interconnect_ARADDR; - wire m01_couplers_to_axi_interconnect_ARBURST; - wire m01_couplers_to_axi_interconnect_ARCACHE; - wire m01_couplers_to_axi_interconnect_ARLEN; - wire m01_couplers_to_axi_interconnect_ARLOCK; wire m01_couplers_to_axi_interconnect_ARPROT; - wire m01_couplers_to_axi_interconnect_ARQOS; wire m01_couplers_to_axi_interconnect_ARREADY; - wire m01_couplers_to_axi_interconnect_ARREGION; - wire m01_couplers_to_axi_interconnect_ARSIZE; wire m01_couplers_to_axi_interconnect_ARVALID; wire m01_couplers_to_axi_interconnect_AWADDR; - wire m01_couplers_to_axi_interconnect_AWBURST; - wire m01_couplers_to_axi_interconnect_AWCACHE; - wire m01_couplers_to_axi_interconnect_AWLEN; - wire m01_couplers_to_axi_interconnect_AWLOCK; wire m01_couplers_to_axi_interconnect_AWPROT; - wire m01_couplers_to_axi_interconnect_AWQOS; wire m01_couplers_to_axi_interconnect_AWREADY; - wire m01_couplers_to_axi_interconnect_AWREGION; - wire m01_couplers_to_axi_interconnect_AWSIZE; wire m01_couplers_to_axi_interconnect_AWVALID; wire m01_couplers_to_axi_interconnect_BREADY; wire m01_couplers_to_axi_interconnect_BRESP; wire m01_couplers_to_axi_interconnect_BVALID; wire m01_couplers_to_axi_interconnect_RDATA; - wire m01_couplers_to_axi_interconnect_RLAST; wire m01_couplers_to_axi_interconnect_RREADY; wire m01_couplers_to_axi_interconnect_RRESP; wire m01_couplers_to_axi_interconnect_RVALID; wire m01_couplers_to_axi_interconnect_WDATA; - wire m01_couplers_to_axi_interconnect_WLAST; wire m01_couplers_to_axi_interconnect_WREADY; wire m01_couplers_to_axi_interconnect_WSTRB; wire m01_couplers_to_axi_interconnect_WVALID; @@ -1868,29 +1707,14 @@ module system_bd_axi_interconnect_0 assign M00_AXI_wstrb[3:0] = m00_couplers_to_axi_interconnect_WSTRB; assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_WVALID; assign M01_AXI_araddr = m01_couplers_to_axi_interconnect_ARADDR; - assign M01_AXI_arburst = m01_couplers_to_axi_interconnect_ARBURST; - assign M01_AXI_arcache = m01_couplers_to_axi_interconnect_ARCACHE; - assign M01_AXI_arlen = m01_couplers_to_axi_interconnect_ARLEN; - assign M01_AXI_arlock = m01_couplers_to_axi_interconnect_ARLOCK; assign M01_AXI_arprot = m01_couplers_to_axi_interconnect_ARPROT; - assign M01_AXI_arqos = m01_couplers_to_axi_interconnect_ARQOS; - assign M01_AXI_arregion = m01_couplers_to_axi_interconnect_ARREGION; - assign M01_AXI_arsize = m01_couplers_to_axi_interconnect_ARSIZE; assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_ARVALID; assign M01_AXI_awaddr = m01_couplers_to_axi_interconnect_AWADDR; - assign M01_AXI_awburst = m01_couplers_to_axi_interconnect_AWBURST; - assign M01_AXI_awcache = m01_couplers_to_axi_interconnect_AWCACHE; - assign M01_AXI_awlen = m01_couplers_to_axi_interconnect_AWLEN; - assign M01_AXI_awlock = m01_couplers_to_axi_interconnect_AWLOCK; assign M01_AXI_awprot = m01_couplers_to_axi_interconnect_AWPROT; - assign M01_AXI_awqos = m01_couplers_to_axi_interconnect_AWQOS; - assign M01_AXI_awregion = m01_couplers_to_axi_interconnect_AWREGION; - assign M01_AXI_awsize = m01_couplers_to_axi_interconnect_AWSIZE; assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_AWVALID; assign M01_AXI_bready = m01_couplers_to_axi_interconnect_BREADY; assign M01_AXI_rready = m01_couplers_to_axi_interconnect_RREADY; assign M01_AXI_wdata = m01_couplers_to_axi_interconnect_WDATA; - assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_WLAST; assign M01_AXI_wstrb = m01_couplers_to_axi_interconnect_WSTRB; assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_WVALID; assign M02_AXI_araddr[31:0] = m02_couplers_to_axi_interconnect_ARADDR; @@ -1936,7 +1760,6 @@ module system_bd_axi_interconnect_0 assign m01_couplers_to_axi_interconnect_BRESP = M01_AXI_bresp; assign m01_couplers_to_axi_interconnect_BVALID = M01_AXI_bvalid; assign m01_couplers_to_axi_interconnect_RDATA = M01_AXI_rdata; - assign m01_couplers_to_axi_interconnect_RLAST = M01_AXI_rlast; assign m01_couplers_to_axi_interconnect_RRESP = M01_AXI_rresp; assign m01_couplers_to_axi_interconnect_RVALID = M01_AXI_rvalid; assign m01_couplers_to_axi_interconnect_WREADY = M01_AXI_wready; @@ -1995,63 +1818,33 @@ module system_bd_axi_interconnect_0 (.M_ACLK(axi_interconnect_ACLK_net), .M_ARESETN(axi_interconnect_ARESETN_net), .M_AXI_araddr(m01_couplers_to_axi_interconnect_ARADDR), - .M_AXI_arburst(m01_couplers_to_axi_interconnect_ARBURST), - .M_AXI_arcache(m01_couplers_to_axi_interconnect_ARCACHE), - .M_AXI_arlen(m01_couplers_to_axi_interconnect_ARLEN), - .M_AXI_arlock(m01_couplers_to_axi_interconnect_ARLOCK), .M_AXI_arprot(m01_couplers_to_axi_interconnect_ARPROT), - .M_AXI_arqos(m01_couplers_to_axi_interconnect_ARQOS), .M_AXI_arready(m01_couplers_to_axi_interconnect_ARREADY), - .M_AXI_arregion(m01_couplers_to_axi_interconnect_ARREGION), - .M_AXI_arsize(m01_couplers_to_axi_interconnect_ARSIZE), .M_AXI_arvalid(m01_couplers_to_axi_interconnect_ARVALID), .M_AXI_awaddr(m01_couplers_to_axi_interconnect_AWADDR), - .M_AXI_awburst(m01_couplers_to_axi_interconnect_AWBURST), - .M_AXI_awcache(m01_couplers_to_axi_interconnect_AWCACHE), - .M_AXI_awlen(m01_couplers_to_axi_interconnect_AWLEN), - .M_AXI_awlock(m01_couplers_to_axi_interconnect_AWLOCK), .M_AXI_awprot(m01_couplers_to_axi_interconnect_AWPROT), - .M_AXI_awqos(m01_couplers_to_axi_interconnect_AWQOS), .M_AXI_awready(m01_couplers_to_axi_interconnect_AWREADY), - .M_AXI_awregion(m01_couplers_to_axi_interconnect_AWREGION), - .M_AXI_awsize(m01_couplers_to_axi_interconnect_AWSIZE), .M_AXI_awvalid(m01_couplers_to_axi_interconnect_AWVALID), .M_AXI_bready(m01_couplers_to_axi_interconnect_BREADY), .M_AXI_bresp(m01_couplers_to_axi_interconnect_BRESP), .M_AXI_bvalid(m01_couplers_to_axi_interconnect_BVALID), .M_AXI_rdata(m01_couplers_to_axi_interconnect_RDATA), - .M_AXI_rlast(m01_couplers_to_axi_interconnect_RLAST), .M_AXI_rready(m01_couplers_to_axi_interconnect_RREADY), .M_AXI_rresp(m01_couplers_to_axi_interconnect_RRESP), .M_AXI_rvalid(m01_couplers_to_axi_interconnect_RVALID), .M_AXI_wdata(m01_couplers_to_axi_interconnect_WDATA), - .M_AXI_wlast(m01_couplers_to_axi_interconnect_WLAST), .M_AXI_wready(m01_couplers_to_axi_interconnect_WREADY), .M_AXI_wstrb(m01_couplers_to_axi_interconnect_WSTRB), .M_AXI_wvalid(m01_couplers_to_axi_interconnect_WVALID), .S_ACLK(axi_interconnect_ACLK_net), .S_ARESETN(axi_interconnect_ARESETN_net), .S_AXI_araddr(xbar_to_m01_couplers_ARADDR[32]), - .S_AXI_arburst(1'b0), - .S_AXI_arcache(1'b0), - .S_AXI_arlen(1'b0), - .S_AXI_arlock(1'b0), .S_AXI_arprot(xbar_to_m01_couplers_ARPROT[3]), - .S_AXI_arqos(1'b0), .S_AXI_arready(xbar_to_m01_couplers_ARREADY), - .S_AXI_arregion(1'b0), - .S_AXI_arsize(1'b0), .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID), .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[32]), - .S_AXI_awburst(1'b0), - .S_AXI_awcache(1'b0), - .S_AXI_awlen(1'b0), - .S_AXI_awlock(1'b0), .S_AXI_awprot(xbar_to_m01_couplers_AWPROT[3]), - .S_AXI_awqos(1'b0), .S_AXI_awready(xbar_to_m01_couplers_AWREADY), - .S_AXI_awregion(1'b0), - .S_AXI_awsize(1'b0), .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID), .S_AXI_bready(xbar_to_m01_couplers_BREADY), .S_AXI_bresp(xbar_to_m01_couplers_BRESP), @@ -2061,7 +1854,6 @@ module system_bd_axi_interconnect_0 .S_AXI_rresp(xbar_to_m01_couplers_RRESP), .S_AXI_rvalid(xbar_to_m01_couplers_RVALID), .S_AXI_wdata(xbar_to_m01_couplers_WDATA[32]), - .S_AXI_wlast(1'b0), .S_AXI_wready(xbar_to_m01_couplers_WREADY), .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB[4]), .S_AXI_wvalid(xbar_to_m01_couplers_WVALID)); diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.hwdef b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.hwdef index 6edb6a2d..10f934b6 100644 Binary files a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.hwdef and b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.hwdef differ diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.v b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.v index 960df9b9..446eda28 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.v +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/synth/system_bd.v @@ -1,8 +1,8 @@ //Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- -//Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 -//Date : Sun Mar 19 00:32:52 2023 -//Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +//Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +//Date : Wed Mar 22 22:51:50 2023 +//Host : localhost.localdomain running 64-bit unknown //Command : generate_target system_bd.bd //Design : system_bd //Purpose : IP block netlist @@ -356,212 +356,117 @@ module m01_couplers_imp_SHET14 (M_ACLK, M_ARESETN, M_AXI_araddr, - M_AXI_arburst, - M_AXI_arcache, - M_AXI_arlen, - M_AXI_arlock, M_AXI_arprot, - M_AXI_arqos, M_AXI_arready, - M_AXI_arregion, - M_AXI_arsize, M_AXI_arvalid, M_AXI_awaddr, - M_AXI_awburst, - M_AXI_awcache, - M_AXI_awlen, - M_AXI_awlock, M_AXI_awprot, - M_AXI_awqos, M_AXI_awready, - M_AXI_awregion, - M_AXI_awsize, M_AXI_awvalid, M_AXI_bready, M_AXI_bresp, M_AXI_bvalid, M_AXI_rdata, - M_AXI_rlast, M_AXI_rready, M_AXI_rresp, M_AXI_rvalid, M_AXI_wdata, - M_AXI_wlast, M_AXI_wready, M_AXI_wstrb, M_AXI_wvalid, S_ACLK, S_ARESETN, S_AXI_araddr, - S_AXI_arburst, - S_AXI_arcache, - S_AXI_arlen, - S_AXI_arlock, S_AXI_arprot, - S_AXI_arqos, S_AXI_arready, - S_AXI_arregion, - S_AXI_arsize, S_AXI_arvalid, S_AXI_awaddr, - S_AXI_awburst, - S_AXI_awcache, - S_AXI_awlen, - S_AXI_awlock, S_AXI_awprot, - S_AXI_awqos, S_AXI_awready, - S_AXI_awregion, - S_AXI_awsize, S_AXI_awvalid, S_AXI_bready, S_AXI_bresp, S_AXI_bvalid, S_AXI_rdata, - S_AXI_rlast, S_AXI_rready, S_AXI_rresp, S_AXI_rvalid, S_AXI_wdata, - S_AXI_wlast, S_AXI_wready, S_AXI_wstrb, S_AXI_wvalid); input M_ACLK; input M_ARESETN; output M_AXI_araddr; - output M_AXI_arburst; - output M_AXI_arcache; - output M_AXI_arlen; - output M_AXI_arlock; output M_AXI_arprot; - output M_AXI_arqos; input M_AXI_arready; - output M_AXI_arregion; - output M_AXI_arsize; output M_AXI_arvalid; output M_AXI_awaddr; - output M_AXI_awburst; - output M_AXI_awcache; - output M_AXI_awlen; - output M_AXI_awlock; output M_AXI_awprot; - output M_AXI_awqos; input M_AXI_awready; - output M_AXI_awregion; - output M_AXI_awsize; output M_AXI_awvalid; output M_AXI_bready; input M_AXI_bresp; input M_AXI_bvalid; input M_AXI_rdata; - input M_AXI_rlast; output M_AXI_rready; input M_AXI_rresp; input M_AXI_rvalid; output M_AXI_wdata; - output M_AXI_wlast; input M_AXI_wready; output M_AXI_wstrb; output M_AXI_wvalid; input S_ACLK; input S_ARESETN; input S_AXI_araddr; - input S_AXI_arburst; - input S_AXI_arcache; - input S_AXI_arlen; - input S_AXI_arlock; input S_AXI_arprot; - input S_AXI_arqos; output S_AXI_arready; - input S_AXI_arregion; - input S_AXI_arsize; input S_AXI_arvalid; input S_AXI_awaddr; - input S_AXI_awburst; - input S_AXI_awcache; - input S_AXI_awlen; - input S_AXI_awlock; input S_AXI_awprot; - input S_AXI_awqos; output S_AXI_awready; - input S_AXI_awregion; - input S_AXI_awsize; input S_AXI_awvalid; input S_AXI_bready; output S_AXI_bresp; output S_AXI_bvalid; output S_AXI_rdata; - output S_AXI_rlast; input S_AXI_rready; output S_AXI_rresp; output S_AXI_rvalid; input S_AXI_wdata; - input S_AXI_wlast; output S_AXI_wready; input S_AXI_wstrb; input S_AXI_wvalid; wire m01_couplers_to_m01_couplers_ARADDR; - wire m01_couplers_to_m01_couplers_ARBURST; - wire m01_couplers_to_m01_couplers_ARCACHE; - wire m01_couplers_to_m01_couplers_ARLEN; - wire m01_couplers_to_m01_couplers_ARLOCK; wire m01_couplers_to_m01_couplers_ARPROT; - wire m01_couplers_to_m01_couplers_ARQOS; wire m01_couplers_to_m01_couplers_ARREADY; - wire m01_couplers_to_m01_couplers_ARREGION; - wire m01_couplers_to_m01_couplers_ARSIZE; wire m01_couplers_to_m01_couplers_ARVALID; wire m01_couplers_to_m01_couplers_AWADDR; - wire m01_couplers_to_m01_couplers_AWBURST; - wire m01_couplers_to_m01_couplers_AWCACHE; - wire m01_couplers_to_m01_couplers_AWLEN; - wire m01_couplers_to_m01_couplers_AWLOCK; wire m01_couplers_to_m01_couplers_AWPROT; - wire m01_couplers_to_m01_couplers_AWQOS; wire m01_couplers_to_m01_couplers_AWREADY; - wire m01_couplers_to_m01_couplers_AWREGION; - wire m01_couplers_to_m01_couplers_AWSIZE; wire m01_couplers_to_m01_couplers_AWVALID; wire m01_couplers_to_m01_couplers_BREADY; wire m01_couplers_to_m01_couplers_BRESP; wire m01_couplers_to_m01_couplers_BVALID; wire m01_couplers_to_m01_couplers_RDATA; - wire m01_couplers_to_m01_couplers_RLAST; wire m01_couplers_to_m01_couplers_RREADY; wire m01_couplers_to_m01_couplers_RRESP; wire m01_couplers_to_m01_couplers_RVALID; wire m01_couplers_to_m01_couplers_WDATA; - wire m01_couplers_to_m01_couplers_WLAST; wire m01_couplers_to_m01_couplers_WREADY; wire m01_couplers_to_m01_couplers_WSTRB; wire m01_couplers_to_m01_couplers_WVALID; assign M_AXI_araddr = m01_couplers_to_m01_couplers_ARADDR; - assign M_AXI_arburst = m01_couplers_to_m01_couplers_ARBURST; - assign M_AXI_arcache = m01_couplers_to_m01_couplers_ARCACHE; - assign M_AXI_arlen = m01_couplers_to_m01_couplers_ARLEN; - assign M_AXI_arlock = m01_couplers_to_m01_couplers_ARLOCK; assign M_AXI_arprot = m01_couplers_to_m01_couplers_ARPROT; - assign M_AXI_arqos = m01_couplers_to_m01_couplers_ARQOS; - assign M_AXI_arregion = m01_couplers_to_m01_couplers_ARREGION; - assign M_AXI_arsize = m01_couplers_to_m01_couplers_ARSIZE; assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID; assign M_AXI_awaddr = m01_couplers_to_m01_couplers_AWADDR; - assign M_AXI_awburst = m01_couplers_to_m01_couplers_AWBURST; - assign M_AXI_awcache = m01_couplers_to_m01_couplers_AWCACHE; - assign M_AXI_awlen = m01_couplers_to_m01_couplers_AWLEN; - assign M_AXI_awlock = m01_couplers_to_m01_couplers_AWLOCK; assign M_AXI_awprot = m01_couplers_to_m01_couplers_AWPROT; - assign M_AXI_awqos = m01_couplers_to_m01_couplers_AWQOS; - assign M_AXI_awregion = m01_couplers_to_m01_couplers_AWREGION; - assign M_AXI_awsize = m01_couplers_to_m01_couplers_AWSIZE; assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID; assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY; assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY; assign M_AXI_wdata = m01_couplers_to_m01_couplers_WDATA; - assign M_AXI_wlast = m01_couplers_to_m01_couplers_WLAST; assign M_AXI_wstrb = m01_couplers_to_m01_couplers_WSTRB; assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID; assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY; @@ -569,42 +474,25 @@ module m01_couplers_imp_SHET14 assign S_AXI_bresp = m01_couplers_to_m01_couplers_BRESP; assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID; assign S_AXI_rdata = m01_couplers_to_m01_couplers_RDATA; - assign S_AXI_rlast = m01_couplers_to_m01_couplers_RLAST; assign S_AXI_rresp = m01_couplers_to_m01_couplers_RRESP; assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID; assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY; assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr; - assign m01_couplers_to_m01_couplers_ARBURST = S_AXI_arburst; - assign m01_couplers_to_m01_couplers_ARCACHE = S_AXI_arcache; - assign m01_couplers_to_m01_couplers_ARLEN = S_AXI_arlen; - assign m01_couplers_to_m01_couplers_ARLOCK = S_AXI_arlock; assign m01_couplers_to_m01_couplers_ARPROT = S_AXI_arprot; - assign m01_couplers_to_m01_couplers_ARQOS = S_AXI_arqos; assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready; - assign m01_couplers_to_m01_couplers_ARREGION = S_AXI_arregion; - assign m01_couplers_to_m01_couplers_ARSIZE = S_AXI_arsize; assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid; assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr; - assign m01_couplers_to_m01_couplers_AWBURST = S_AXI_awburst; - assign m01_couplers_to_m01_couplers_AWCACHE = S_AXI_awcache; - assign m01_couplers_to_m01_couplers_AWLEN = S_AXI_awlen; - assign m01_couplers_to_m01_couplers_AWLOCK = S_AXI_awlock; assign m01_couplers_to_m01_couplers_AWPROT = S_AXI_awprot; - assign m01_couplers_to_m01_couplers_AWQOS = S_AXI_awqos; assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready; - assign m01_couplers_to_m01_couplers_AWREGION = S_AXI_awregion; - assign m01_couplers_to_m01_couplers_AWSIZE = S_AXI_awsize; assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid; assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready; assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp; assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid; assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata; - assign m01_couplers_to_m01_couplers_RLAST = M_AXI_rlast; assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready; assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp; assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid; assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata; - assign m01_couplers_to_m01_couplers_WLAST = S_AXI_wlast; assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready; assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb; assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid; @@ -1311,7 +1199,6 @@ module system_bd .M01_AXI_bresp(1'b0), .M01_AXI_bvalid(1'b0), .M01_AXI_rdata(1'b0), - .M01_AXI_rlast(1'b0), .M01_AXI_rresp(1'b0), .M01_AXI_rvalid(1'b0), .M01_AXI_wready(1'b0), @@ -1514,37 +1401,21 @@ module system_bd_axi_interconnect_0 M01_ACLK, M01_ARESETN, M01_AXI_araddr, - M01_AXI_arburst, - M01_AXI_arcache, - M01_AXI_arlen, - M01_AXI_arlock, M01_AXI_arprot, - M01_AXI_arqos, M01_AXI_arready, - M01_AXI_arregion, - M01_AXI_arsize, M01_AXI_arvalid, M01_AXI_awaddr, - M01_AXI_awburst, - M01_AXI_awcache, - M01_AXI_awlen, - M01_AXI_awlock, M01_AXI_awprot, - M01_AXI_awqos, M01_AXI_awready, - M01_AXI_awregion, - M01_AXI_awsize, M01_AXI_awvalid, M01_AXI_bready, M01_AXI_bresp, M01_AXI_bvalid, M01_AXI_rdata, - M01_AXI_rlast, M01_AXI_rready, M01_AXI_rresp, M01_AXI_rvalid, M01_AXI_wdata, - M01_AXI_wlast, M01_AXI_wready, M01_AXI_wstrb, M01_AXI_wvalid, @@ -1614,37 +1485,21 @@ module system_bd_axi_interconnect_0 input M01_ACLK; input M01_ARESETN; output M01_AXI_araddr; - output M01_AXI_arburst; - output M01_AXI_arcache; - output M01_AXI_arlen; - output M01_AXI_arlock; output M01_AXI_arprot; - output M01_AXI_arqos; input M01_AXI_arready; - output M01_AXI_arregion; - output M01_AXI_arsize; output M01_AXI_arvalid; output M01_AXI_awaddr; - output M01_AXI_awburst; - output M01_AXI_awcache; - output M01_AXI_awlen; - output M01_AXI_awlock; output M01_AXI_awprot; - output M01_AXI_awqos; input M01_AXI_awready; - output M01_AXI_awregion; - output M01_AXI_awsize; output M01_AXI_awvalid; output M01_AXI_bready; input M01_AXI_bresp; input M01_AXI_bvalid; input M01_AXI_rdata; - input M01_AXI_rlast; output M01_AXI_rready; input M01_AXI_rresp; input M01_AXI_rvalid; output M01_AXI_wdata; - output M01_AXI_wlast; input M01_AXI_wready; output M01_AXI_wstrb; output M01_AXI_wvalid; @@ -1730,37 +1585,21 @@ module system_bd_axi_interconnect_0 wire [3:0]m00_couplers_to_axi_interconnect_WSTRB; wire m00_couplers_to_axi_interconnect_WVALID; wire m01_couplers_to_axi_interconnect_ARADDR; - wire m01_couplers_to_axi_interconnect_ARBURST; - wire m01_couplers_to_axi_interconnect_ARCACHE; - wire m01_couplers_to_axi_interconnect_ARLEN; - wire m01_couplers_to_axi_interconnect_ARLOCK; wire m01_couplers_to_axi_interconnect_ARPROT; - wire m01_couplers_to_axi_interconnect_ARQOS; wire m01_couplers_to_axi_interconnect_ARREADY; - wire m01_couplers_to_axi_interconnect_ARREGION; - wire m01_couplers_to_axi_interconnect_ARSIZE; wire m01_couplers_to_axi_interconnect_ARVALID; wire m01_couplers_to_axi_interconnect_AWADDR; - wire m01_couplers_to_axi_interconnect_AWBURST; - wire m01_couplers_to_axi_interconnect_AWCACHE; - wire m01_couplers_to_axi_interconnect_AWLEN; - wire m01_couplers_to_axi_interconnect_AWLOCK; wire m01_couplers_to_axi_interconnect_AWPROT; - wire m01_couplers_to_axi_interconnect_AWQOS; wire m01_couplers_to_axi_interconnect_AWREADY; - wire m01_couplers_to_axi_interconnect_AWREGION; - wire m01_couplers_to_axi_interconnect_AWSIZE; wire m01_couplers_to_axi_interconnect_AWVALID; wire m01_couplers_to_axi_interconnect_BREADY; wire m01_couplers_to_axi_interconnect_BRESP; wire m01_couplers_to_axi_interconnect_BVALID; wire m01_couplers_to_axi_interconnect_RDATA; - wire m01_couplers_to_axi_interconnect_RLAST; wire m01_couplers_to_axi_interconnect_RREADY; wire m01_couplers_to_axi_interconnect_RRESP; wire m01_couplers_to_axi_interconnect_RVALID; wire m01_couplers_to_axi_interconnect_WDATA; - wire m01_couplers_to_axi_interconnect_WLAST; wire m01_couplers_to_axi_interconnect_WREADY; wire m01_couplers_to_axi_interconnect_WSTRB; wire m01_couplers_to_axi_interconnect_WVALID; @@ -1868,29 +1707,14 @@ module system_bd_axi_interconnect_0 assign M00_AXI_wstrb[3:0] = m00_couplers_to_axi_interconnect_WSTRB; assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_WVALID; assign M01_AXI_araddr = m01_couplers_to_axi_interconnect_ARADDR; - assign M01_AXI_arburst = m01_couplers_to_axi_interconnect_ARBURST; - assign M01_AXI_arcache = m01_couplers_to_axi_interconnect_ARCACHE; - assign M01_AXI_arlen = m01_couplers_to_axi_interconnect_ARLEN; - assign M01_AXI_arlock = m01_couplers_to_axi_interconnect_ARLOCK; assign M01_AXI_arprot = m01_couplers_to_axi_interconnect_ARPROT; - assign M01_AXI_arqos = m01_couplers_to_axi_interconnect_ARQOS; - assign M01_AXI_arregion = m01_couplers_to_axi_interconnect_ARREGION; - assign M01_AXI_arsize = m01_couplers_to_axi_interconnect_ARSIZE; assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_ARVALID; assign M01_AXI_awaddr = m01_couplers_to_axi_interconnect_AWADDR; - assign M01_AXI_awburst = m01_couplers_to_axi_interconnect_AWBURST; - assign M01_AXI_awcache = m01_couplers_to_axi_interconnect_AWCACHE; - assign M01_AXI_awlen = m01_couplers_to_axi_interconnect_AWLEN; - assign M01_AXI_awlock = m01_couplers_to_axi_interconnect_AWLOCK; assign M01_AXI_awprot = m01_couplers_to_axi_interconnect_AWPROT; - assign M01_AXI_awqos = m01_couplers_to_axi_interconnect_AWQOS; - assign M01_AXI_awregion = m01_couplers_to_axi_interconnect_AWREGION; - assign M01_AXI_awsize = m01_couplers_to_axi_interconnect_AWSIZE; assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_AWVALID; assign M01_AXI_bready = m01_couplers_to_axi_interconnect_BREADY; assign M01_AXI_rready = m01_couplers_to_axi_interconnect_RREADY; assign M01_AXI_wdata = m01_couplers_to_axi_interconnect_WDATA; - assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_WLAST; assign M01_AXI_wstrb = m01_couplers_to_axi_interconnect_WSTRB; assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_WVALID; assign M02_AXI_araddr[31:0] = m02_couplers_to_axi_interconnect_ARADDR; @@ -1936,7 +1760,6 @@ module system_bd_axi_interconnect_0 assign m01_couplers_to_axi_interconnect_BRESP = M01_AXI_bresp; assign m01_couplers_to_axi_interconnect_BVALID = M01_AXI_bvalid; assign m01_couplers_to_axi_interconnect_RDATA = M01_AXI_rdata; - assign m01_couplers_to_axi_interconnect_RLAST = M01_AXI_rlast; assign m01_couplers_to_axi_interconnect_RRESP = M01_AXI_rresp; assign m01_couplers_to_axi_interconnect_RVALID = M01_AXI_rvalid; assign m01_couplers_to_axi_interconnect_WREADY = M01_AXI_wready; @@ -1995,63 +1818,33 @@ module system_bd_axi_interconnect_0 (.M_ACLK(axi_interconnect_ACLK_net), .M_ARESETN(axi_interconnect_ARESETN_net), .M_AXI_araddr(m01_couplers_to_axi_interconnect_ARADDR), - .M_AXI_arburst(m01_couplers_to_axi_interconnect_ARBURST), - .M_AXI_arcache(m01_couplers_to_axi_interconnect_ARCACHE), - .M_AXI_arlen(m01_couplers_to_axi_interconnect_ARLEN), - .M_AXI_arlock(m01_couplers_to_axi_interconnect_ARLOCK), .M_AXI_arprot(m01_couplers_to_axi_interconnect_ARPROT), - .M_AXI_arqos(m01_couplers_to_axi_interconnect_ARQOS), .M_AXI_arready(m01_couplers_to_axi_interconnect_ARREADY), - .M_AXI_arregion(m01_couplers_to_axi_interconnect_ARREGION), - .M_AXI_arsize(m01_couplers_to_axi_interconnect_ARSIZE), .M_AXI_arvalid(m01_couplers_to_axi_interconnect_ARVALID), .M_AXI_awaddr(m01_couplers_to_axi_interconnect_AWADDR), - .M_AXI_awburst(m01_couplers_to_axi_interconnect_AWBURST), - .M_AXI_awcache(m01_couplers_to_axi_interconnect_AWCACHE), - .M_AXI_awlen(m01_couplers_to_axi_interconnect_AWLEN), - .M_AXI_awlock(m01_couplers_to_axi_interconnect_AWLOCK), .M_AXI_awprot(m01_couplers_to_axi_interconnect_AWPROT), - .M_AXI_awqos(m01_couplers_to_axi_interconnect_AWQOS), .M_AXI_awready(m01_couplers_to_axi_interconnect_AWREADY), - .M_AXI_awregion(m01_couplers_to_axi_interconnect_AWREGION), - .M_AXI_awsize(m01_couplers_to_axi_interconnect_AWSIZE), .M_AXI_awvalid(m01_couplers_to_axi_interconnect_AWVALID), .M_AXI_bready(m01_couplers_to_axi_interconnect_BREADY), .M_AXI_bresp(m01_couplers_to_axi_interconnect_BRESP), .M_AXI_bvalid(m01_couplers_to_axi_interconnect_BVALID), .M_AXI_rdata(m01_couplers_to_axi_interconnect_RDATA), - .M_AXI_rlast(m01_couplers_to_axi_interconnect_RLAST), .M_AXI_rready(m01_couplers_to_axi_interconnect_RREADY), .M_AXI_rresp(m01_couplers_to_axi_interconnect_RRESP), .M_AXI_rvalid(m01_couplers_to_axi_interconnect_RVALID), .M_AXI_wdata(m01_couplers_to_axi_interconnect_WDATA), - .M_AXI_wlast(m01_couplers_to_axi_interconnect_WLAST), .M_AXI_wready(m01_couplers_to_axi_interconnect_WREADY), .M_AXI_wstrb(m01_couplers_to_axi_interconnect_WSTRB), .M_AXI_wvalid(m01_couplers_to_axi_interconnect_WVALID), .S_ACLK(axi_interconnect_ACLK_net), .S_ARESETN(axi_interconnect_ARESETN_net), .S_AXI_araddr(xbar_to_m01_couplers_ARADDR[32]), - .S_AXI_arburst(1'b0), - .S_AXI_arcache(1'b0), - .S_AXI_arlen(1'b0), - .S_AXI_arlock(1'b0), .S_AXI_arprot(xbar_to_m01_couplers_ARPROT[3]), - .S_AXI_arqos(1'b0), .S_AXI_arready(xbar_to_m01_couplers_ARREADY), - .S_AXI_arregion(1'b0), - .S_AXI_arsize(1'b0), .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID), .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[32]), - .S_AXI_awburst(1'b0), - .S_AXI_awcache(1'b0), - .S_AXI_awlen(1'b0), - .S_AXI_awlock(1'b0), .S_AXI_awprot(xbar_to_m01_couplers_AWPROT[3]), - .S_AXI_awqos(1'b0), .S_AXI_awready(xbar_to_m01_couplers_AWREADY), - .S_AXI_awregion(1'b0), - .S_AXI_awsize(1'b0), .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID), .S_AXI_bready(xbar_to_m01_couplers_BREADY), .S_AXI_bresp(xbar_to_m01_couplers_BRESP), @@ -2061,7 +1854,6 @@ module system_bd_axi_interconnect_0 .S_AXI_rresp(xbar_to_m01_couplers_RRESP), .S_AXI_rvalid(xbar_to_m01_couplers_RVALID), .S_AXI_wdata(xbar_to_m01_couplers_WDATA[32]), - .S_AXI_wlast(1'b0), .S_AXI_wready(xbar_to_m01_couplers_WREADY), .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB[4]), .S_AXI_wvalid(xbar_to_m01_couplers_WVALID)); diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bmm b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bmm index 1da263fb..6ed0172a 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bmm +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bmm @@ -1,11 +1,11 @@ WORKFLOW_OPERATION simulation,dialog; -DEFINE_MEMORY_TYPE microblaze_ps_local_memory_lmb_bram_256K_3_MEM_DEVICE [0x00040000] 32; +DEFINE_MEMORY_TYPE microblaze_ps_local_memory_lmb_bram_MEM_DEVICE [0x00040000] 32; ADDRESS_MAP microblaze_ps MICROBLAZE-LE 100 microblaze_ps - ADDRESS_SPACE microblaze_ps_local_memory_lmb_bram_256K_3_ADDR_SPACE microblaze_ps_local_memory_lmb_bram_256K_3_MEM_DEVICE [0x00000000:0x0003FFFF] microblaze_ps_local_memory/dlmb_bram_if_cntlr + ADDRESS_SPACE microblaze_ps_local_memory_lmb_bram_ADDR_SPACE microblaze_ps_local_memory_lmb_bram_MEM_DEVICE [0x00000000:0x0003FFFF] microblaze_ps_local_memory/dlmb_bram_if_cntlr BUS_BLOCK - microblaze_ps_local_memory_lmb_bram_256K_3_BUS_BLK [31:0] INPUT = "system_bd_lmb_bram_0.mem"; + microblaze_ps_local_memory_lmb_bram_BUS_BLK [31:0] INPUT = "system_bd_lmb_bram_0.mem"; END_BUS_BLOCK; END_ADDRESS_SPACE; END_ADDRESS_MAP; diff --git a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bxml b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bxml index f55d06a4..c7453054 100644 --- a/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bxml +++ b/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bxml @@ -2,12 +2,12 @@ Composite Fileset - - - - + + + + - + @@ -15,7 +15,7 @@ - + @@ -23,7 +23,7 @@ - + @@ -31,7 +31,7 @@ - + @@ -39,7 +39,7 @@ - + @@ -47,7 +47,7 @@ - + @@ -55,7 +55,7 @@ - + @@ -63,7 +63,7 @@ - + @@ -71,7 +71,7 @@ - + @@ -79,7 +79,7 @@ - + @@ -87,7 +87,7 @@ - + @@ -95,7 +95,7 @@ - + @@ -103,7 +103,7 @@ - + @@ -111,7 +111,7 @@ - + @@ -119,13 +119,13 @@ - + - + @@ -143,22 +143,22 @@ - + - + - + - + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_cmos.tcl b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam.tcl similarity index 67% rename from projects/datalink_814/dl814_k7_beam/project/dl814_k7_cmos.tcl rename to projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam.tcl index 81d364db..6c4d563a 100644 --- a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_cmos.tcl +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam.tcl @@ -1,9 +1,9 @@ #***************************************************************************************** # Vivado (TM) v2019.1.3 (64-bit) # -# dl814_k7_cmos.tcl: Tcl script for re-creating project 'dl814_k7_cmos' +# dl814_k7_beam.tcl: Tcl script for re-creating project 'dl814_k7_beam' # -# Generated by Vivado on Tue Mar 21 11:22:53 +0800 2023 +# Generated by Vivado on Thu Mar 23 11:33:24 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -18,99 +18,102 @@ # NOTE: In order to use this script for source control purposes, please make sure that the # following files are added to the source control system:- # -# 1. This project restoration tcl script (dl814_k7_cmos.tcl) that was generated. +# 1. This project restoration tcl script (dl814_k7_beam.tcl) that was generated. # # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.srcs/sources_1/ip/ila_tx/ila_tx.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.srcs/sources_1/ip/vio_weight/vio_weight.xci" # # 3. The following remote source files that were added to the original project:- # -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/vio_manual_ctrl/vio_manual_ctrl.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ila_rx_pre/ila_rx_pre.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/vio_cal/vio_cal.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ila_cal/ila_cal.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ila_tx_rx/ila_tx_rx.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/vio_ant_rd/vio_ant_rd.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/vio_rf_rd/vio_rf_rd.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ila_AntCtrl/ila_AntCtrl.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ila_rfcontrl/ila_rfcontrl.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/vio_ant_test/vio_ant_test.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/vio_rfcontrl/vio_rfcontrl.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/atan2_16b/atan2_16b.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/rx_pre_process/rotate_16b/rotate_16b.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/GaussFir_12m/GaussFir_12m.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/data_1p5m/data_1p5m.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ipi-bds/system_bd/system_bd.bd" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/ad9361_clk_gen/ad9361_clk_gen.xci" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/ADF4351_2.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/transmitter/AddrtoWaveform.v" -# "D:/vivado-git/common/ApproxModuli_26bit.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/FRAC1.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/transmitter/GMSK_send.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/INT_ROMb.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/R_CAL_1.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/R_CAL_2.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/R_CAL_3.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/R_CAL_4.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/Sisyif.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/T_CAL.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/accor_mat_formatting.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/accum_cmplx_mat.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/acorr_cmplx_col_vec.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/ad9361_phase_cal_fine.v" -# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v" -# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v" -# "D:/vivado-git/common/adder_tree_ppl.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/adf4371_a.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/adf4371_b.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/ant_rf_ctrl.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/band_rom_a.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/band_rom_b.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/clk_dist.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/ds18b20_temp.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/frac2_rom.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/fre_caliatt.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/mgc_ctrl.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/mod2_rom.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/rx_pre_process.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/spatial_filter.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/spi_master.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/spi_salve.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/Sisyif_src/spi_tx.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ipi-bds/system_bd/hdl/system_bd_wrapper.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/transmitter/tx_control.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/tx_pre_process.v" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/weight_vec_formatting.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/system_top.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/rtl/rx_pre_process/ad9361_phase_cal_coarse.v" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/coe/GaussFir_12m.coe" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/coe/Gaussfir_1p5m.coe" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/coe/cos_8192_18bit.coe" -# "D:/vivado-git/projects/datalink_814/dl814_k7/ip/transmitter/coe/data_1m5.coe" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" -# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" -# "D:/vivado-git/projects/datalink_814/dl814_k7/constraints/k7401t_ad9516_2ad9361_physical.xdc" -# "D:/vivado-git/projects/datalink_814/dl814_k7/constraints/k7410t_ad9516_2ad9361_timing.xdc" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/system_bd.bd" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/ADF4351_2.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/transmitter/AddrtoWaveform.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/FRAC1.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/transmitter/GMSK_send.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/INT_ROMb.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/R_CAL_1.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/R_CAL_2.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/R_CAL_3.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/R_CAL_4.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/Sisyif.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/T_CAL.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/ad9361_phase_cal_coarse.v" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v" +# "/home/josh/Workspace/vivado-git/common/adder_tree_ppl.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/adf4371_a.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/adf4371_b.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/ant_rf_ctrl.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/band_rom_a.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/band_rom_b.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/clk_dist.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/ds18b20_temp.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/frac2_rom.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/fre_caliatt.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/mgc_ctrl.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/mod2_rom.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/rx_pre_process.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/spatial_filter.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/spi_master.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/spi_salve.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/Sisyif_src/spi_tx.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hdl/system_bd_wrapper.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/transmitter/tx_control.v" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/system_top.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/tx_pre_process.v" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/coe/cos_8192_18bit.coe" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/coe/GaussFir_12m.coe" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/coe/data_1m5.coe" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/coe/Gaussfir_1p5m.coe" +# "/home/josh/Workspace/vivado-git/common/ApproxModuli_26bit.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/accor_mat_formatting.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/accum_cmplx_mat.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/acorr_cmplx_col_vec.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/ad9361_phase_cal_fine.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/weight_vec_formatting.v" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ad9361_clk_gen/ad9361_clk_gen.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/atan2_16b/atan2_16b.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/data_1p5m/data_1p5m.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/transmitter/GaussFir_12m/GaussFir_12m.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ila_AntCtrl/ila_AntCtrl.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ila_cal/ila_cal.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ila_rfcontrl/ila_rfcontrl.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ila_rx_pre/ila_rx_pre.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ila_tx_rx/ila_tx_rx.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/rx_pre_process/rotate_16b/rotate_16b.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/vio_ant_rd/vio_ant_rd.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/vio_ant_test/vio_ant_test.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/vio_cal/vio_cal.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/vio_rf_rd/vio_rf_rd.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/vio_rfcontrl/vio_rfcontrl.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/ila_rx_1/ila_rx.xci" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/constraints/k7401t_ad9516_2ad9361_physical.xdc" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/constraints/k7410t_ad9516_2ad9361_timing.xdc" +# "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/testbenches/tb_rx_pre.v" # #***************************************************************************************** @@ -123,7 +126,7 @@ if { [info exists ::origin_dir_loc] } { } # Set the project name -set _xil_proj_name_ "dl814_k7_cmos" +set _xil_proj_name_ "dl814_k7_beam" # Use project name variable, if specified in the tcl shell if { [info exists ::user_project_name] } { @@ -131,7 +134,7 @@ if { [info exists ::user_project_name] } { } variable script_file -set script_file "dl814_k7_cmos.tcl" +set script_file "dl814_k7_beam.tcl" # Help information for this script proc print_help {} { @@ -179,7 +182,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/dl814_k7_cmos"]" +set orig_proj_dir "[file normalize "$origin_dir/dl814_k7_beam"]" # Create project create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7k410tffg900-2 @@ -189,7 +192,8 @@ set proj_dir [get_property directory [current_project]] # Set project properties set obj [current_project] -set_property -name "compxlib.modelsim_compiled_library_dir" -value "C:/Mentor/CompLib/2019.1.3" -objects $obj +set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/project/Mentor/CompLib/2019.1.3" -objects $obj +set_property -name "compxlib.vcs_compiled_library_dir" -value "/home/josh/Software/Synopsys/CompLib/2019.1" -objects $obj set_property -name "corecontainer.enable" -value "1" -objects $obj set_property -name "default_lib" -value "xil_defaultlib" -objects $obj set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj @@ -208,20 +212,23 @@ set_property -name "dsa.vendor" -value "xilinx" -objects $obj set_property -name "dsa.version" -value "0.0" -objects $obj set_property -name "enable_core_container" -value "1" -objects $obj set_property -name "enable_vhdl_2008" -value "1" -objects $obj -set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_cache_permissions" -value "disable" -objects $obj set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj set_property -name "part" -value "xc7k410tffg900-2" -objects $obj set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "39" -objects $obj -set_property -name "webtalk.ies_export_sim" -value "39" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "39" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "39" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "39" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "39" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "39" -objects $obj +set_property -name "target_simulator" -value "VCS" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "77" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "77" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "77" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "77" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "77" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "77" -objects $obj +set_property -name "webtalk.vcs_launch_sim" -value "9" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "3" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "77" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -229,53 +236,12 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { create_fileset -srcset sources_1 } -# Set IP repository paths -set obj [get_filesets sources_1] -set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../../adi_library"]" $obj - -# Rebuild user ip_repo's index before adding any source files -update_ip_catalog -rebuild - # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ - [file normalize "${origin_dir}/../ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ - [file normalize "${origin_dir}/../ip/ila_rx_pre/ila_rx_pre.xci"] \ - [file normalize "${origin_dir}/../ip/vio_cal/vio_cal.xci"] \ - [file normalize "${origin_dir}/../ip/ila_cal/ila_cal.xci"] \ - [file normalize "${origin_dir}/../ip/ila_tx_rx/ila_tx_rx.xci"] \ - [file normalize "${origin_dir}/../ip/vio_ant_rd/vio_ant_rd.xci"] \ - [file normalize "${origin_dir}/../ip/vio_rf_rd/vio_rf_rd.xci"] \ - [file normalize "${origin_dir}/../ip/ila_AntCtrl/ila_AntCtrl.xci"] \ - [file normalize "${origin_dir}/../ip/ila_rfcontrl/ila_rfcontrl.xci"] \ - [file normalize "${origin_dir}/../ip/vio_ant_test/vio_ant_test.xci"] \ - [file normalize "${origin_dir}/../ip/vio_rfcontrl/vio_rfcontrl.xci"] \ - [file normalize "${origin_dir}/../ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \ - [file normalize "${origin_dir}/../ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"] \ - [file normalize "${origin_dir}/../ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci"] \ - [file normalize "${origin_dir}/../ip/transmitter/GaussFir_12m/GaussFir_12m.xci"] \ - [file normalize "${origin_dir}/../ip/transmitter/data_1p5m/data_1p5m.xci"] \ - [file normalize "${origin_dir}/../ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci"] \ - [file normalize "${origin_dir}/../ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci"] \ [file normalize "${origin_dir}/../ipi-bds/system_bd/system_bd.bd"] \ - [file normalize "${origin_dir}/../ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"] \ - [file normalize "${origin_dir}/../ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"] \ - [file normalize "${origin_dir}/../ip/ad9361_clk_gen/ad9361_clk_gen.xci"] \ [file normalize "${origin_dir}/../rtl/Sisyif_src/ADF4351_2.v"] \ [file normalize "${origin_dir}/../rtl/transmitter/AddrtoWaveform.v"] \ - [file normalize "${origin_dir}/../../../../common/ApproxModuli_26bit.v"] \ [file normalize "${origin_dir}/../rtl/Sisyif_src/FRAC1.v"] \ [file normalize "${origin_dir}/../rtl/transmitter/GMSK_send.v"] \ [file normalize "${origin_dir}/../rtl/Sisyif_src/INT_ROMb.v"] \ @@ -285,10 +251,7 @@ set files [list \ [file normalize "${origin_dir}/../rtl/Sisyif_src/R_CAL_4.v"] \ [file normalize "${origin_dir}/../rtl/Sisyif_src/Sisyif.v"] \ [file normalize "${origin_dir}/../rtl/Sisyif_src/T_CAL.v"] \ - [file normalize "${origin_dir}/../rtl/rx_pre_process/accor_mat_formatting.v"] \ - [file normalize "${origin_dir}/../rtl/rx_pre_process/accum_cmplx_mat.v"] \ - [file normalize "${origin_dir}/../rtl/rx_pre_process/acorr_cmplx_col_vec.v"] \ - [file normalize "${origin_dir}/../rtl/rx_pre_process/ad9361_phase_cal_fine.v"] \ + [file normalize "${origin_dir}/../rtl/rx_pre_process/ad9361_phase_cal_coarse.v"] \ [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"] \ [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"] \ [file normalize "${origin_dir}/../../../../common/adder_tree_ppl.v"] \ @@ -310,314 +273,50 @@ set files [list \ [file normalize "${origin_dir}/../rtl/Sisyif_src/spi_tx.v"] \ [file normalize "${origin_dir}/../ipi-bds/system_bd/hdl/system_bd_wrapper.v"] \ [file normalize "${origin_dir}/../rtl/transmitter/tx_control.v"] \ - [file normalize "${origin_dir}/../rtl/tx_pre_process.v"] \ [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ - [file normalize "${origin_dir}/../rtl/rx_pre_process/weight_vec_formatting.v"] \ [file normalize "${origin_dir}/../rtl/system_top.v"] \ - [file normalize "${origin_dir}/../rtl/rx_pre_process/ad9361_phase_cal_coarse.v"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/GaussFir_12m.coe"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/Gaussfir_1p5m.coe"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/cos_8192_18bit.coe"] \ - [file normalize "${origin_dir}/../ip/transmitter/coe/data_1m5.coe"] \ - [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/../rtl/tx_pre_process.v"] \ [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/cos_8192_18bit.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/GaussFir_12m.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/data_1m5.coe"] \ + [file normalize "${origin_dir}/../ip/transmitter/coe/Gaussfir_1p5m.coe"] \ + [file normalize "${origin_dir}/../../../../common/ApproxModuli_26bit.v"] \ + [file normalize "${origin_dir}/../rtl/rx_pre_process/accor_mat_formatting.v"] \ + [file normalize "${origin_dir}/../rtl/rx_pre_process/accum_cmplx_mat.v"] \ + [file normalize "${origin_dir}/../rtl/rx_pre_process/acorr_cmplx_col_vec.v"] \ + [file normalize "${origin_dir}/../rtl/rx_pre_process/ad9361_phase_cal_fine.v"] \ + [file normalize "${origin_dir}/../rtl/rx_pre_process/weight_vec_formatting.v"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../ip/vio_manual_ctrl/vio_manual_ctrl.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/ila_rx_pre/ila_rx_pre.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/vio_cal/vio_cal.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/ila_cal/ila_cal.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/ila_tx_rx/ila_tx_rx.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/vio_ant_rd/vio_ant_rd.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/vio_rf_rd/vio_rf_rd.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/ila_AntCtrl/ila_AntCtrl.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/ila_rfcontrl/ila_rfcontrl.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/vio_ant_test/vio_ant_test.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/vio_rfcontrl/vio_rfcontrl.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/atan2_16b/atan2_16b.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/rx_pre_process/rotate_16b/rotate_16b.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/transmitter/GaussFir_12m/GaussFir_12m.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/transmitter/data_1p5m/data_1p5m.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - -set file "$origin_dir/../ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - set file "$origin_dir/../ipi-bds/system_bd/system_bd.bd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "registered_with_manager" -value "1" -objects $file_obj - -set file "$origin_dir/../ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj + set_property -name "is_locked" -value "1" -objects $file_obj } - -set file "$origin_dir/../ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ad9361_clk_gen/ad9361_clk_gen.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files set file "$origin_dir/../ip/ad9361_clk_gen/ad9361_clk_gen.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -631,9 +330,740 @@ if { ![get_property "is_locked" $file_obj] } { # Set 'sources_1' fileset file properties for local files # None -# Set 'sources_1' fileset properties +# Set 'sources_1' fileset object set obj [get_filesets sources_1] -set_property -name "top" -value "system_top" -objects $obj +set files [list \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/atan2_16b/atan2_16b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/transmitter/data_1p5m/data_1p5m.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/transmitter/data_1p5m/data_1p5m.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/transmitter/GaussFir_12m/GaussFir_12m.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/transmitter/GaussFir_12m/GaussFir_12m.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ila_AntCtrl/ila_AntCtrl.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ila_AntCtrl/ila_AntCtrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ila_cal/ila_cal.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ila_cal/ila_cal.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ila_rfcontrl/ila_rfcontrl.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ila_rfcontrl/ila_rfcontrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ila_rx_pre/ila_rx_pre.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ila_rx_pre/ila_rx_pre.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ila_tx_rx/ila_tx_rx.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ila_tx_rx/ila_tx_rx.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/ram_hop_data/ram_hop_data.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/rx_pre_process/rotate_16b/rotate_16b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/vio_ant_rd/vio_ant_rd.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/vio_ant_rd/vio_ant_rd.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/vio_ant_test/vio_ant_test.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/vio_ant_test/vio_ant_test.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/vio_cal/vio_cal.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/vio_cal/vio_cal.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/vio_clk_ld_rd/vio_clk_ld_rd.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/vio_manual_ctrl/vio_manual_ctrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/vio_rf_rd/vio_rf_rd.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/vio_rf_rd/vio_rf_rd.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/vio_rfcontrl/vio_rfcontrl.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/vio_rfcontrl/vio_rfcontrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../ip/ila_rx_1/ila_rx.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/ila_rx_1/ila_rx.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/dl814_k7_beam/dl814_k7_beam.srcs/sources_1/ip/ila_tx/ila_tx.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "ila_tx/ila_tx.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/dl814_k7_beam/dl814_k7_beam.srcs/sources_1/ip/vio_weight/vio_weight.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "vio_weight/vio_weight.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + # Create 'constrs_1' fileset (if not found) if {[string equal [get_filesets -quiet constrs_1] ""]} { @@ -670,12 +1100,25 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] -# Empty (no sources present) +set files [list \ + [file normalize "${origin_dir}/../testbenches/tb_rx_pre.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None # Set 'sim_1' fileset properties set obj [get_filesets sim_1] -set_property -name "top" -value "system_top" -objects $obj +set_property -name "top" -value "tb_rx_pre" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "vcs.compile.vlogan.more_options" -value "-v2005 -kdb" -objects $obj +set_property -name "vcs.elaborate.debug_pp" -value "0" -objects $obj +set_property -name "vcs.elaborate.vcs.more_options" -value "-debug_access+all" -objects $obj # Set 'utils_1' fileset object set obj [get_filesets utils_1] diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_cmos/dl814_k7_cmos.hw/dl814_k7_cmos.lpr b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.hw/dl814_k7_beam.lpr similarity index 100% rename from projects/datalink_814/dl814_k7_beam/project/dl814_k7_cmos/dl814_k7_cmos.hw/dl814_k7_cmos.lpr rename to projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.hw/dl814_k7_beam.lpr diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.runs/impl_1/debug_nets.ltx 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"weight_ch2_q[15]" + }, + { + "name": "weight_ch2_q[14]" + }, + { + "name": "weight_ch2_q[13]" + }, + { + "name": "weight_ch2_q[12]" + }, + { + "name": "weight_ch2_q[11]" + }, + { + "name": "weight_ch2_q[10]" + }, + { + "name": "weight_ch2_q[9]" + }, + { + "name": "weight_ch2_q[8]" + }, + { + "name": "weight_ch2_q[7]" + }, + { + "name": "weight_ch2_q[6]" + }, + { + "name": "weight_ch2_q[5]" + }, + { + "name": "weight_ch2_q[4]" + }, + { + "name": "weight_ch2_q[3]" + }, + { + "name": "weight_ch2_q[2]" + }, + { + "name": "weight_ch2_q[1]" + }, + { + "name": "weight_ch2_q[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 119, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 4, + "nets": [ + { + "name": "weight_ch3_i", + "isBus": true, + "subnets": [ + { + "name": "weight_ch3_i[15]" + }, + { + "name": "weight_ch3_i[14]" + }, + { + "name": "weight_ch3_i[13]" + }, + { + "name": "weight_ch3_i[12]" + }, + { + "name": "weight_ch3_i[11]" + }, + { + "name": "weight_ch3_i[10]" + }, + { + "name": "weight_ch3_i[9]" + }, + { + "name": "weight_ch3_i[8]" + }, + { + "name": "weight_ch3_i[7]" + }, + { + "name": "weight_ch3_i[6]" + }, + { + "name": "weight_ch3_i[5]" + }, + { + "name": "weight_ch3_i[4]" + }, + { + "name": "weight_ch3_i[3]" + }, + { + "name": "weight_ch3_i[2]" + }, + { + "name": "weight_ch3_i[1]" + }, + { + "name": "weight_ch3_i[0]" + } + ] + } + ] + }, + { + "name": "probe_out5", + "id": 120, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 5, + "nets": [ + { + "name": "weight_ch3_q", + "isBus": true, + "subnets": [ + { + "name": "weight_ch3_q[15]" + }, + { + "name": "weight_ch3_q[14]" + }, + { + "name": "weight_ch3_q[13]" + }, + { + "name": "weight_ch3_q[12]" + }, + { + "name": "weight_ch3_q[11]" + }, + { + "name": "weight_ch3_q[10]" + }, + { + "name": "weight_ch3_q[9]" + }, + { + "name": "weight_ch3_q[8]" + }, + { + "name": "weight_ch3_q[7]" + }, + { + "name": "weight_ch3_q[6]" + }, + { + "name": "weight_ch3_q[5]" + }, + { + "name": "weight_ch3_q[4]" + }, + { + "name": "weight_ch3_q[3]" + }, + { + "name": "weight_ch3_q[2]" + }, + { + "name": "weight_ch3_q[1]" + }, + { + "name": "weight_ch3_q[0]" + } + ] + } + ] + }, + { + "name": "probe_out6", + "id": 121, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 6, + "nets": [ + { + "name": "weight_ch4_i", + "isBus": true, + "subnets": [ + { + "name": "weight_ch4_i[15]" + }, + { + "name": "weight_ch4_i[14]" + }, + { + "name": "weight_ch4_i[13]" + }, + { + "name": "weight_ch4_i[12]" + }, + { + "name": "weight_ch4_i[11]" + }, + { + "name": "weight_ch4_i[10]" + }, + { + "name": "weight_ch4_i[9]" + }, + { + "name": "weight_ch4_i[8]" + }, + { + "name": "weight_ch4_i[7]" + }, + { + "name": "weight_ch4_i[6]" + }, + { + "name": "weight_ch4_i[5]" + }, + { + "name": "weight_ch4_i[4]" + }, + { + "name": "weight_ch4_i[3]" + }, + { + "name": "weight_ch4_i[2]" + }, + { + "name": "weight_ch4_i[1]" + }, + { + "name": "weight_ch4_i[0]" + } + ] + } + ] + }, + { + "name": "probe_out7", + "id": 122, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 7, + "nets": [ + { + "name": "weight_ch4_q", + "isBus": true, + "subnets": [ + { + "name": "weight_ch4_q[15]" + }, + { + "name": "weight_ch4_q[14]" + }, + { + "name": "weight_ch4_q[13]" + }, + { + "name": "weight_ch4_q[12]" + }, + { + "name": "weight_ch4_q[11]" + }, + { + "name": "weight_ch4_q[10]" + }, + { + "name": "weight_ch4_q[9]" + }, + { + "name": "weight_ch4_q[8]" + }, + { + "name": "weight_ch4_q[7]" + }, + { + "name": "weight_ch4_q[6]" + }, + { + "name": "weight_ch4_q[5]" + }, + { + "name": "weight_ch4_q[4]" + }, + { + "name": "weight_ch4_q[3]" + }, + { + "name": "weight_ch4_q[2]" + }, + { + "name": "weight_ch4_q[1]" + }, + { + "name": "weight_ch4_q[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/SDK.log b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/SDK.log new file mode 100644 index 00000000..4ba538fa --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/SDK.log @@ -0,0 +1,6 @@ +11:34:15 INFO : Registering command handlers for SDK TCF services +11:34:16 INFO : Launching XSCT server: xsct -n -interactive /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/temp_xsdb_launch_script.tcl +11:34:18 INFO : XSCT server has started successfully. +11:34:18 INFO : Successfully done setting XSCT server connection channel +11:34:18 INFO : Successfully done setting SDK workspace +11:34:18 INFO : Processing command line option -hwspec /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/system_top.hdf. diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/.cproject b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/.cproject new file mode 100644 index 00000000..fddccb9e --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/.cproject @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/.project b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/.project new file mode 100644 index 00000000..29b3571d --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/.project @@ -0,0 +1,26 @@ + + + dl814_k7_48M + Created by SDK v2019.1. dl814_k7_48M_bsp - microblaze_ps + + dl814_k7_48M_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/README.txt b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/README.txt new file mode 100644 index 00000000..c4d32efe --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/README.txt @@ -0,0 +1 @@ +Empty application. Add your own sources. diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/gpio.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/gpio.c new file mode 100644 index 00000000..9742613d --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/gpio.c @@ -0,0 +1,184 @@ +/***************************************************************************//** + * @file gpio.c + * @brief Implementation of the GPIO Interface + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include "../../include/gpio.h" +#include "../../include/error.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Obtain the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->gpio_ops_get(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Get the value of an optional GPIO. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if (!param || (param->number == -1)) { + *desc = NULL; + return SUCCESS; + } + + if ((param->platform_ops->gpio_ops_get_optional(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} +/** + * @brief Free the resources allocated by gpio_get(). + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_remove(struct gpio_desc *desc) +{ + if (desc) + return desc->platform_ops->gpio_ops_remove(desc); + else + return SUCCESS; +} + +/** + * @brief Enable the input direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_input(struct gpio_desc *desc) +{ + if (desc) + return desc->platform_ops->gpio_ops_direction_input(desc); + else + return SUCCESS; +} + +/** + * @brief Enable the output direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value) +{ + if (desc) + return desc->platform_ops-> + gpio_ops_direction_output(desc, value); + else + return SUCCESS; +} + +/** + * @brief Get the direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param direction - The direction. + * Example: GPIO_OUT + * GPIO_IN + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction) +{ + if (desc) + return desc->platform_ops-> + gpio_ops_get_direction(desc, direction); + else + return SUCCESS; +} + +/** + * @brief Set the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value) +{ + if (desc) + return desc->platform_ops->gpio_ops_set_value(desc, value); + else + return SUCCESS; +} + +/** + * @brief Get the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value) +{ + if (desc) + return desc->platform_ops->gpio_ops_get_value(desc, value); + else + return SUCCESS; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/irq.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/irq.c new file mode 100644 index 00000000..937c57f8 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/irq.c @@ -0,0 +1,153 @@ +/***************************************************************************//** + * @file irq.c + * @brief Implementation of the IRQ Interface + * @author Andrei Porumb (andrei.porumb@analog.com) +******************************************************************************** + * Copyright 2021(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include "../../include/irq.h" +#include "../../include/error.h" + +/** + * @brief Initialize the IRQ interrupts. + * @param desc - The IRQ descriptor. + * @param param - The structure that contains the IRQ parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->init(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by irq_ctrl_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->remove(desc); +} + +/** + * @brief Register a callback to handle the irq events. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param callback_desc - Callback descriptor + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc) +{ + return desc->platform_ops->register_callback(desc, irq_id, callback_desc); +} + +/** + * @brief Unregisters a generic IRQ handling function. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->unregister(desc, irq_id); +} + +/** + * @brief Enable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_global_enable(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->global_enable(desc); +} + +/** + * @brief Disable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_global_disable(struct irq_ctrl_desc *desc) +{ + return desc->platform_ops->global_disable(desc); +} + +/** + * @brief Set interrupt trigger level. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param trig - New trigger level for the interrupt. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig) +{ + if(desc->platform_ops->trigger_level_set) + return desc->platform_ops->trigger_level_set(desc, irq_id, trig); + else + return ENOSYS; +} + +/** + * @brief Enable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->enable(desc, irq_id); +} + +/** + * @brief Disable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + return desc->platform_ops->disable(desc, irq_id); +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/spi.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/spi.c new file mode 100644 index 00000000..c114eda7 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/api/spi.c @@ -0,0 +1,144 @@ +/***************************************************************************//** + * @file spi.c + * @brief Implementation of the SPI Interface + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2020(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include +#include +#include +#include "../../include/spi.h" +#include "../../include/error.h" + +/** + * @brief Initialize the SPI communication peripheral. + * @param desc - The SPI descriptor. + * @param param - The structure that contains the SPI parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + if (!param) + return FAILURE; + + if ((param->platform_ops->init(desc, param))) + return FAILURE; + + (*desc)->platform_ops = param->platform_ops; + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by spi_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_remove(struct spi_desc *desc) +{ + return desc->platform_ops->remove(desc); +} + +/** + * @brief Write and read data to/from SPI. + * @param desc - The SPI descriptor. + * @param data - The buffer with the transmitted/received data. + * @param bytes_number - Number of bytes to write/read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + return desc->platform_ops->write_and_read(desc, data, bytes_number); +} + +/** + * @brief Write and read data to/from SPI in 3 wire mode. + * @param desc - The SPI descriptor. + * @param write_data - The buffer with the transmitted data. + * @param read_data - The buffer with the received data. + * @param write_bytes_number - Number of bytes to write. + * @param read_bytes_number - Number of bytes to read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number) +{ + int ret; + if(desc->platform_ops->write_and_read_3wire != NULL){ + return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data, + write_bytes_number, read_bytes_number); + } + else{ + return FAILURE; + } +} + + +/** + * @brief Iterate over head list and send all spi messages + * @param desc - The SPI descriptor. + * @param msgs - Array of messages. + * @param len - Number of messages in the array. + * @return SUCCESS in case of success, negativ error code otherwise. + */ +int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len) +{ + int32_t ret; + uint32_t i; + + if (!desc || !desc->platform_ops) + return -EINVAL; + + if (desc->platform_ops->transfer) + return desc->platform_ops->transfer(desc, msgs, len); + + for (i = 0; i < len; i++) { + if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff) + return -EINVAL; + ret = spi_write_and_read(desc, msgs[i].rx_buff, + msgs[i].bytes_number); + if (IS_ERR_VALUE(ret)) + return ret; + } + + return SUCCESS; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c new file mode 100644 index 00000000..7964fbf3 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c @@ -0,0 +1,328 @@ +/***************************************************************************//** + * @file axi_dmac.c + * @brief Driver for the Analog Devices AXI-DMAC core. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +#include +#include "../../../include/axi_io.h" +#include "../../../include/error.h" +#include "../axi_dmac/axi_dmac.h" + +/***************************************************************************//** + * @brief dma_isr +*******************************************************************************/ +void axi_dmac_default_isr(void *instance) +{ + struct axi_dmac *dmac = (struct axi_dmac *)instance; + uint32_t remaining_size, burst_size; + uint32_t reg_val; + + /* Get interrupt sources and clear interrupts. */ + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) { + remaining_size = dmac->big_transfer.size - + dmac->big_transfer.size_done; + burst_size = (remaining_size <= dmac->transfer_max_size) ? + remaining_size : dmac->transfer_max_size; + + dmac->big_transfer.size_done += burst_size; + dmac->big_transfer.address += burst_size; + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, + dmac->big_transfer.address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, + dmac->big_transfer.address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return; // Other directions are not supported yet + } + /* The current transfer was started and a new one is queued. */ + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + burst_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } + if (reg_val & AXI_DMAC_IRQ_EOT) { + dmac->big_transfer.transfer_done = true; + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + } +} + +/***************************************************************************//** + * @brief axi_dmac_read + *******************************************************************************/ +int32_t axi_dmac_read(struct axi_dmac *dmac, + uint32_t reg_addr, + uint32_t *reg_data) +{ + axi_io_read(dmac->base, reg_addr, reg_data); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_write + *******************************************************************************/ +int32_t axi_dmac_write(struct axi_dmac *dmac, + uint32_t reg_addr, + uint32_t reg_data) +{ + axi_io_write(dmac->base, reg_addr, reg_data); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_transfer_nonblock + *******************************************************************************/ +int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac, + uint32_t address, uint32_t size) +{ + uint32_t reg_val; + + if (size == 0) + return SUCCESS; /* nothing to do */ + + axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, ®_val); + if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) { + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0); + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0); + } + + axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val); + if (!(reg_val & 1)) { + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return FAILURE; // Other directions are not supported yet + } + if ((size - 1) > dmac->transfer_max_size) { + dmac->big_transfer.address = address; + dmac->big_transfer.size = size - 1; + dmac->big_transfer.size_done = dmac->transfer_max_size; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + dmac->transfer_max_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } else { + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + size - 1); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + } + } else { + return FAILURE; + } + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_is_transfer_ready + *******************************************************************************/ +int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy) +{ + *rdy = dmac->big_transfer.transfer_done; + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_transfer + *******************************************************************************/ +int32_t axi_dmac_transfer(struct axi_dmac *dmac, + uint32_t address, uint32_t size) +{ + uint32_t transfer_id; + uint32_t reg_val; + uint32_t timeout = 0; + + if (size == 0) + return SUCCESS; /* nothing to do */ + + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0); + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); + + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0); + + axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id); + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + switch (dmac->direction) { + case DMA_DEV_TO_MEM: + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0); + break; + case DMA_MEM_TO_DEV: + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address); + axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0); + break; + default: + return FAILURE; // Other directions are not supported yet + } + + if ((size - 1) > dmac->transfer_max_size) { + dmac->big_transfer.address = address; + dmac->big_transfer.size = size - 1; + dmac->big_transfer.size_done = dmac->transfer_max_size; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, + dmac->transfer_max_size); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + + while(!dmac->big_transfer.transfer_done) { + timeout++; + if (timeout == UINT32_MAX) + return FAILURE; + } + + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + + return SUCCESS; + } + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1); + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0); + + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags); + + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1); + + if (dmac->flags & DMA_CYCLIC) + return SUCCESS; + + /* Wait until the new transfer is queued. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val); + } while(reg_val == 1); + + /* Wait until the current transfer is completed. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val); + if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT)) + break; + } while(!dmac->big_transfer.transfer_done); + if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT)) + axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val); + + /* Wait until the transfer with the ID transfer_id is completed. */ + do { + axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, ®_val); + } while((reg_val & (1u << transfer_id)) != (1u << transfer_id)); + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_init + *******************************************************************************/ +int32_t axi_dmac_init(struct axi_dmac **dmac_core, + const struct axi_dmac_init *init) +{ + struct axi_dmac *dmac; + + dmac = (struct axi_dmac *)malloc(sizeof(*dmac)); + if (!dmac) + return FAILURE; + + dmac->name = init->name; + dmac->base = init->base; + dmac->direction = init->direction; + dmac->flags = init->flags; + dmac->transfer_max_size = -1; + dmac->big_transfer.address = 0; + dmac->big_transfer.size = 0; + dmac->big_transfer.size_done = 0; + + axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size); + axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size); + + *dmac_core = dmac; + + return SUCCESS; +} + +/***************************************************************************//** + * @brief axi_dmac_remove + *******************************************************************************/ +int32_t axi_dmac_remove(struct axi_dmac *dmac) +{ + if(!dmac) + return FAILURE; + + free(dmac); + + return SUCCESS; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h new file mode 100644 index 00000000..d7a10858 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h @@ -0,0 +1,124 @@ +/***************************************************************************//** + * @file axi_dmac.h + * @brief Driver for the Analog Devices AXI-DMAC core. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef AXI_DMAC_H_ +#define AXI_DMAC_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/util.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define AXI_DMAC_REG_IRQ_MASK 0x80 +#define AXI_DMAC_REG_IRQ_PENDING 0x84 +#define AXI_DMAC_IRQ_SOT BIT(0) +#define AXI_DMAC_IRQ_EOT BIT(1) + +#define AXI_DMAC_REG_CTRL 0x400 +#define AXI_DMAC_CTRL_ENABLE BIT(0) +#define AXI_DMAC_CTRL_PAUSE BIT(1) + +#define AXI_DMAC_REG_TRANSFER_ID 0x404 +#define AXI_DMAC_REG_START_TRANSFER 0x408 +#define AXI_DMAC_REG_FLAGS 0x40c +#define AXI_DMAC_REG_DEST_ADDRESS 0x410 +#define AXI_DMAC_REG_SRC_ADDRESS 0x414 +#define AXI_DMAC_REG_X_LENGTH 0x418 +#define AXI_DMAC_REG_Y_LENGTH 0x41c +#define AXI_DMAC_REG_DEST_STRIDE 0x420 +#define AXI_DMAC_REG_SRC_STRIDE 0x424 +#define AXI_DMAC_REG_TRANSFER_DONE 0x428 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +enum dma_direction { + DMA_DEV_TO_MEM, + DMA_MEM_TO_DEV +}; + +enum dma_flags { + DMA_CYCLIC = 1, + DMA_LAST = 2 +}; + +struct axi_dma_transfer { + uint32_t size; + uint32_t address; + uint32_t size_done; + volatile bool transfer_done; +}; + +struct axi_dmac { + const char *name; + uint32_t base; + enum dma_direction direction; + uint32_t flags; + uint32_t transfer_max_size; + volatile struct axi_dma_transfer big_transfer; +}; + +struct axi_dmac_init { + const char *name; + uint32_t base; + enum dma_direction direction; + uint32_t flags; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +void axi_dmac_default_isr(void *instance); +int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr, + uint32_t *reg_data); +int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr, + uint32_t reg_data); +int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac, + uint32_t address, uint32_t size); +int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy); +int32_t axi_dmac_transfer(struct axi_dmac *dmac, + uint32_t address, uint32_t size); +int32_t axi_dmac_init(struct axi_dmac **adc_core, + const struct axi_dmac_init *init); +int32_t axi_dmac_remove(struct axi_dmac *dmac); + +#endif diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c new file mode 100644 index 00000000..702d97df --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c @@ -0,0 +1,978 @@ +/******************************************************************************* + * @file spi_engine.c + * @brief Core implementation of the SPI Engine Driver. + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +/* In debug mode the printf function used in displaying the messages is causing +significant delays */ +//#define DEBUG_LEVEL 2 + +#include +#include +#include +#include +#include +#include + +#include "spi_engine.h" +#include "../axi_dmac/axi_dmac.h" +#include "../../../include/axi_io.h" +#include "../../../include/error.h" + +/** + * @brief Spi engine platform specific SPI platform ops structure + */ +const struct spi_platform_ops spi_eng_platform_ops = { + .init = &spi_engine_init, + .write_and_read = &spi_engine_spi_write_and_read, + .write_and_read_3wire = &spi_engine_spi_write_and_read_3wire, + .remove = &spi_engine_remove +}; + +/******************************************************************************/ +/***************************** Static variables *******************************/ +/******************************************************************************/ + +/** + * @brief Static variable used to sync transfers + * + */ +static uint8_t _sync_id = 0x01; + +/******************************************************************************/ +/************************** Functions Implementation **************************/ +/******************************************************************************/ + +/** + * @brief Write SPI Engine's axi registers + * + * @param desc Decriptor containing SPI Engine's parameters + * @param reg_addr The address of the SPI Engine's axi register where the data + * will be written + * @param reg_data Data that will be written + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_write(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t reg_data) +{ + axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data); + + return SUCCESS; +} + +/** + * @brief Read SPI Engine's axi registers + * + * @param desc Decriptor containing SPI Engine's parameters + * @param reg_addr The address of the SPI Engine's axi register from where the + * data where the data will be read + * @param reg_data Pointer where the read that will be stored + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_read(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t *reg_data) +{ + axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data); + return SUCCESS; +} + +/** + * @brief Set width of the transferred word over SPI + * + * @param desc Decriptor containing SPI interface parameters + * @param data_width The desired data width + * The supported values are: + * - 8 + * - 16 + * - 24 + * - 32 + */ +int32_t spi_engine_set_transfer_width(struct spi_desc *desc, + uint8_t data_width) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + if (data_width > desc_extra->max_data_width) + desc_extra->data_width = desc_extra->max_data_width; + else + desc_extra->data_width = data_width; + + return SUCCESS; +} + +/** + * @brief Set SPI engine clock frequency + * + * @param desc Decriptor containing SPI Engine's parameters + * @param speed_hz SPI engine transfer speed + */ +void spi_engine_set_speed(struct spi_desc *desc, + uint32_t speed_hz) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + desc_extra->clk_div = desc_extra->ref_clk_hz / + (2 * speed_hz) - 1; +} + +/** + * @brief Set the number of words transferred in a single transaction + * + * @param desc Decriptor containing SPI Engine's parameters + * @param bytes_number The number of bytes to be converted + * @return uint8_t A number of words in which bytes_number can be grouped + */ +static uint8_t spi_get_words_number(struct spi_engine_desc *desc, + uint8_t bytes_number) +{ + uint8_t xfer_word_len; + uint8_t words_number; + + xfer_word_len = desc->data_width / 8; + words_number = bytes_number / xfer_word_len; + + if ((bytes_number % xfer_word_len) != 0) + words_number++; + + return words_number; +} + +/** + * @brief Get the word length in bytes + * + * @param desc Decriptor containing SPI Engine's parameters + * @return uint8_t Number of bytes that fit in one word + */ +static uint8_t spi_get_word_length(struct spi_engine_desc *desc) +{ + uint8_t word_length; + + word_length = desc->data_width / 8; + + return word_length; +} + +/** + * @brief Compute the prescaler used to set the sleep period. + * + * @param desc Decriptor containing SPI interface parameters + * @param sleep_time_ns The amount of time where the transfer hangs + * @param sleep_div Clock prescaler + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_get_sleep_div(struct spi_desc *desc, + uint32_t sleep_time_ns, + uint32_t *sleep_div) +{ + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + /* + * Engine Wiki: + * + * The frequency of the SCLK signal is derived from the + * module clock frequency using the following formula: + * f_sclk = f_clk / ((div + 1) * 2) + */ + + *sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) / + ((eng_desc->clk_div + 1) * 2) - 1; + + return SUCCESS; +} + +/** + * @brief Create a new commands queue used in a spi transfer + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command with witch the buffer will be initiated + * @return int32_t Failure if the memory allocation failed + */ +static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *local_fifo; + + local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo)); + + if(!local_fifo) + return FAILURE; + + local_fifo->cmd = cmd; + local_fifo->next = NULL; + *fifo = local_fifo; + + return SUCCESS; +} + +/** + * @brief Add a command at the end of an existing queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command to be added + */ +static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *to_add = NULL; + struct spi_engine_cmd_queue *local_fifo; + + local_fifo = *fifo; + while (local_fifo->next != NULL) { + // Get the last element + local_fifo = local_fifo->next; + } + + // Create a new element + spi_engine_queue_new_cmd(&to_add, cmd); + // Add as the next element + local_fifo->next = to_add; +} + +/** + * @brief Add a command at the beginning of an existing queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Command to be added + */ +static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t cmd) +{ + struct spi_engine_cmd_queue *to_add = NULL; + + // Create a new element + spi_engine_queue_new_cmd(&to_add, cmd); + // Interchange the addresses + to_add->next = *fifo; + *fifo = to_add; +} + + +/** + * @brief Get the command from the beginning of the queue + * + * @param fifo Command buffer, usually used in fifo mode + * @param cmd Value of the command that was extracted + * @return int32_t Return FAILURE if the queue is empty + */ +static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo, + uint32_t *cmd) +{ + struct spi_engine_cmd_queue *local_fifo; + + if (!*fifo) + return FAILURE; + + local_fifo = *fifo; + *cmd = local_fifo->cmd; + if ((*fifo)->next) { + *fifo = local_fifo->next; + free(local_fifo); + } else { + free(*fifo); + *fifo = NULL; + } + + return SUCCESS; +} + +/** + * @brief Free the memory allocated by a queue + * + * @param fifo The queue that needs it's memory freed + * @return int32_t This function allways return SUCCESS + */ +static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo) +{ + if(*fifo && (*fifo)->next) + spi_engine_queue_free(&(*fifo)->next); + if((*fifo) != NULL) { + free(*fifo); + *fifo = NULL; + } + + return SUCCESS; +} + +/** + * @brief Write the SPI engine's command fifo + * + * @param desc Decriptor containing SPI Engine's parameters + * @param cmd The command that will be written + * @return int32_t Returns FAILURE if the the axi transfer failed + */ +static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc, + uint32_t cmd) +{ + int32_t ret; + + /* Check if offload is enabled */ + if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) { + ret = spi_engine_write(desc, + SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0), + cmd); + + } else { + ret = spi_engine_write(desc, + SPI_ENGINE_REG_CMD_FIFO, + cmd); + } + + return ret; +} + +/** + * @brief Write a transfer command to the SPI engine's command fifo + * + * @param desc Decriptor containing SPI Engine's parameters + * @param read_write Read/Write operation flag + * @param bytes_number Number of bytes to transfer + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_engine_transfer(struct spi_engine_desc *desc, + uint8_t read_write, + uint8_t bytes_number) +{ + uint8_t words_number; + + words_number = spi_get_words_number(desc, bytes_number); + + desc->offload_tx_len += words_number; + + /* + * Engine Wiki: + * + * https://wiki.analog.com/resources/fpga/peripherals/spi_engine + * + * The words number is zero based + */ + + spi_engine_write_cmd_reg(desc, + SPI_ENGINE_CMD_TRANSFER(read_write, + words_number - 1)); + + return SUCCESS; +} + +/** + * @brief Change the state of the chip select port + * + * @param desc Decriptor containing SPI interface parameters + * @param assert Chip select state. + * The supported values are : + * -true (HIGH) + * -false (LOW) + */ +static void spi_engine_set_cs(struct spi_desc *desc, + bool assert) +{ + uint8_t mask; + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + mask = 0xFF; + /* Switch the state only of the selected chip select */ + if (!assert) + mask ^= BIT(desc->chip_select); + + spi_engine_write_cmd_reg(eng_desc, + SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay, + mask)); +} + +/** + * @brief Add a delay between the engine commands + * + * @param desc Decriptor containing SPI interface parameters + * @param sleep_time_ns Number of nanoseconds to sleep between commands + */ +static void spi_gen_sleep_ns(struct spi_desc *desc, + uint32_t sleep_time_ns) +{ + uint32_t sleep_div; + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + spi_get_sleep_div(desc, sleep_time_ns, &sleep_div); + + spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div)); +} + +/** + * @brief Spi engine command interpreter + * + * @param desc Decriptor containing SPI interface parameters + * @param cmd Command to send to the engine + * @return int32_t - SUCCESS if the command is transferred + * - FAILURE if the command format is invalid + */ +static int32_t spi_engine_write_cmd(struct spi_desc *desc, + uint32_t cmd) +{ + uint8_t engine_command; + uint8_t parameter; + uint8_t modifier; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + engine_command = (cmd >> 12) & 0x0F; + modifier = (cmd >> 8) & 0x0F; + parameter = cmd & 0xFF; + + switch(engine_command) { + case SPI_ENGINE_INST_TRANSFER: + spi_engine_transfer(desc_extra, modifier, parameter); + break; + + case SPI_ENGINE_INST_ASSERT: + if(parameter == 0xFF) { + /* Set the CS HIGH */ + spi_engine_set_cs(desc, true); + } else if(parameter == 0x00) { + /* Set the CS LOW */ + spi_engine_set_cs(desc, false); + } + break; + + /* The SYNC and SLEEP commands got the same value but different + modifier */ + case SPI_ENGINE_INST_SYNC_SLEEP: + /* SYNC instruction */ + if(modifier == 0x00) { + spi_engine_write_cmd_reg(desc_extra, cmd); + } else if(modifier == 0x01) { + spi_gen_sleep_ns(desc, parameter); + } + break; + case SPI_ENGINE_INST_CONFIG: + spi_engine_write_cmd_reg(desc_extra, cmd); + + break; + + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Prepare the command queue before sending it to the engine + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Structure used to store the transfer messages + * @return int32_t This function allways returns SUCCESS + */ +static int32_t spi_engine_compile_message(struct spi_desc *desc, + struct spi_engine_msg *msg) +{ + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* Configure the prescaler */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_REG_CLK_DIV, + desc_extra->clk_div)); + + /* Set the data transfer length */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_DATA_TRANSFER_LEN, + desc_extra->data_width)); + /* + * Configure the spi mode : + * - 3 wire + * - CPOL + * - CPHA + */ + spi_engine_queue_append_cmd(&msg->cmds, + SPI_ENGINE_CMD_CONFIG( + SPI_ENGINE_CMD_REG_CONFIG, + desc->mode)); + + /* Add a sync command to signal that the transfer has finished */ + spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id)); + + return SUCCESS; +} + +/** + * @brief Initiate a spi transfer (Blocking) + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Structure used to store the transfer messages + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation failed + */ +static int32_t spi_engine_transfer_message(struct spi_desc *desc, + struct spi_engine_msg *msg) +{ + uint32_t i; + uint32_t data; + uint32_t sync_id; + bool offload_en; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + spi_engine_compile_message(desc, msg); + + offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) | + (desc_extra->offload_config & OFFLOAD_RX_EN); + + /* Write the command fifo buffer */ + while(msg->cmds != NULL) { + spi_engine_queue_get_cmd(&msg->cmds, &data); + spi_engine_write_cmd(desc, data); + } + + /* Write a number of tx_length WORDS on the SDO line */ + if(offload_en) { + for(i = 0; i < desc_extra->offload_tx_len; i++) + spi_engine_write(desc_extra, + SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0), + msg->tx_buf[i]); + + } else { + if(msg->tx_buf != NULL){ + for(i = 0; i < msg->tx_length; i++) + spi_engine_write(desc_extra, + SPI_ENGINE_REG_SDO_DATA_FIFO, + msg->tx_buf[i]); + } + do { + spi_engine_read(desc_extra, + SPI_ENGINE_REG_SYNC_ID, + &sync_id); + } + /* Wait for the end sync signal */ + while(sync_id != _sync_id); + _sync_id++; + + /* Read a number of rx_length WORDS from the SDI line and store + them */ + for(i = 0; i < msg->rx_length; i++) { + spi_engine_read(desc_extra, + SPI_ENGINE_REG_SDI_DATA_FIFO, + &data); + /* Store the rx data if rx buffer valid, flush sdi_fifo if + rx buffer is invalid.*/ + if(msg->rx_buf != NULL){ + msg->rx_buf[i] = data; + } + } + } + + return SUCCESS; +} + +/** + * @brief Initialize the spi engine + * + * @param desc Decriptor containing SPI interface parameters + * @param param Structure containing the spi init parameters + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation failed + */ +int32_t spi_engine_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + uint32_t data_width = 0; + uint32_t spi_engine_version = 0; + struct spi_engine_desc *eng_desc; + struct spi_engine_init_param *spi_engine_init; + + if (!param) { + return FAILURE; + } + + *desc = malloc(sizeof(**desc)); + if(! *desc) { + free(*desc); + return FAILURE; + } + + eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc)); + + if (!eng_desc) + return FAILURE; + + spi_engine_init = param->extra; + + (*desc)->max_speed_hz = param->max_speed_hz; + (*desc)->chip_select = param->chip_select; + (*desc)->mode = param->mode; + (*desc)->extra = eng_desc; + + eng_desc->offload_config = OFFLOAD_DISABLED; + eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr; + eng_desc->type = spi_engine_init->type; + eng_desc->cs_delay = spi_engine_init->cs_delay; + eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz; + eng_desc->clk_div = eng_desc->ref_clk_hz / + (2 * param->max_speed_hz) - 1; + + /* Perform a reset */ + spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01); + usleep(1000); + spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00); + + /* Get current data width */ + spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width); + eng_desc->max_data_width = data_width; + + spi_engine_set_transfer_width(*desc, spi_engine_init->data_width); + + /* Get spi engine version */ + spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version); + + printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n", + (spi_engine_version >> 16), + ((spi_engine_version >> 8) & 0xFF), + (spi_engine_version & 0xFF)); + + return SUCCESS; +} + +/** + * @brief Write and read on the spi interface in 4-wire mode (full-duplex) + * + * @param desc Decriptor containing SPI interface parameters + * @param data Pointer to data buffer + * @param bytes_number Number of bytes to transfer + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation or transfer failed + */ +int32_t spi_engine_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + uint8_t word_len; + uint8_t words_number; + int32_t ret; + struct spi_engine_msg msg; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* If we want to access SPI interface and SPI engine offload module was + * activated, we need to disable it + * This is set in spi_engine_offload_init() */ + desc_extra->offload_config = OFFLOAD_DISABLED; + /* This is set in spi_engine_offload_transfer() */ + spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0); + + words_number = spi_get_words_number(desc_extra, bytes_number); + + msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds)); + if (!msg.cmds) + return FAILURE; + + msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0])); + msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0])); + msg.tx_length = words_number; + msg.rx_length = words_number; + + /* Get the length of transferred word */ + word_len = spi_get_word_length(desc_extra); + + /* Make sure the CS is HIGH before starting a transaction */ + msg.cmds->next = NULL; + msg.cmds->cmd = CS_HIGH; + // Assert select. + spi_engine_queue_add_cmd(&msg.cmds, CS_LOW); + // add read/write command + spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number)); + // Disable select. + spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH); + + /* Pack the bytes into engine WORDS */ + for (int i = 0; i < bytes_number; i++) + msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width- + (i % word_len + 1) * 8); + + ret = spi_engine_transfer_message(desc, &msg); + + for (int i = 0; i < bytes_number; i++) + data[i] = msg.rx_buf[(i) / word_len] >> + (desc_extra->data_width - + ((i) % word_len + 1) * 8); + + spi_engine_queue_free(&msg.cmds); + free(msg.tx_buf); + free(msg.rx_buf); + + return ret; +} + +/** + * @brief Write and read on the spi interface in 3-wire mode (half-duplex) + * + * @param desc Decriptor containing SPI interface parameters + * @param data Pointer to data buffer + * @param bytes_number Number of bytes to transfer + * @return int32_t - SUCCESS if the transfer finished + * - FAILURE if the memory allocation or transfer failed + */ +int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number) +{ + uint8_t word_len; + uint8_t wr_words_number; + uint8_t rd_words_number; + int32_t ret; + struct spi_engine_msg msg; + struct spi_engine_desc *desc_extra; + + desc_extra = desc->extra; + + /* If we want to access SPI interface and SPI engine offload module was + * activated, we need to disable it + * This is set in spi_engine_offload_init() */ + desc_extra->offload_config = OFFLOAD_DISABLED; + /* This is set in spi_engine_offload_transfer() */ + spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0); + + wr_words_number = spi_get_words_number(desc_extra, write_bytes_number); + rd_words_number = spi_get_words_number(desc_extra, read_bytes_number); + + msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds)); + if (!msg.cmds) + return FAILURE; + + msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL; + msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL; + msg.tx_length = wr_words_number; + msg.rx_length = rd_words_number; + + /* Get the length of transferred word */ + word_len = spi_get_word_length(desc_extra); + + /* Make sure the CS is HIGH before starting a transaction */ + msg.cmds->next = NULL; + msg.cmds->cmd = CS_HIGH; + + // Assert select. + spi_engine_queue_add_cmd(&msg.cmds, CS_LOW); + + // add read/write command + if(write_bytes_number > 0) + spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number)); + if(read_bytes_number > 0) + spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number)); + + // Disable select. + spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH); + + /* Pack the bytes into engine WORDS */ + for (int i = 0; i < write_bytes_number; i++) + msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width- + (i % word_len + 1) * 8); + + ret = spi_engine_transfer_message(desc, &msg); + + for (int i = 0; i < read_bytes_number; i++) + read_data[i] = msg.rx_buf[(i) / word_len] >> + (desc_extra->data_width - + ((i) % word_len + 1) * 8); + + spi_engine_queue_free(&msg.cmds); + free(msg.tx_buf); + free(msg.rx_buf); + + return ret; +} + +/** + * @brief Initialize the SPI engine's offload module + * + * @param desc Decriptor containing SPI interface parameters + * @param param Structure containing the offload init parameters + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_offload_init(struct spi_desc *desc, + const struct spi_engine_offload_init_param *param) +{ + struct spi_engine_desc *eng_desc; + struct axi_dmac_init dmac_init; + uint32_t dma_flags; + + eng_desc = desc->extra; + + eng_desc->offload_config = param->offload_config; + + if(!(param->dma_flags)) + dma_flags = DMA_CYCLIC; + else + dma_flags = *(param->dma_flags); + + if(param->offload_config & OFFLOAD_TX_EN) { + dmac_init.name = "DAC DMAC"; + dmac_init.base = param->tx_dma_baseaddr; + dmac_init.direction = DMA_MEM_TO_DEV; + dmac_init.flags = dma_flags; + axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init); + if(!eng_desc->offload_tx_dma) + return FAILURE; + } + if(param->offload_config & OFFLOAD_RX_EN) { + dmac_init.name = "ADC DMAC"; + dmac_init.base = param->rx_dma_baseaddr; + dmac_init.direction = DMA_DEV_TO_MEM; + dmac_init.flags = dma_flags; + axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init); + if(!eng_desc->offload_rx_dma) + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Initiate a SPI transfer in offload mode + * + * @param desc Decriptor containing SPI interface parameters + * @param msg Offload message that get's to be transferred + * @param no_samples Number of time the messages will be transferred + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_offload_transfer(struct spi_desc *desc, + struct spi_engine_offload_message msg, + uint32_t no_samples) +{ + struct spi_engine_msg transfer; + struct spi_engine_desc *eng_desc; + uint32_t i; + uint8_t word_length; + + eng_desc = desc->extra; + + /* Check if offload is disabled */ + if(!((eng_desc->offload_config & OFFLOAD_TX_EN) | + (eng_desc->offload_config & OFFLOAD_RX_EN))) + return FAILURE; + + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1); + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0); + + eng_desc->offload_tx_len = 0; + eng_desc->offload_rx_len = 0; + + transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds)); + + if (!transfer.cmds) + return FAILURE; + + transfer.tx_buf = msg.commands_data; + + /* Load the commands into the message */ + transfer.cmds->next = NULL; + transfer.cmds->cmd = msg.commands[0]; + i = 1; + while(i < msg.no_commands) { + spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]); + + } + + spi_engine_transfer_message(desc, &transfer); + + /* Start transfer */ + spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001); + + word_length = spi_get_word_length(eng_desc); + if(eng_desc->offload_config & OFFLOAD_TX_EN) { + axi_dmac_transfer(eng_desc->offload_tx_dma, + msg.tx_addr, + word_length * eng_desc->offload_tx_len * + no_samples); + } + + if(eng_desc->offload_config & OFFLOAD_RX_EN) { + axi_dmac_transfer(eng_desc->offload_rx_dma, + msg.rx_addr, + word_length * eng_desc->offload_tx_len * + no_samples); + } + + usleep(1000); + + spi_engine_queue_free(&transfer.cmds); + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by spi_init(). + * + * @param desc Decriptor containing SPI interface parameters + * @return int32_t This function allways returns SUCCESS + */ +int32_t spi_engine_remove(struct spi_desc *desc) +{ + struct spi_engine_desc *eng_desc; + + eng_desc = desc->extra; + + if(eng_desc->offload_config & OFFLOAD_TX_EN) + axi_dmac_remove(eng_desc->offload_tx_dma); + if(eng_desc->offload_config & OFFLOAD_RX_EN) + axi_dmac_remove(eng_desc->offload_rx_dma); + free(desc->extra); + free(desc); + + return SUCCESS; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h new file mode 100644 index 00000000..90dd18e9 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h @@ -0,0 +1,231 @@ +/******************************************************************************* + * @file spi_engine.h + * @brief Header file of SPI Engine core features. + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_ENGINE_H +#define SPI_ENGINE_H + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include "spi_engine_private.h" +#include "../../platform/spi_extra.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define OFFLOAD_DISABLED 0x00 +#define OFFLOAD_TX_EN BIT(0) +#define OFFLOAD_RX_EN BIT(1) +#define OFFLOAD_TX_RX_EN OFFLOAD_TX_EN | OFFLOAD_RX_EN + +#define SPI_ENGINE_MSG_QUEUE_END 0xFFFFFFFF + +/* Spi engine commands */ +#define WRITE_OR_READ(mode, no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ +((mode) << 8) | (no_bytes)) + +#define WRITE(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes)) + +#define READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes)) + +#define WRITE_READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\ + (SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes)) + + + +#define SLEEP(time) SPI_ENGINE_CMD_SLEEP(time & 0xF) + +/* The delay and chip select parmeters are passed over the engine descriptor +and will be used inside the function call */ +#define CS_HIGH SPI_ENGINE_CMD_ASSERT(0x00, 0xFF) +#define CS_LOW SPI_ENGINE_CMD_ASSERT(0x00, 0x00) + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @struct spi_engine_init_param + * @brief Structure containing the init parameters needed by the SPI engine + */ +struct spi_engine_init_param { + /** SPI engine reference clock */ + uint32_t ref_clk_hz; + /** Type of implementation */ + enum xil_spi_type type; + /** Base address where the HDL core is situated */ + uint32_t spi_engine_baseaddr; + /** Delay between the CS toggle and the start of SCLK */ + uint32_t cs_delay; + /** Data with of one SPI transfer ( in bits ) */ + uint8_t data_width; +}; + + +/** + * @struct spi_engine_desc + * @brief Structure representing an SPI engine device + */ +struct spi_engine_desc { + /** SPI engine reference clock */ + uint32_t ref_clk_hz; + /** Type of implementation */ + enum xil_spi_type type; + /** Pointer to a DMAC used in transmission */ + struct axi_dmac *offload_tx_dma; + /** Pointer to a DMAC used in reception */ + struct axi_dmac *offload_rx_dma; + /** Offload's module transfer direction : TX, RX or both */ + uint8_t offload_config; + /** Number of words that the module has to send */ + uint8_t offload_tx_len; + /** Number of words that the module has to receive */ + uint8_t offload_rx_len; + /** Base address where the HDL core is situated */ + uint32_t spi_engine_baseaddr; + /** Base address where the RX DMAC core is situated */ + uint32_t rx_dma_baseaddr; + /** Base address where the TX DMAC core is situated */ + uint32_t tx_dma_baseaddr; + /** Delay between the CS toggle and the start of SCLK */ + uint8_t cs_delay; + /** Clock divider used in transmission delays */ + uint32_t clk_div; + /** Data with of one SPI transfer ( in bits ) */ + uint8_t data_width; + /** The maximum data width supported by the engine */ + uint8_t max_data_width; +}; + + +/** + * @struct spi_engine_offload_init_param + * @brief Structure containing the init parameters needed by the offload module + */ +struct spi_engine_offload_init_param { + /** Base address where the RX DMAC core is situated */ + uint32_t rx_dma_baseaddr; + /** Base address where the TX DMAC core is situated */ + uint32_t tx_dma_baseaddr; + /** DMAC flags - if not initialized, the default value is DMA_CYCLIC */ + uint32_t *dma_flags; + /** Offload's module transfer direction : TX, RX or both */ + uint8_t offload_config; +}; + +/** + * @struct spi_engine_offload_message + * @brief Structure representing an offload message + */ +struct spi_engine_offload_message { + /** Pointer to the SPI engine commands buffer that will be sent. + * The available commands can be found at: + * https://wiki.analog.com/resources/fpga/peripherals/spi_engine/ + */ + uint32_t *commands; + /** Length of the SPI engine commands buffer */ + uint32_t no_commands; + /** Pointer of the data that will be sent over spi */ + uint32_t *commands_data; + /** The address where the data that will be transmitted is situated */ + uint32_t tx_addr; + /** The address where the data that will be received is situated */ + uint32_t rx_addr; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/** + * @brief Spi engine platform specific SPI platform ops structure + */ +extern const struct spi_platform_ops xil_spi_ops; + +/* Write SPI Engine's axi registers */ +int32_t spi_engine_write(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t reg_data); + +/* Read SPI Engine's axi registers */ +int32_t spi_engine_read(struct spi_engine_desc *desc, + uint32_t reg_addr, + uint32_t *reg_data); +/* Initialize the SPI engine device */ +int32_t spi_engine_init(struct spi_desc **desc, + const struct spi_init_param *param); + +/* Write and read data over SPI using the SPI engine */ +int32_t spi_engine_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number); + +/* Write and read data over SPI using the SPI engine in 3-wire mode */ +int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number); +/* Free the resources used by the SPI engine device */ +int32_t spi_engine_remove(struct spi_desc *desc); + +/* Initialize the SPI engine offload module */ +int32_t spi_engine_offload_init(struct spi_desc *desc, + const struct spi_engine_offload_init_param *param); + +/* Write and read data over SPI using the offload module */ +int32_t spi_engine_offload_transfer(struct spi_desc *desc, + struct spi_engine_offload_message msg, + uint32_t no_samples); + +/* Set SPI transfer width */ +int32_t spi_engine_set_transfer_width(struct spi_desc *desc, + uint8_t data_wdith); + +/* Set SPI transfer speed */ +void spi_engine_set_speed(struct spi_desc *desc, + uint32_t speed_hz); + +#endif // SPI_ENGINE_H diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h new file mode 100644 index 00000000..2c71ebfa --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h @@ -0,0 +1,154 @@ +/******************************************************************************* + * @file spi_engine_private.h + * @brief Private definitions of the SPI Engine + * @author Sergiu Cuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_ENGINE_PRIVATE_H +#define SPI_ENGINE_PRIVATE_H + +#include +#include + +#include "../../../include/spi.h" +#include "../../../include/util.h" + +/******************************************************************************/ +/*************************** Spi Engine registers *****************************/ +/******************************************************************************/ + +#define SPI_ENGINE_REG_VERSION 0x00 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_RESET 0x40 +#define SPI_ENGINE_REG_INT_ENABLE 0x80 +#define SPI_ENGINE_REG_INT_PENDING 0x84 +#define SPI_ENGINE_REG_INT_SOURCE 0x88 +#define SPI_ENGINE_REG_SYNC_ID 0xC0 +#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xD0 +#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xD4 +#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xD8 +#define SPI_ENGINE_REG_CMD_FIFO 0xE0 +#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xE4 +#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xE8 +#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xEC + +/******************************************************************************/ +/************************ Spi Engine register parameters **********************/ +/******************************************************************************/ + +#define SPI_ENGINE_INST_TRANSFER 0x00 +#define SPI_ENGINE_INST_ASSERT 0x01 +#define SPI_ENGINE_INST_CONFIG 0x02 +#define SPI_ENGINE_INST_SYNC_SLEEP 0x03 +#define SPI_ENGINE_INST_MISC 0x03 +#define SPI_ENGINE_CMD_REG_CLK_DIV 0x00 +#define SPI_ENGINE_CMD_REG_CONFIG 0x01 +#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN 0x02 +#define SPI_ENGINE_MISC_SYNC 0x00 +#define SPI_ENGINE_MISC_SLEEP 0x01 +#define SPI_ENGINE_SYNC_TRANSFER_BEGIN BIT(1) +#define SPI_ENGINE_SYNC_TRANSFER_END BIT(2) +#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0) +#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1) +#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2) +#define SPI_ENGINE_INT_SYNC BIT(3) +#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0) +#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED BIT(0) +#define SPI_ENGINE_CONFIG_CPHA BIT(0) +#define SPI_ENGINE_CONFIG_CPOL BIT(1) +#define SPI_ENGINE_CONFIG_3WIRE BIT(2) +#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff) +#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff) +#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff) + +/******************************************************************************/ +/**************************** Spi Engine commands *****************************/ +/******************************************************************************/ + +#define SPI_ENGINE_INSTRUCTION_TRANSFER_W 0x01 +#define SPI_ENGINE_INSTRUCTION_TRANSFER_R 0x02 +#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW 0x03 + +#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x) (0x110 + (0x20 * x)) +#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x) (0x114 + (0x20 * x)) + +#define SPI_ENGINE_CMD(inst, arg1, arg2) \ + (((inst & 0x03) << 12) | \ + ((arg1 & 0x03) << 8) | arg2 ) + +#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, \ + (readwrite), (n)) + +#define SPI_ENGINE_CMD_ASSERT(delay, cs) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, \ + (delay), (cs)) + +#define SPI_ENGINE_CMD_CONFIG(reg, val) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG, \ + (reg), (val)) + +#define SPI_ENGINE_CMD_SLEEP(delay) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \ + SPI_ENGINE_MISC_SLEEP, \ + (delay)) + +#define SPI_ENGINE_CMD_SYNC(id) \ + SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \ + SPI_ENGINE_MISC_SYNC, \ + (id)) + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +typedef struct spi_engine_cmd_queue { + uint32_t cmd; + struct spi_engine_cmd_queue *next; +} spi_engine_cmd_queue; + +typedef struct spi_engine_msg { + uint32_t *tx_buf; + uint32_t *rx_buf; + uint32_t tx_length; + uint32_t rx_length; + struct spi_engine_cmd_queue *cmds; +} spi_engine_msg; + +#endif // SPI_ENGINE_PRIVATE_H diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/frequency/ad9516/ad9516.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/frequency/ad9516/ad9516.c new file mode 100644 index 00000000..c47524d5 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/frequency/ad9516/ad9516.c @@ -0,0 +1,129 @@ +/***************************************************************************//** + * @file ad9516.c + * @brief Implementation of AD9680 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include "ad9516.h" + +#include +#include +#include "../../../include/error.h" + +/***************************************************************************//** + * @brief ad9516_read + *******************************************************************************/ +int32_t ad9516_read(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data) +{ + uint8_t tx_buf[2]; + uint8_t rx_buf[1]; + int32_t ret; + + tx_buf[0] = 0x80 | (reg_addr >> 8); + tx_buf[1] = reg_addr & 0xFF; + + + ret = spi_write_and_read_3wire(dev->spi_desc, + tx_buf, rx_buf, 2, 1); + + *reg_data = rx_buf[0]; + + return ret; +} + +/***************************************************************************//** + * @brief ad9516_write + *******************************************************************************/ +int32_t ad9516_write(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t reg_data) +{ + uint8_t buf[3]; + + int32_t ret; + + buf[0] = reg_addr >> 8; + buf[1] = reg_addr & 0xFF; + buf[2] = reg_data; + + ret = spi_write_and_read_3wire(dev->spi_desc, + buf, NULL, 3, 0); + return ret; +} + +/***************************************************************************//** + * @brief ad9516_init + *******************************************************************************/ +int32_t ad9516_init(struct ad9516_dev **device, + const struct ad9516_init_param *init_param) +{ + int ret = SUCCESS; + struct ad9516_dev *dev; + + dev = (struct ad9516_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + /* SPI */ + ret = spi_init(&dev->spi_desc, init_param->spi_init); + + *device = dev; + + return ret; +} + +/***************************************************************************//** + * @brief Free the resources allocated by ad9516_setup(). + * + * @param dev - The device structure. + * + * @return SUCCESS in case of success, negative error code otherwise. +*******************************************************************************/ +int32_t ad9516_remove(struct ad9516_dev *dev) +{ + int32_t ret; + + ret = spi_remove(dev->spi_desc); + + free(dev); + + return ret; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/frequency/ad9516/ad9516.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/frequency/ad9516/ad9516.h new file mode 100644 index 00000000..04fc637c --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/frequency/ad9516/ad9516.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file ad9516.h + * @brief Header file of ad9516 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ +#ifndef AD9516_H_ +#define AD9516_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/delay.h" +#include "../../../include/spi.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +struct ad9516_dev { + /* SPI */ + spi_desc *spi_desc; +}; + +struct ad9516_init_param { + /* SPI */ + spi_init_param *spi_init; +}; + +struct ad9516_config { + uint16_t addr; + uint8_t value; +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +int32_t ad9516_read(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data); + +int32_t ad9516_write(struct ad9516_dev *dev, + uint16_t reg_addr, + uint8_t reg_data); + +int32_t ad9516_init(struct ad9516_dev **device, + const struct ad9516_init_param *init_param); + +int32_t ad9516_remove(struct ad9516_dev *dev); + +#endif diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/axi_io.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/axi_io.c new file mode 100644 index 00000000..d7b5a82f --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/axi_io.c @@ -0,0 +1,79 @@ +/***************************************************************************//** + * @file xilinx/axi_io.c + * @brief Implementation of Xilinx AXI IO. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/error.h" +#include "../../include/axi_io.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief AXI IO Xilinx specific read function. + * @param base - Base address + * @param offset - Address offset + * @param data - variable where returned data is stored + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data) +{ + *data = Xil_In32(base + offset); + + return SUCCESS; +} + +/** + * @brief AXI IO Xilinx specific write function. + * @param base - Base address + * @param offset - Address offset + * @param data - data to be written. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data) +{ + Xil_Out32(base + offset, data); + + return SUCCESS; +} + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/delay.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/delay.c new file mode 100644 index 00000000..ca06169b --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/delay.c @@ -0,0 +1,77 @@ +/***************************************************************************//** + * @file xilinx/delay.c + * @brief Implementation of Xilinx Delay Functions. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include "../../include/delay.h" +#include + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Generate microseconds delay. + * @param usecs - Delay in microseconds. + * @return None. + */ +void udelay(uint32_t usecs) +{ +#ifdef _XPARAMETERS_PS_H_ + usleep(usecs); +#else + usleep(usecs / 20); // FIXME +#endif +} + +/** + * @brief Generate miliseconds delay. + * @param msecs - Delay in miliseconds. + * @return None. + */ +void mdelay(uint32_t msecs) +{ +#ifdef _XPARAMETERS_PS_H_ + usleep(msecs * 1000); +#else + usleep(msecs * 50); // FIXME +#endif +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/gpio_extra.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/gpio_extra.h new file mode 100644 index 00000000..dbc64b93 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/gpio_extra.h @@ -0,0 +1,95 @@ +/******************************************************************************* + * @file xilinx/gpio_extra.h + * @brief Header containing extra types used in the gpio driver + * @author scuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef GPIO_EXTRA_H_ +#define GPIO_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_gpio_type + * @brief Xilinx platform architecture sections + */ +typedef enum xil_gpio_type { + /** Programmable Logic */ + GPIO_PL, + /** Processing System */ + GPIO_PS +} xil_gpio_type; + +/** + * @struct xil_gpio_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific GPIO parameters. + */ +typedef struct xil_gpio_init_param { + /** Xilinx architecture */ + enum xil_gpio_type type; + /** Device ID */ + uint32_t device_id; +} xil_gpio_init_param; + +/** + * @struct xil_gpio_desc + * @brief Xilinx platform specific GPIO descriptor + */ +typedef struct xil_gpio_desc { + /** Xilinx architecture */ + enum xil_gpio_type type; + /** Xilinx GPIO configuration */ + void *config; + /** Xilinx GPIO Instance */ + void *instance; +} xil_gpio_desc; + +/** + * @brief Xilinx platform specific gpio platform ops structure + */ +extern const struct gpio_platform_ops xil_gpio_ops; + +#endif diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/irq_extra.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/irq_extra.h new file mode 100644 index 00000000..1c9b959f --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/irq_extra.h @@ -0,0 +1,91 @@ +/******************************************************************************* + * @file irq_extra.h + * @brief Header containing types used in the irq driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef IRQ_EXTRA_H_ +#define IRQ_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/irq.h" + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_irq_type + * @brief Xilinx platform architecture sections + */ +enum xil_irq_type { + /** Programmable Logic */ + IRQ_PL, + /** Processing System */ + IRQ_PS +}; + +/** + * @struct xil_irq_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific IRQ parameters. + */ +struct xil_irq_init_param { + /** Xilinx architecture */ + enum xil_irq_type type; +}; + +/** + * @struct xil_irq_desc + * @brief Xilinx platform specific IRQ descriptor + */ +struct xil_irq_desc { + /** Xilinx architecture */ + enum xil_irq_type type; + /** Xilinx IRQ Instance */ + void *instance; +}; + +/** + * @brief Xilinx specific IRQ platform ops structure + */ +extern const struct irq_platform_ops xil_irq_ops; + +#endif diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/spi_extra.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/spi_extra.h new file mode 100644 index 00000000..2edb42c1 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/spi_extra.h @@ -0,0 +1,115 @@ +/******************************************************************************* + * @file xilinx/spi_extra.h + * @brief Header containing extra types used in the spi driver. + * @author scuciurean (sergiu.cuciurean@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef SPI_EXTRA_H_ +#define SPI_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include "../../include/spi.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define SPI_CS_DECODE 0x01 +#define SPI_DEASSERT_CURRENT_SS 0x0F + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_spi_type + * @brief Xilinx platform architecture sections + */ +enum xil_spi_type { + /** Programmable Logic */ + SPI_PL, + /** Processing System */ + SPI_PS, + /** SPI Engine */ + SPI_ENGINE +}; + +/** + * @struct xil_spi_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific SPI parameters when using xil_spi_ops. + */ +typedef struct xil_spi_init_param { + /** Xilinx architecture */ + enum xil_spi_type type; + /** SPI flags */ + uint32_t flags; +} xil_spi_init_param; + +/** + * @struct xil_spi_desc + * @brief Xilinx platform specific SPI descriptor + */ +typedef struct xil_spi_desc { + /** Xilinx architecture */ + enum xil_spi_type type; + /** SPI flags */ + uint32_t flags; + /** SPI configuration */ + void *config; + /** SPI instance */ + void *instance; +} xil_spi_desc; + +/** + * @brief SPI engine platform ops structure + */ +extern const struct spi_platform_ops spi_eng_platform_ops; + +/** + * @brief Xilinx specific SPI platform ops structure + */ +extern const struct spi_platform_ops xil_spi_ops; + +/** + * @brief Xilinx SPI PS register functions. No extra param needed + */ +extern const struct spi_platform_ops xil_spi_reg_ops_pl; + +#endif // SPI_EXTRA_H_ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/uart_extra.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/uart_extra.h new file mode 100644 index 00000000..c877ebf2 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/uart_extra.h @@ -0,0 +1,107 @@ +/******************************************************************************* + * @file xilinx/uart_extra.h + * @brief Header containing types used in the uart driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef UART_EXTRA_H_ +#define UART_EXTRA_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define UART_BUFF_LENGTH 256 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum xil_uart_type + * @brief Xilinx platform architecture sections + */ +enum xil_uart_type { + /** Programmable Logic */ + UART_PL, + /** Processing System */ + UART_PS +}; + +/** + * @struct xil_uart_init_param + * @brief Structure holding the initialization parameters for Xilinx platform + * specific UART parameters. + */ +struct xil_uart_init_param { + /** Xilinx architecture */ + enum xil_uart_type type; + /** Interrupt Request ID */ + uint32_t irq_id; + /** Interrupt Request Descriptor */ + struct irq_ctrl_desc *irq_desc; +}; + +/** + * @struct xil_uart_desc + * @brief Xilinx platform specific UART descriptor + */ +struct xil_uart_desc { + /** Xilinx architecture */ + enum xil_uart_type type; + /** Interrupt Request ID */ + uint32_t irq_id; + /** Interrupt Request Descriptor */ + struct irq_ctrl_desc *irq_desc; + /** FIFO */ + struct fifo_element *fifo; + /** FIFO read offset */ + uint32_t fifo_read_offset; + /** UART Buffer */ + char buff[UART_BUFF_LENGTH]; + /** Number of bytes received */ + uint32_t bytes_received; + /** Total number of errors */ + uint32_t total_error_count; + /** UART Instance */ + void *instance; +}; + +#endif diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_gpio.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_gpio.c new file mode 100644 index 00000000..08ed15f3 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_gpio.c @@ -0,0 +1,464 @@ +/***************************************************************************//** + * @file xilinx/xilinx_gpio.c + * @brief Implementation of Xilinx GPIO Generic Driver. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include +#ifdef XPAR_XGPIO_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XGPIOPS_NUM_INSTANCES +#include +#endif + +#include "gpio_extra.h" +#include "../../include/error.h" +#include "../../include/gpio.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Prepare the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - The structure that contains the GPIO parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t _gpio_init(struct gpio_desc *desc, + const struct gpio_init_param *param) +{ + int32_t ret; + struct xil_gpio_desc *xdesc; + struct xil_gpio_init_param *xinit; + + ret = FAILURE; + + xdesc = desc->extra; + xinit = param->extra; + + xdesc->type = xinit->type; + desc->number = param->number; + + switch (xinit->type) { + case GPIO_PL: +#ifdef XGPIO_H + xdesc->instance = (XGpio *)malloc(sizeof(XGpio)); + if(!xdesc->instance) + goto pl_error; + + xdesc->config = XGpio_LookupConfig(xinit->device_id); + if(xdesc->config == NULL) + goto pl_error; + + ret = XGpio_CfgInitialize(xdesc->instance, + xdesc->config, + ((XGpio_Config*)xdesc->config) + ->BaseAddress); + if(ret < 0) + goto pl_error; + + break; +pl_error: + free(xdesc->instance); +#endif + goto error; + case GPIO_PS: +#ifdef XGPIOPS_H + xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs)); + if(!xdesc->instance) + goto ps_error; + + xdesc->config = XGpioPs_LookupConfig(xinit->device_id); + if(xdesc->config == NULL) + goto ps_error; + + ret = XGpioPs_CfgInitialize(xdesc->instance, + xdesc->config, + ((XGpioPs_Config*)xdesc->config)->BaseAddr); + if(ret < 0) + goto ps_error; + break; +ps_error: + free(xdesc->instance); +#endif + goto error; +error: + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Obtain the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param param - GPIO initialization parameters + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + struct gpio_desc *descriptor; + struct xil_gpio_desc *extra; + int32_t ret; + + descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor)); + extra = (struct xil_gpio_desc*)malloc(sizeof(*extra)); + + if (!descriptor || !extra) + return FAILURE; + + descriptor->extra = extra; + ret = _gpio_init(descriptor, param); + + if(ret != SUCCESS) + goto error; + + *desc = descriptor; + + return SUCCESS; +error: + free(extra); + free(descriptor); + + return FAILURE; +} + +/** + * @brief Get the value of an optional GPIO. + * @param desc - The GPIO descriptor. + * @param param - GPIO Initialization parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param) +{ + if(param == NULL) { + *desc = NULL; + return SUCCESS; + } + + return xil_gpio_get(desc, param); +} + +/** + * @brief Free the resources allocated by gpio_get(). + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_remove(struct gpio_desc *desc) +{ + if (desc != NULL) { + free(((xil_gpio_desc *)(desc->extra))->instance); + free(desc->extra); + free(desc); + } + + return SUCCESS; +} + +/** + * @brief Enable the input direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_direction_input(struct gpio_desc *desc) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint32_t channel = 1; + uint32_t config = 0; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + /* We assume that pin 32 is the first pin from channel 2 */ + if (pin >= 32) { + channel = 2; + pin -= 32; + } + + config = XGpio_GetDataDirection((XGpio *)extra->instance, + channel); + config |= (1 << pin); + XGpio_SetDataDirection((XGpio *)extra->instance, + channel, + config); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_SetDirectionPin(extra->instance, + desc->number, + GPIO_IN); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Enable the output direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_direction_output(struct gpio_desc *desc, + uint8_t value) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_GetDataDirection(extra->instance, + channel); + reg_val &= ~(1 << pin); + XGpio_SetDataDirection(extra->instance, + channel, + reg_val); + reg_val = XGpio_DiscreteRead(extra->instance, + channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(extra->instance, + channel, + reg_val); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_SetDirectionPin(extra->instance, + desc->number, + GPIO_OUT); + XGpioPs_SetOutputEnablePin(extra->instance, + desc->number, + GPIO_OUT); + XGpioPs_WritePin(extra->instance, + desc->number, + value); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Get the direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param direction - The direction. + * Example: GPIO_OUT + * GPIO_IN + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction) +{ + if (!desc) + return FAILURE; + + struct xil_gpio_desc *extra; + uint8_t pin = desc->number; + +#ifdef XGPIO_H + uint8_t channel; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + *direction = ((XGpio_GetDataDirection(extra->instance, + channel) >> pin) & 0x1) ^ 0x1; +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + *direction = XGpioPs_GetDirectionPin(extra->instance, pin); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Set the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_set_value(struct gpio_desc *desc, + uint8_t value) +{ + struct xil_gpio_desc *extra; +#ifdef XGPIO_H + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_DiscreteRead(extra->instance, channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(extra->instance, channel, reg_val); +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + XGpioPs_WritePin(extra->instance, desc->number, value); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Get the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_gpio_get_value(struct gpio_desc *desc, + uint8_t *value) +{ + if (!desc) + return FAILURE; + + struct xil_gpio_desc *extra; + uint8_t pin = desc->number; + +#ifdef XGPIO_H + uint8_t channel; +#endif + extra = desc->extra; + + switch (extra->type) { + case GPIO_PL: +#ifdef XGPIO_H + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + *value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01; +#endif + break; + case GPIO_PS: +#ifdef XGPIOPS_H + *value = XGpioPs_ReadPin(extra->instance, pin); +#endif + break; + default: + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Xilinx platform specific GPIO platform ops structure + */ +const struct gpio_platform_ops xil_gpio_ops = { + .gpio_ops_get = &xil_gpio_get, + .gpio_ops_get_optional = &xil_gpio_get_optional, + .gpio_ops_remove = &xil_gpio_remove, + .gpio_ops_direction_input = &xil_gpio_direction_input, + .gpio_ops_direction_output = &xil_gpio_direction_output, + .gpio_ops_get_direction = &xil_gpio_get_direction, + .gpio_ops_set_value = &xil_gpio_set_value, + .gpio_ops_get_value = &xil_gpio_get_value, +}; diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_irq.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_irq.c new file mode 100644 index 00000000..e688a3ae --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_irq.c @@ -0,0 +1,384 @@ +/***************************************************************************//** + * @file xilinx/xilinx_irq.c + * @brief Implementation of Xilinx IRQ Generic Driver. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include +#include "irq_extra.h" +#include "../../include/irq.h" +#include "../../include/error.h" +#ifdef XPAR_XSCUGIC_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XINTC_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XTMRCTR_NUM_INSTANCES +#include +#endif + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Initialize the IRQ interrupts. + * @param desc - The IRQ controller descriptor. + * @param param - The structure that contains the IRQ parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param) +{ + int32_t status; + struct irq_ctrl_desc *descriptor; + struct xil_irq_desc *xil_dev; +#ifdef XSCUGIC_H + void *config; +#endif + + descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor); + if(!descriptor) + return FAILURE; + xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev); + if(!xil_dev) { + free(descriptor); + return FAILURE; + } + + Xil_ExceptionInit(); + + descriptor->irq_ctrl_id = param->irq_ctrl_id; + descriptor->extra = xil_dev; + xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + xil_dev->instance = calloc(1, sizeof(XScuGic)); + if(!xil_dev->instance) + goto error; + + config = XScuGic_LookupConfig(descriptor->irq_ctrl_id); + if(!config) + goto ps_error; + + status = XScuGic_CfgInitialize(xil_dev->instance, config, + ((XScuGic_Config *)config)->CpuBaseAddress); + if (status != SUCCESS) + goto ps_error; + + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, + xil_dev->instance); + + break; +ps_error: + free(xil_dev->instance); +#endif + goto error; + case IRQ_PL: +#ifdef XINTC_H + xil_dev->instance = calloc(1, sizeof(XIntc)); + if(!xil_dev->instance) + goto error; + + status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id); + if(status != SUCCESS) + goto pl_error; + + status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE); + if(status != SUCCESS) + goto pl_error; + + break; +pl_error: + free(xil_dev->instance); +#endif + goto error; + default: + goto error; + + break; + } + + *desc = descriptor; + + return SUCCESS; + +error: + free(xil_dev); + free(descriptor); + + return FAILURE; +} + +/** + * @brief Enable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc) +{ + /* Enable interrupts */ + Xil_ExceptionEnable(); + + return SUCCESS; +} + +/** + * @brief Disable global interrupts. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc) +{ + /* Disable interrupts */ + Xil_ExceptionDisable(); + + return SUCCESS; +} + +/** + * @brief Enable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Enable(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Enable(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Disable specific interrupt. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Disable(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Disable(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Register a callback to handle the irq events. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param callback_desc - Callback descriptor + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + return XScuGic_Connect(xil_dev->instance, irq_id, + (Xil_InterruptHandler) callback_desc->callback, + callback_desc->ctx); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) { + int32_t ret; + + ret = XIntc_Connect(xil_dev->instance, irq_id, + XTmrCtr_InterruptHandler, callback_desc->config); + if (IS_ERR_VALUE(ret)) + return FAILURE; + XTmrCtr_SetHandler(callback_desc->config, + (XTmrCtr_Handler)callback_desc->callback, + callback_desc->ctx); + + return SUCCESS; + } + return XIntc_Connect(xil_dev->instance, irq_id, + (XInterruptHandler) callback_desc->callback, + callback_desc->ctx); +#endif + break; + default: + break; + } + + return FAILURE; +} + +/** + * @brief Set interrupt trigger level. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @param trig - New trigger level for the interrupt. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + if(trig == IRQ_EDGE_BOTH) + return -EINVAL; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + ; + uint8_t priority, trigger; + + XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority, + &trigger); + trigger = trig; + XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority, + trigger); + + return SUCCESS; +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + /* Interrupt trigger determined in hardware. TODO: verify */ + return SUCCESS; +#endif + break; + default: + break; + } + + return FAILURE; +} + +/** + * @brief Unregisters a generic IRQ handling function. + * @param desc - The IRQ controller descriptor. + * @param irq_id - Interrupt identifier. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id) +{ + struct xil_irq_desc *xil_dev = desc->extra; + + switch(xil_dev->type) { + case IRQ_PS: +#ifdef XSCUGIC_H + XScuGic_Disconnect(xil_dev->instance, irq_id); +#endif + break; + case IRQ_PL: +#ifdef XINTC_H + XIntc_Disconnect(xil_dev->instance, irq_id); +#endif + break; + default: + + return FAILURE; + } + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by irq_ctrl_init(). + * @param desc - The IRQ control descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc) +{ + struct xil_irq_desc *xil_dev = desc->extra; + free(xil_dev->instance); + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/** + * @brief Xilinx platform specific IRQ platform ops structure + */ +const struct irq_platform_ops xil_irq_ops = { + .init = &xil_irq_ctrl_init, + .register_callback = &xil_irq_register_callback, + .unregister = &xil_irq_unregister, + .global_enable = &xil_irq_global_enable, + .global_disable = &xil_irq_global_disable, + .trigger_level_set = &xil_irq_trigger_level_set, + .enable = &xil_irq_enable, + .disable = &xil_irq_disable, + .remove = &xil_irq_ctrl_remove +}; diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_spi.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_spi.c new file mode 100644 index 00000000..adc38325 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_spi.c @@ -0,0 +1,461 @@ +/***************************************************************************//** + * @file xilinx/xilinx_spi.c + * @brief Implementation of Xilinx SPI Generic Driver. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +#include +#ifdef XPAR_XSPI_NUM_INSTANCES +#include +#endif +#ifdef XPAR_XSPIPS_NUM_INSTANCES +#include +#endif + +#include "../../include/error.h" +#include "../../include/spi.h" +#include "spi_extra.h" + +#if defined(PLATFORM_ZYNQ) +#define SPI_CLK_FREQ_HZ(dev) (XPAR_PS7_SPI_ ## dev ## _SPI_CLK_FREQ_HZ) +#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES +#elif defined(PLATFORM_ZYNQMP) +#define SPI_CLK_FREQ_HZ(dev) (XPAR_PSU_SPI_ ## dev ## _SPI_CLK_FREQ_HZ) +#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES +#else +#define SPI_NUM_INSTANCES 0 +#endif + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Initialize the hardware SPI peripherial + * + * @param xdesc Platform specific SPI descriptor + * @param xinit Platform specific SPI init param + * @return int32_t FAILURE if the device couldn't be found or configured + */ +static int32_t spi_init_pl(struct spi_desc *desc, + const struct spi_init_param *param) +{ +#ifdef XSPI_H + int32_t ret; + struct xil_spi_desc *xdesc; + struct xil_spi_init_param *xinit; + + xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc)); + if(!xdesc) { + free(xdesc); + return FAILURE; + } + + desc->extra = xdesc; + xinit = param->extra; + xdesc->type = xinit->type; + xdesc->flags = xinit->flags; + + xdesc->instance = (XSpi*)calloc(1, sizeof(XSpi)); + if(!xdesc->instance) + goto pl_error; + + xdesc->config = XSpi_LookupConfig(param->device_id); + if(xdesc->config == NULL) + goto pl_error; + + ret = XSpi_CfgInitialize(xdesc->instance, + xdesc->config, + ((XSpi_Config*)xdesc->config) + ->BaseAddress); + if(ret != SUCCESS) + goto pl_error; + + ret = XSpi_Initialize(xdesc->instance, param->device_id); + if (ret != SUCCESS) + goto pl_error; + + ret = XSpi_SetOptions(xdesc->instance, + XSP_MASTER_OPTION | + ((desc->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto pl_error; + + ret = XSpi_Start(xdesc->instance); + if (ret != SUCCESS) + goto pl_error; + + XSpi_IntrGlobalDisable((XSpi *)(xdesc->instance)); + + return SUCCESS; + +pl_error: + free(xdesc->instance); + free(xdesc); +#endif + return FAILURE; +} + +/** + * @brief Initialize the hardware SPI peripherial + * + * @param xdesc Platform specific SPI descriptor + * @param xinit Platform specific SPI init param + * @return int32_t FAILURE if the device couldn't be found or configured + */ +static int32_t spi_init_ps(struct spi_desc *desc, + const struct spi_init_param *param) +{ +#ifdef XSPIPS_H + int32_t ret; + struct xil_spi_desc *xdesc; + struct xil_spi_init_param *xinit; + const uint32_t prescaler_default = XSPIPS_CLK_PRESCALE_64; + const uint32_t prescaler_min = XSPIPS_CLK_PRESCALE_4; + const uint32_t prescaler_max = XSPIPS_CLK_PRESCALE_256; + uint32_t prescaler = 0u; + uint32_t input_clock = 0u; + + xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc)); + if(!xdesc) { + free(xdesc); + return FAILURE; + } + + desc->extra = xdesc; + xinit = param->extra; + xdesc->type = xinit->type; + xdesc->flags = xinit->flags; + + xdesc->instance = (XSpiPs*)malloc(sizeof(XSpiPs)); + if(!xdesc->instance) + goto ps_error; + + xdesc->config = XSpiPs_LookupConfig(param->device_id); + if(xdesc->config == NULL) + goto ps_error; + + ret = XSpiPs_CfgInitialize(xdesc->instance, + xdesc->config, + ((XSpiPs_Config*)xdesc->config) + ->BaseAddress); + if(ret != SUCCESS) + goto ps_error; + + switch (param->device_id) { +#if (SPI_NUM_INSTANCES >= 1) + case 0: + input_clock = SPI_CLK_FREQ_HZ(0); + break; +#endif +#if (SPI_NUM_INSTANCES >= 2) + case 1: + input_clock = SPI_CLK_FREQ_HZ(1); + break; +#endif + default: + goto ps_error; + }; + + if (desc->max_speed_hz != 0u) { + uint32_t div = input_clock / desc->max_speed_hz; + uint32_t rem = input_clock % desc->max_speed_hz; + uint32_t po2 = !(div & (div - 1)) && !rem; + + // find the power of two just higher than div and + // store the exponent in prescaler + while(div) { + prescaler += 1; + div >>= 1u; + } + + // this exponent - 1 is needed because of the way + // xilinx stores it into registers + if (prescaler) + prescaler -= 1; + + // this exponent - 1 is needed when initial div was + // precisely a power of two + if (prescaler && po2) + prescaler -= 1; + + if (prescaler < prescaler_min) + prescaler = prescaler_min; + + if (prescaler > prescaler_max) + prescaler = prescaler_max; + } else + prescaler = prescaler_default; + + ret = XSpiPs_SetClkPrescaler(xdesc->instance, prescaler); + + if(ret != SUCCESS) + goto ps_error; + + return SUCCESS; + +ps_error: + free(xdesc->instance); + free(xdesc); +#endif + return FAILURE; +} + +/** + * @brief Initialize the SPI communication peripheral. + * @param desc - The SPI descriptor. + * @param param - The structure that contains the SPI parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + int32_t ret; + enum xil_spi_type *spi_type; + + if (!param) { + return FAILURE; + } + + *desc = malloc(sizeof(**desc)); + if(! *desc) { + free(*desc); + return FAILURE; + } + + spi_type = param->extra; + + if(!spi_type) + goto init_error; + + (*desc)->max_speed_hz = param->max_speed_hz; + (*desc)->mode = param->mode; + (*desc)->bit_order = param->bit_order; + (*desc)->chip_select = param->chip_select; + + switch (*spi_type) { + case SPI_PL: + ret = spi_init_pl(*desc, param); + break; + case SPI_PS: + ret = spi_init_ps(*desc, param); + break; + + default: + goto init_error; + break; + } + + if (ret != SUCCESS) { +init_error: + free(*desc); + + return FAILURE; + } + + return ret; +} + +/** + * @brief Free the resources allocated by spi_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_remove(struct spi_desc *desc) +{ +#ifdef XSPI_H + int32_t ret; +#endif + struct xil_spi_desc *xdesc = NULL; + enum xil_spi_type *spi_type; + + spi_type = desc->extra; + + if(!spi_type) + return FAILURE; + + switch (*spi_type ) { + case SPI_PL: +#ifdef XSPI_H + xdesc = desc->extra; + + if(!xdesc) + return FAILURE; + + ret = XSpi_Stop((XSpi *)(xdesc->instance)); + if(ret != SUCCESS) + goto error; +#endif + break; + case SPI_PS: +#ifdef XSPIPS_H + xdesc = desc->extra; + + if(!xdesc) + return FAILURE; +#endif + break; + + /* Intended fallthrough */ +#ifdef XSPI_H +error: +#endif + default: + return FAILURE; + } + + if(xdesc) + free(xdesc->instance); + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/** + * @brief Write and read data to/from SPI. + * @param desc - The SPI descriptor. + * @param data - The buffer with the transmitted/received data. + * @param bytes_number - Number of bytes to write/read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t xil_spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number) +{ + int32_t ret; +#ifdef XSPI_H + uint32_t ctrl_reg; +#endif + struct xil_spi_desc *xdesc; + enum xil_spi_type *spi_type; + + ret = FAILURE; + + spi_type = desc->extra; + + if(!spi_type) + return FAILURE; + + xdesc = desc->extra; + + switch (*spi_type) { + case SPI_PL: +#ifdef XSPI_H + ret = XSpi_SetOptions(xdesc->instance, + XSP_MASTER_OPTION | + ((desc->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto error; + + ctrl_reg = XSpi_GetControlReg(((XSpi*)xdesc->instance)); + if (desc->bit_order == SPI_BIT_ORDER_LSB_FIRST) + ctrl_reg |= XSP_CR_LSB_MSB_FIRST_MASK; + else + ctrl_reg &= ~ XSP_CR_LSB_MSB_FIRST_MASK; + XSpi_SetControlReg(((XSpi*)xdesc->instance), ctrl_reg); + + ret = XSpi_SetSlaveSelect(xdesc->instance, + 0x01 << desc->chip_select); + if (ret != SUCCESS) + goto error; + + ret = XSpi_Transfer(xdesc->instance, + data, + data, + bytes_number); + if (ret != SUCCESS) + goto error; +#endif + break; + case SPI_PS: +#ifdef XSPIPS_H + ret = XSpiPs_SetOptions(xdesc->instance, + XSPIPS_MASTER_OPTION | + ((xdesc->flags & SPI_CS_DECODE) ? + XSPIPS_DECODE_SSELECT_OPTION : 0) | + XSPIPS_FORCE_SSELECT_OPTION | + ((desc->mode & SPI_CPOL) ? + XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSPIPS_CLK_PHASE_1_OPTION : 0)); + if (ret != SUCCESS) + goto error; + + ret = XSpiPs_SetSlaveSelect(xdesc->instance, + desc->chip_select); + if (ret != SUCCESS) + goto error; + ret = XSpiPs_PolledTransfer(xdesc->instance, + data, + data, + bytes_number); + if (ret != SUCCESS) + goto error; + ret = XSpiPs_SetSlaveSelect(xdesc->instance, SPI_DEASSERT_CURRENT_SS); + if (ret != SUCCESS) + goto error; +#endif + break; +error: + default: + return FAILURE; + } + + return ret; +} + +/** + * @brief Xilinx platform specific SPI platform ops structure + */ +const struct spi_platform_ops xil_spi_ops = { + .init = &xil_spi_init, + .write_and_read = &xil_spi_write_and_read, + .write_and_read_3wire = NULL, // Not support. + .remove = &xil_spi_remove +}; diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_spi_pl.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_spi_pl.c new file mode 100644 index 00000000..ed74cc84 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/platform/xilinx_spi_pl.c @@ -0,0 +1,531 @@ +/******************************************************************************* + * @file xilinx/xilinx_spi_pl.c + * @brief Driver for spi pl device using registers + * @author Mihail Chindris (mihail.chindris@analog.com) +******************************************************************************** + * Copyright 2021(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#include + +#ifdef XPAR_XSPI_NUM_INSTANCES + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include +#include +#include +#include "spi.h" +#include "error.h" +#include "delay.h" +#include "util.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define XPS_TYPE_WRITE 0x1 +#define XPS_TYPE_READ 0x2 +#define XSP_DEFAULT_SR_VALUE 0x25 +#define XSP_DUMMY_DATA 0xFF + +/* + * Used to store current spi device configuration in order to not update it for + * each spi transaction if not needed. + */ +static struct spi_desc g_spi_desc[XPAR_XSPI_NUM_INSTANCES]; + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/* Xilinx PL spi specific data */ +struct xspi_desc { + uint32_t base_addr; + uint32_t disable_slaves_mask; + uint32_t fifo_depth; + uint8_t cs_asserted; +}; + +/* Structure used to iterate over SPI messages */ +struct msg_iter { + struct spi_msg *msgs; + uint32_t len; + uint32_t i; + uint32_t buff_i; + uint8_t is_wr; +}; + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/* Read device register */ +static inline uint32_t _read(struct xspi_desc *xdesc, uint32_t reg) +{ + return Xil_In32(xdesc->base_addr + reg); +} + +/* Write device register */ +static inline void _write(struct xspi_desc *xdesc, uint32_t reg, uint32_t val) +{ + Xil_Out32(xdesc->base_addr + reg, val); +} + +/* Update device register. Only bits set to 1 in mask will be modified */ +static inline void _wr_mask(struct xspi_desc *xdesc, uint32_t reg, + uint32_t val, uint32_t mask) +{ + uint32_t tmp; + + tmp = _read(xdesc, reg); + tmp &= ~mask; + tmp |= val & mask; + _write(xdesc, reg, tmp); +} + +/* Update spi device configuration if needed */ +static void _update_mode(struct spi_desc *desc) +{ + uint32_t val; + uint32_t mask; + + if (desc->mode == g_spi_desc[desc->device_id].mode && + desc->bit_order == g_spi_desc[desc->device_id].bit_order) + return ; + + /* Update mode */ + val = desc->mode | SPI_CPOL ? XSP_CR_CLK_POLARITY_MASK : 0; + val |= desc->mode | SPI_CPHA ? XSP_CR_CLK_PHASE_MASK : 0; + mask = XSP_CR_CLK_POLARITY_MASK | XSP_CR_CLK_PHASE_MASK; + + val |= desc->bit_order == SPI_BIT_ORDER_LSB_FIRST ? + XSP_CR_LSB_MSB_FIRST_MASK : 0; + mask |= XSP_CR_LSB_MSB_FIRST_MASK; + + _wr_mask(desc->extra, XSP_CR_OFFSET, val, mask); + g_spi_desc[desc->device_id] = *desc; +} + +/* Configure SPI PL device */ +static int32_t _xil_spi_init_dev(struct xspi_desc *xdesc) +{ + uint32_t val; + + /* Software reset */ + _write(xdesc, XSP_SRR_OFFSET, XSP_SRR_RESET_MASK); + mdelay(1); + + /* Check if success reset */ + val = _read(xdesc, XSP_SR_OFFSET); + if (val != XSP_DEFAULT_SR_VALUE) + return -ENODEV; + + /* Disable interrupts. Drivers only works with pooled mode */ + _write(xdesc, XSP_IIER_OFFSET, 0); + + /* Deasert chip selects */ + _write(xdesc, XSP_SSR_OFFSET, 0xFFFFFFFF); + + /* Get fifo depth */ + while (!(_read(xdesc, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK)) + _write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA); + xdesc->fifo_depth = _read(xdesc, XSP_TFO_OFFSET) + 1; + + /* Configure spi device */ + val = XSP_CR_ENABLE_MASK | + XSP_CR_MANUAL_SS_MASK | + XSP_CR_TXFIFO_RESET_MASK | + XSP_CR_RXFIFO_RESET_MASK | + XSP_CR_MASTER_MODE_MASK | + XSP_CR_TRANS_INHIBIT_MASK; + + _write(xdesc, XSP_CR_OFFSET, val); + + return SUCCESS; +} + +/* Initialize spi_desc structure and device */ +static int32_t xil_spi_init_pl(struct spi_desc **desc, + const struct spi_init_param *param) +{ + struct spi_desc *ldesc; + struct xspi_desc *xdesc; + int32_t err; + XSpi_Config *cfg; + + if (!desc || !param || param->device_id >= XPAR_XSPI_NUM_INSTANCES) + return -EINVAL; + + cfg = XSpi_LookupConfig(param->device_id); + if (!cfg) + return -EINVAL; + + if (param->chip_select > cfg->NumSlaveBits) + return -EINVAL; + + ldesc = (struct spi_desc *)calloc(1, sizeof(*ldesc)); + if (!ldesc) + return -ENOMEM; + + xdesc = (struct xspi_desc *)calloc(1, sizeof(*xdesc)); + if (!xdesc) { + err = -ENOMEM; + goto error; + } + + ldesc->bit_order = param->bit_order; + ldesc->chip_select = param->chip_select; + ldesc->mode = param->mode; + xdesc->base_addr = cfg->BaseAddress; + xdesc->disable_slaves_mask = (1 << cfg->NumSlaveBits) - 1; + xdesc->cs_asserted = 0; + + err = _xil_spi_init_dev(xdesc); + if (IS_ERR_VALUE(err)) + goto error; + + ldesc->extra = xdesc; + *desc = ldesc; + + return SUCCESS; + +error: + free(xdesc); + free(ldesc); + + return err; +} + +/* Remove allocated resources */ +static int32_t xil_spi_remove_pl(struct spi_desc *desc) +{ + if (!desc) + return -EINVAL; + + free(desc->extra); + free(desc); + + return SUCCESS; +} + +/* + * Fill fifo until fifo is full or no more data available. + * Return the number of written bytes. + */ +static uint32_t _wr_fifo(struct xspi_desc *xdesc, uint8_t *data, + uint32_t len) +{ + uint32_t i; + uint32_t to_write; + uint32_t tx_available; + + tx_available = xdesc->fifo_depth - _read(xdesc, XSP_TFO_OFFSET); + to_write = min(tx_available, len); + for (i = 0; i < to_write; ++i) + if (data) + _write(xdesc, XSP_DTR_OFFSET, data[i]); + else + _write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA); + + return to_write; +} + +/* + * Read fifo until fifo is empty or no more buffer available to read into + * Returns the number of read bytes + */ +static uint32_t _rd_fifo(struct xspi_desc *xdesc, uint8_t *data, + uint32_t len) +{ + uint32_t rx_available; + uint32_t to_read; + uint32_t tmp; + uint32_t i; + + tmp = _read(xdesc, XSP_SR_OFFSET); + if (tmp & XSP_SR_RX_EMPTY_MASK) + return 0; + + rx_available = _read(xdesc, XSP_RFO_OFFSET) + 1; + to_read = min(rx_available, len); + for (i = 0; i < to_read; ++i) { + tmp = _read(xdesc, XSP_DRR_OFFSET); + if (data) + data[i] = tmp; + } + + return to_read; +} + +/* If start is 0 stop transfer, else start it. + * CS will be asserted if needed. If different CS othere than the one needed + * is asserted. Deassert it and assert correct one */ +static void _xil_spi_start_transfer(struct spi_desc *desc, uint8_t start) +{ + struct xspi_desc *xdesc; + + xdesc = desc->extra; + if (start) { + if (xdesc->cs_asserted) { + if (desc->chip_select == + g_spi_desc[desc->device_id].chip_select) + return ; + else + /* Stop transfer to start again with new CS */ + _xil_spi_start_transfer(desc, 0); + } + _write(xdesc, XSP_SSR_OFFSET, ~(1 << desc->chip_select)); + _wr_mask(xdesc, XSP_CR_OFFSET, 0, XSP_CR_TRANS_INHIBIT_MASK); + } else { + _wr_mask(xdesc, XSP_CR_OFFSET, XSP_CR_TRANS_INHIBIT_MASK, + XSP_CR_TRANS_INHIBIT_MASK); + _write(xdesc, XSP_SSR_OFFSET, xdesc->disable_slaves_mask); + } + xdesc->cs_asserted = start; +} + + +/* SPI polled transfer */ +static int32_t xil_spi_write_and_read_pl(struct spi_desc *desc, uint8_t *data, + uint16_t bytes_number) +{ + struct xspi_desc *xdesc; + uint32_t rx; + uint32_t tx; + + if (!desc || !desc->extra) + return -EINVAL; + + xdesc = desc->extra; + _update_mode(desc); + + _xil_spi_start_transfer(desc, 1); + rx = 0; + tx = 0; + while (rx < bytes_number) { + if (tx < bytes_number) + tx += _wr_fifo(xdesc, data + tx, bytes_number - tx); + rx += _rd_fifo(xdesc, data + rx, bytes_number - rx); + } + _xil_spi_start_transfer(desc, 0); + + return SUCCESS; +} + +/* Get type of message. It can be READ, WRITE or both */ +static uint32_t _get_msg_type(struct spi_msg *msg) +{ + uint32_t type; + + type = 0; + if (msg->tx_buff) + type |= XPS_TYPE_WRITE; + if (msg->rx_buff) + type |= XPS_TYPE_READ; + + return type; +} + +/* Get information based on current iterator position */ +static void _get_data(struct msg_iter *it, uint8_t **buff, uint32_t *len, + uint32_t *type) +{ + struct spi_msg *msg; + + if (it->i == it->len) { + *len = 0; + return ; + } + + msg = it->msgs + it->i; + if (it->is_wr) + *buff = msg->tx_buff; + else + *buff = msg->rx_buff; + + if (*buff) + *buff += it->buff_i; + + *len = msg->bytes_number - it->buff_i; + if (type) + *type = _get_msg_type(msg); +} + +/* + * Increment iterator position with desired length. + * If the new position has a different message type, new_type will be set to 1 + * If a CS change is needed, cs_change is set + */ +static void _increment_iter(struct msg_iter *it, uint32_t len, + uint8_t *cs_change, uint8_t *new_type) +{ + struct spi_msg *msg; + uint32_t type; + uint32_t extra_len; + + if (!len) + return ; + + *cs_change = 0; + *new_type = 0; + msg = it->msgs + it->i; + if (it->buff_i + len > msg->bytes_number) + extra_len = it->buff_i + len - msg->bytes_number; + else + extra_len = 0; + len -= extra_len; + it->buff_i += len; + if (it->buff_i == msg->bytes_number) { + type = _get_msg_type(msg); + ++it->i; + it->buff_i = 0; + if (cs_change && msg->cs_change) + *cs_change = 1; + if (new_type) + if (it->i == it->len || + type != _get_msg_type(it->msgs + it->i)) + *new_type = 1; + } + if (extra_len) + _increment_iter(it, extra_len, cs_change, new_type); +} + +/* + * SPI polling transfer of multiple messages. + */ +static int32_t xil_spi_transfer_pl(struct spi_desc *desc, struct spi_msg *msgs, + uint32_t len) + +{ + struct xspi_desc *xdesc; + uint8_t cs_change; + uint8_t new_type; + struct msg_iter rx = {.msgs = msgs, .len = len, .is_wr = 0}; + struct msg_iter tx = {.msgs = msgs, .len = len, .is_wr = 1}; + uint8_t *buff; + uint32_t bytes; + uint32_t type; + /* Bytes to increment rx when only a write transaction is executed */ + uint32_t to_inc_rx; + /* Difference between rx and tx iterators in bytes */ + uint32_t tx_advance; + /* Save bytes sent during a write loop */ + uint32_t tx_sent; + /* Used to loop if need to empty the RX FIFO */ + uint32_t loop; + + if (!desc || !desc->extra) + return -EINVAL; + + xdesc = desc->extra; + _update_mode(desc); + + tx_advance = 0; + to_inc_rx = 0; + buff = NULL; + type = 0; + do { + _xil_spi_start_transfer(desc, 1); + + tx_sent = 0; + /* Writing loop */ + do { + _get_data(&tx, &buff, &bytes, &type); + if (type & XPS_TYPE_READ) + /* + * Do not write more bytes than fifo_depth if + * they haven't been read. + */ + bytes = min(bytes, + xdesc->fifo_depth - tx_advance); + bytes = _wr_fifo(xdesc, buff, bytes); + tx_sent += bytes; + _increment_iter(&tx, bytes, &cs_change, &new_type); + tx_advance += bytes; + } while (!cs_change && !new_type && bytes); + + if (type & XPS_TYPE_READ) { + loop = 1; + /* + * Loop only when no more data to write otherwise read + * only available data. + */ + while (loop) { + if (!new_type) + loop = 0; + _get_data(&rx, &buff, &bytes, NULL); + bytes = _rd_fifo(xdesc, buff, bytes); + _increment_iter(&rx, bytes, &cs_change, &new_type); + tx_advance -= bytes; + if (loop && new_type) + break; + } + } else { + /* Clean RX FIFO if it was only a WRITE message */ + to_inc_rx += tx_sent; + if (new_type) { + /* Wait for TX to be sent */ + while (!(_read(xdesc, XSP_SR_OFFSET) & + XSP_SR_TX_EMPTY_MASK)) + ; + /* Reset fifo. Only write was performed */ + _wr_mask(xdesc, XSP_CR_OFFSET, + XSP_CR_RXFIFO_RESET_MASK, + XSP_CR_RXFIFO_RESET_MASK); + + _increment_iter(&rx, to_inc_rx, NULL, NULL); + tx_advance -= to_inc_rx; + to_inc_rx = 0; + } + } + + if ((cs_change && rx.i != len) || (!cs_change && rx.i == len)) + _xil_spi_start_transfer(desc, 0); + } while (rx.i < len); + + return SUCCESS; +} + +const struct spi_platform_ops xil_spi_reg_ops_pl = { + .init = xil_spi_init_pl, + .remove = xil_spi_remove_pl, + .write_and_read = xil_spi_write_and_read_pl, + .write_and_read_3wire = NULL, // Not support. + .transfer = xil_spi_transfer_pl +}; + +#endif // XPAR_XSPI_NUM_INSTANCES diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c new file mode 100644 index 00000000..5cf7d2d2 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c @@ -0,0 +1,151 @@ +/***************************************************************************//** + * @file ad9361_reg.c + * @brief Implementation of AD9680 Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include "ad9361_reg.h" + +#include +#include +#include "../../../include/error.h" + +/***************************************************************************//** + * @brief ad9361_reg_read + *******************************************************************************/ +int32_t ad9361_reg_read(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data) +{ + uint8_t tx_buf[2]; + uint8_t rx_buf[1]; + int32_t ret; + + tx_buf[0] = reg_addr >> 8; + tx_buf[1] = reg_addr & 0xFF; + + + ret = spi_write_and_read_3wire(dev->spi_desc, + tx_buf, rx_buf, 2, 1); + + *reg_data = rx_buf[0]; + + return ret; +} + +/***************************************************************************//** + * @brief ad9361_reg_write + *******************************************************************************/ +int32_t ad9361_reg_write(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t reg_data) +{ + uint8_t buf[3]; + + int32_t ret; + + buf[0] = 0x80 | reg_addr >> 8; + buf[1] = reg_addr & 0xFF; + buf[2] = reg_data; + + ret = spi_write_and_read_3wire(dev->spi_desc, + buf, NULL, 3, 0); + return ret; +} + +/***************************************************************************//** + * @brief ad9361_reg_init + *******************************************************************************/ +int32_t ad9361_reg_init(struct ad9361_reg_dev **device, + const struct ad9361_reg_init_param *init_param) +{ + int ret = SUCCESS; + struct ad9361_reg_dev *dev; + + dev = (struct ad9361_reg_dev *)malloc(sizeof(*dev)); + if (!dev) + return FAILURE; + + /* SPI */ + ret = spi_init(&dev->spi_desc, init_param->spi_init); + ret |= gpio_get(&dev->gpio_desc_resetb, init_param->gpio_resetb); + +// gpio_direction_output(dev->gpio_desc_resetb, 0); +// +// ad9361_reg_reset(dev); + + *device = dev; + + return ret; +} + +/** + * AD9361 Device Reset + * @param phy The AD9361 state structure. + * @return 0 in case of success, negative error code otherwise. + */ +int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev) +{ + if (dev->gpio_desc_resetb) { + gpio_set_value(dev->gpio_desc_resetb, 0); + mdelay(10); + gpio_set_value(dev->gpio_desc_resetb, 1); + mdelay(10); + return 0; + } + return 0; +} + +/***************************************************************************//** + * @brief Free the resources allocated by ad9361_reg_setup(). + * + * @param dev - The device structure. + * + * @return SUCCESS in case of success, negative error code otherwise. +*******************************************************************************/ +int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev) +{ + int32_t ret; + + ret = spi_remove(dev->spi_desc); + + free(dev); + + return ret; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h new file mode 100644 index 00000000..46c486b8 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h @@ -0,0 +1,104 @@ +/***************************************************************************//** + * @file ad9361_reg.h + * @brief Header file of ad9361_reg Driver. + * @author DBogdan (dragos.bogdan@analog.com) + ******************************************************************************** + * Copyright 2014-2016(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *******************************************************************************/ +#ifndef ad9361_reg_H_ +#define ad9361_reg_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "../../../include/delay.h" +#include "../../../include/spi.h" +#include "../../../include/gpio.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ +struct ad9361_reg_dev { + /* SPI */ + spi_desc *spi_desc; + gpio_desc *gpio_desc_resetb; +}; + +struct ad9361_reg_init_param { + /* SPI */ + spi_init_param *spi_init; + gpio_init_param *gpio_resetb; +}; + +enum Operation_Type{ + AD9361_WRITE, + AD9361_READ, + AD9361_WAIT, + AD9361_WHEN +}; + +struct ad9361_reg_config { + int operation; + uint16_t val1; + uint16_t val2; +}; + + + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +int32_t ad9361_reg_read(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t *reg_data); + +int32_t ad9361_reg_write(struct ad9361_reg_dev *dev, + uint16_t reg_addr, + uint8_t reg_data); + +int32_t ad9361_reg_init(struct ad9361_reg_dev **device, + const struct ad9361_reg_init_param *init_param); + +int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev); + +int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev); + +#endif diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/axi_io.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/axi_io.h new file mode 100644 index 00000000..92b689ab --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/axi_io.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file axi_io.h + * @brief Header file of AXI IO. + * @author Antoniu Miclaus (antoniu.miclaus@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef AXI_IO_H_ +#define AXI_IO_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* AXI IO Read data */ +int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data); + +/* AXI IO Write data */ +int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data); + +#endif // AXI_IO_H_ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/delay.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/delay.h new file mode 100644 index 00000000..7937a9d6 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/delay.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file delay.h + * @brief Header file of Delay functions + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef DELAY_H_ +#define DELAY_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Generate microseconds delay. */ +void udelay(uint32_t usecs); + +/* Generate miliseconds delay. */ +void mdelay(uint32_t msecs); + +#endif // DELAY_H_ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/error.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/error.h new file mode 100644 index 00000000..275b126d --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/error.h @@ -0,0 +1,67 @@ +/***************************************************************************//** + * @file error.h + * @brief Error codes definition + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef ERROR_H_ +#define ERROR_H_ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#ifdef SUCCESS +#undef SUCCESS +#endif +#define SUCCESS 0 +#ifdef FAILURE +#undef FAILURE +#endif +#define FAILURE -1 + +#ifndef __ELASTERROR +#define __ELASTERROR 2000 +#endif + +#define EOVERRUN (__ELASTERROR + 1) /* Circular buffer overrun */ + + +#define IS_ERR_VALUE(x) ((x) < 0) + +#endif // ERROR_H_ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/gpio.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/gpio.h new file mode 100644 index 00000000..5c057cb4 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/gpio.h @@ -0,0 +1,165 @@ +/***************************************************************************//** + * @file gpio.h + * @brief Header file of GPIO Interface + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef GPIO_H_ +#define GPIO_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define GPIO_OUT 0x01 +#define GPIO_IN 0x00 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @struct gpio_platform_ops + * @brief Structure holding gpio function pointers that point to the platform + * specific function + */ +struct gpio_platform_ops ; + +/** + * @struct gpio_init_param + * @brief Structure holding the parameters for GPIO initialization. + */ +typedef struct gpio_init_param { + /** GPIO number */ + int32_t number; + /** GPIO platform specific functions */ + const struct gpio_platform_ops *platform_ops; + /** GPIO extra parameters (device specific) */ + void *extra; +} gpio_init_param; + +/** + * @struct gpio_desc + * @brief Structure holding the GPIO descriptor. + */ +typedef struct gpio_desc { + /** GPIO number */ + int32_t number; + /** GPIO platform specific functions */ + const struct gpio_platform_ops *platform_ops; + /** GPIO extra parameters (device specific) */ + void *extra; +} gpio_desc; + +/** + * @enum gpio_values + * @brief Enum that holds the possible output states of a GPIO. + */ +enum gpio_values { + /** GPIO logic low */ + GPIO_LOW, + /** GPIO logic high */ + GPIO_HIGH, + /** GPIO high impedance */ + GPIO_HIGH_Z +}; + +/** + * @struct gpio_platform_ops + * @brief Structure holding gpio function pointers that point to the platform + * specific function + */ +struct gpio_platform_ops { + /** gpio initialization function pointer */ + int32_t (*gpio_ops_get)(struct gpio_desc **, const struct gpio_init_param *); + /** gpio optional descriptor function pointer */ + int32_t (*gpio_ops_get_optional)(struct gpio_desc **, + const struct gpio_init_param *); + /** gpio remove function pointer */ + int32_t (*gpio_ops_remove)(struct gpio_desc *); + /** gpio direction input function pointer */ + int32_t (*gpio_ops_direction_input)(struct gpio_desc *); + /** gpio direction output function pointer */ + int32_t (*gpio_ops_direction_output)(struct gpio_desc *, uint8_t); + /** gpio get direction function pointer */ + int32_t (*gpio_ops_get_direction)(struct gpio_desc *, uint8_t *); + /** gpio set value function pointer */ + int32_t (*gpio_ops_set_value)(struct gpio_desc *, uint8_t); + /** gpio get value function pointer */ + int32_t (*gpio_ops_get_value)(struct gpio_desc *, uint8_t *); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Obtain the GPIO decriptor. */ +int32_t gpio_get(struct gpio_desc **desc, + const struct gpio_init_param *param); + +/* Obtain optional GPIO descriptor. */ +int32_t gpio_get_optional(struct gpio_desc **desc, + const struct gpio_init_param *param); + +/* Free the resources allocated by gpio_get() */ +int32_t gpio_remove(struct gpio_desc *desc); + +/* Enable the input direction of the specified GPIO. */ +int32_t gpio_direction_input(struct gpio_desc *desc); + +/* Enable the output direction of the specified GPIO. */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value); + +/* Get the direction of the specified GPIO. */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction); + +/* Set the value of the specified GPIO. */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value); + +/* Get the value of the specified GPIO. */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value); + +#endif // GPIO_H_ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/irq.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/irq.h new file mode 100644 index 00000000..7db97e90 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/irq.h @@ -0,0 +1,188 @@ +/***************************************************************************//** + * @file irq.h + * @brief Header file of IRQ interface. + * @author Cristian Pop (cristian.pop@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef IRQ_H_ +#define IRQ_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum irq_uart_event_e + * @brief Possible events for uart interrupt + */ +enum irq_uart_event_e { + /** Write operation finalized */ + IRQ_WRITE_DONE, + /** Read operation finalized */ + IRQ_READ_DONE, + /** An error occurred */ + IRQ_ERROR +}; + +enum irq_trig_level { + IRQ_LEVEL_LOW, + IRQ_LEVEL_HIGH, + IRQ_EDGE_FALLING, + IRQ_EDGE_RISING, + IRQ_EDGE_BOTH +}; + +/** + * @struct irq_platform_ops + * @brief Structure holding IRQ function pointers that point to the platform + * specific function + */ +struct irq_platform_ops ; + +/** + * @struct irq_init_param + * @brief Structure holding the initial parameters for Interrupt Request. + */ +struct irq_init_param { + /** Interrupt request controller ID. */ + uint32_t irq_ctrl_id; + /** Platform specific IRQ platform ops structure. */ + const struct irq_platform_ops *platform_ops; + /** IRQ extra parameters (device specific) */ + void *extra; +}; + +/** + * @struct irq_desc + * @brief Structure for Interrupt Request descriptor. + */ +struct irq_ctrl_desc { + /** Interrupt request controller ID. */ + uint32_t irq_ctrl_id; + /** Platform specific IRQ platform ops structure. */ + const struct irq_platform_ops *platform_ops; + /** IRQ extra parameters (device specific) */ + void *extra; +}; + +/** + * @struct callback_desc + * @brief Structure describing a callback to be registered + */ +struct callback_desc { + /** + * Callback to be called when the event an event occurs + * @param ctx - Same as \ref callback_desc.ctx + * @param event - Event that generated the callback + * @param extra - Platform specific data + */ + void (*callback)(void *ctx, uint32_t event, void *extra); + /** Parameter to be passed when the callback is called */ + void *ctx; + /** Platform specific configuration for a callback */ + void *config; +}; + +/** + * @struct irq_platform_ops + * @brief Structure holding IRQ function pointers that point to the platform + * specific function + */ +struct irq_platform_ops { + /** Initialize a interrupt controller peripheral. */ + int32_t (*init)(struct irq_ctrl_desc **desc, + const struct irq_init_param *param); + /** Register a callback to handle the irq events */ + int32_t (*register_callback)(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc); + /** Unregisters a generic IRQ handling function */ + int32_t (*unregister)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** Global interrupt enable */ + int32_t (*global_enable)(struct irq_ctrl_desc *desc); + /** Global interrupt disable */ + int32_t (*global_disable)(struct irq_ctrl_desc *desc); + /** Set interrupt trigger level. */ + int32_t (*trigger_level_set)(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig); + /** Enable specific interrupt */ + int32_t (*enable)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** Disable specific interrupt */ + int32_t (*disable)(struct irq_ctrl_desc *desc, uint32_t irq_id); + /** IRQ remove function pointer */ + int32_t (*remove)(struct irq_ctrl_desc *desc); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Initialize a interrupt controller peripheral. */ +int32_t irq_ctrl_init(struct irq_ctrl_desc **desc, + const struct irq_init_param *param); + +/* Free the resources allocated by irq_ctrl_init(). */ +int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc); + +/* Register a callback to handle the irq events */ +int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id, + struct callback_desc *callback_desc); + +/* Unregisters a generic IRQ handling function */ +int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id); + +/* Global interrupt enable */ +int32_t irq_global_enable(struct irq_ctrl_desc *desc); + +/* Global interrupt disable */ +int32_t irq_global_disable(struct irq_ctrl_desc *desc); + +/* Set interrupt trigger level. */ +int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id, + enum irq_trig_level trig); + +/* Enable specific interrupt */ +int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id); + +/* Disable specific interrupt */ +int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id); + +#endif // IRQ_H_ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/spi.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/spi.h new file mode 100644 index 00000000..0e9b8e0d --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/spi.h @@ -0,0 +1,194 @@ +/***************************************************************************//** + * @file spi.h + * @brief Header file of SPI Interface + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2019(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef SPI_H_ +#define SPI_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ + +#include + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define SPI_CPHA 0x01 +#define SPI_CPOL 0x02 +#define SPI_3WIRE 0x04 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +/** + * @enum spi_mode + * @brief SPI configuration for clock phase and polarity. + */ +typedef enum spi_mode { + /** Data on rising, shift out on falling */ + SPI_MODE_0 = (0 | 0), + /** Data on falling, shift out on rising */ + SPI_MODE_1 = (0 | SPI_CPHA), + /** Data on falling, shift out on rising */ + SPI_MODE_2 = (SPI_CPOL | 0), + /** Data on rising, shift out on falling */ + SPI_MODE_3 = (SPI_CPOL | SPI_CPHA), + /** Data on rising, shift out on falling */ + SPI_MODE_4 = SPI_3WIRE +} spi_mode; + +/** + * @enum spi_bit_order + * @brief SPI configuration for bit order (MSB/LSB). + */ +typedef enum spi_bit_order { + /** Most-significant bit (MSB) first */ + SPI_BIT_ORDER_MSB_FIRST = 0, + /** Least-significant bit (LSB) first */ + SPI_BIT_ORDER_LSB_FIRST = 1, +} spi_bit_order; + +/** + * @struct spi_msg_list + * @brief List item describing a SPI transfer + */ +struct spi_msg { + /** Buffer with data to send. If NULL, 0x00 will be sent */ + uint8_t *tx_buff; + /** Buffer where to store data. If NULL, incoming data won't be saved */ + uint8_t *rx_buff; + /** Length of buffers. Must have equal size. */ + uint32_t bytes_number; + /** If set, CS will be deasserted after the transfer */ + uint8_t cs_change; +}; + +/** + * @struct spi_platform_ops + * @brief Structure holding SPI function pointers that point to the platform + * specific function + */ +struct spi_platform_ops ; + +/** + * @struct spi_init_param + * @brief Structure holding the parameters for SPI initialization + */ +typedef struct spi_init_param { + /** Device ID */ + uint32_t device_id; + /** maximum transfer speed */ + uint32_t max_speed_hz; + /** SPI chip select */ + uint8_t chip_select; + /** SPI mode */ + enum spi_mode mode; + /** SPI bit order */ + enum spi_bit_order bit_order; + const struct spi_platform_ops *platform_ops; + /** SPI extra parameters (device specific) */ + void *extra; +} spi_init_param; + +/** + * @struct spi_desc + * @brief Structure holding SPI descriptor. + */ +typedef struct spi_desc { + /** Device ID */ + uint32_t device_id; + /** maximum transfer speed */ + uint32_t max_speed_hz; + /** SPI chip select */ + uint8_t chip_select; + /** SPI mode */ + enum spi_mode mode; + /** SPI bit order */ + enum spi_bit_order bit_order; + const struct spi_platform_ops *platform_ops; + /** SPI extra parameters (device specific) */ + void *extra; +} spi_desc; + +/** + * @struct spi_platform_ops + * @brief Structure holding SPI function pointers that point to the platform + * specific function + */ +struct spi_platform_ops { + /** SPI initialization function pointer */ + int32_t (*init)(struct spi_desc **, const struct spi_init_param *); + /** SPI write/read function pointer */ + int32_t (*write_and_read)(struct spi_desc *, uint8_t *, uint16_t); + /** SPI write function pointer */ + int32_t (*write_and_read_3wire)(struct spi_desc *, uint8_t *,uint8_t *,uint16_t, uint16_t); + /** Iterate over the spi_msg array and send all messages at once */ + int32_t (*transfer)(struct spi_desc *, struct spi_msg *, uint32_t); + /** SPI remove function pointer */ + int32_t (*remove)(struct spi_desc *); +}; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Initialize the SPI communication peripheral. */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param); + +/* Free the resources allocated by spi_init(). */ +int32_t spi_remove(struct spi_desc *desc); + +/* Write and read data to/from SPI. */ +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint16_t bytes_number); +int32_t spi_write_and_read_3wire(struct spi_desc *desc, + uint8_t *write_data, + uint8_t *read_data, + uint16_t write_bytes_number, + uint16_t read_bytes_number); + +/* Iterate over the spi_msg array and send all messages at once */ +int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len); + + +#endif // SPI_H_ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/util.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/util.h new file mode 100644 index 00000000..4255cd96 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/include/util.h @@ -0,0 +1,165 @@ +/***************************************************************************//** + * @file util.h + * @brief Implementation of utility functions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef UTIL_H_ +#define UTIL_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#define BIT(x) (1 << (x)) + +#define ARRAY_SIZE(x) \ + (sizeof(x) / sizeof((x)[0])) + +#define DIV_ROUND_UP(x,y) \ + (((x) + (y) - 1) / (y)) +#define DIV_ROUND_CLOSEST(x, y) \ + (((x) + (y) / 2) / (y)) +#define DIV_ROUND_CLOSEST_ULL(x, y) \ + DIV_ROUND_CLOSEST(x, y) + +#define min(x, y) \ + (((x) < (y)) ? (x) : (y)) +#define min_t(type, x, y) \ + (type)min((type)(x), (type)(y)) + +#define max(x, y) \ + (((x) > (y)) ? (x) : (y)) +#define max_t(type, x, y) \ + (type)max((type)(x), (type)(y)) + +#define clamp(val, min_val, max_val) \ + (max(min((val), (max_val)), (min_val))) +#define clamp_t(type, val, min_val, max_val) \ + (type)clamp((type)(val), (type)(min_val), (type)(max_val)) + +#define swap(x, y) \ + {typeof(x) _tmp_ = (x); (x) = (y); (y) = _tmp_;} + +#define round_up(x,y) \ + (((x)+(y)-1)/(y)) + +#define BITS_PER_LONG 32 + +#define GENMASK(h, l) ({ \ + uint32_t t = (uint32_t)(~0UL); \ + t = t << (BITS_PER_LONG - (h - l + 1)); \ + t = t >> (BITS_PER_LONG - (h + 1)); \ + t; \ +}) + +#define bswap_constant_32(x) \ + ((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | (((x) & 0x000000ff) << 24)) + +#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \ + (((x) & (uint16_t)0x00ff) << 8)) + +#define bit_swap_constant_8(x) \ + ((((x) & 0x80) >> 7) | \ + (((x) & 0x40) >> 5) | \ + (((x) & 0x20) >> 3) | \ + (((x) & 0x10) >> 1) | \ + (((x) & 0x08) << 1) | \ + (((x) & 0x04) << 3) | \ + (((x) & 0x02) << 5) | \ + (((x) & 0x01) << 7)) + +#define U16_MAX ((uint16_t)~0U) +#define S16_MAX ((int16_t)(U16_MAX>>1)) + +#define DIV_U64(x, y) (x / y) + +#define UNUSED_PARAM(x) ((void)x) + +#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s)) + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ +/* Find first set bit in word. */ +uint32_t find_first_set_bit(uint32_t word); +/* Find last set bit in word. */ +uint32_t find_last_set_bit(uint32_t word); +/* Locate the closest element in an array. */ +uint32_t find_closest(int32_t val, + const int32_t *array, + uint32_t size); +/* Shift the value and apply the specified mask. */ +uint32_t field_prep(uint32_t mask, uint32_t val); +/* Get a field specified by a mask from a word. */ +uint32_t field_get(uint32_t mask, uint32_t word); +/* Log base 2 of the given number. */ +int32_t log_base_2(uint32_t x); +/* Find greatest common divisor of the given two numbers. */ +uint32_t greatest_common_divisor(uint32_t a, + uint32_t b); +/* Calculate best rational approximation for a given fraction. */ +void rational_best_approximation(uint32_t given_numerator, + uint32_t given_denominator, + uint32_t max_numerator, + uint32_t max_denominator, + uint32_t *best_numerator, + uint32_t *best_denominator); +/* Calculate the number of set bits. */ +uint32_t hweight8(uint32_t word); +/* Calculate the quotient and the remainder of an integer division. */ +uint64_t do_div(uint64_t* n, + uint64_t base); +/* Unsigned 64bit divide with 64bit divisor and remainder */ +uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, + uint64_t *remainder); +/* Unsigned 64bit divide with 32bit divisor with remainder */ +uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder); +int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder); +/* Unsigned 64bit divide with 32bit divisor */ +uint64_t div_u64(uint64_t dividend, uint32_t divisor); +int64_t div_s64(int64_t dividend, int32_t divisor); +/* Converts from string to int32_t */ +int32_t str_to_int32(const char *str); +/* Converts from string to uint32_t */ +uint32_t srt_to_uint32(const char *str); +#endif // UTIL_H_ + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/util/util.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/util/util.c new file mode 100644 index 00000000..58c6a83f --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/adi_noos/util/util.c @@ -0,0 +1,283 @@ +/***************************************************************************//** + * @file util.c + * @brief Implementation of utility functions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#include "errno.h" +#include "../include/util.h" + +/******************************************************************************/ +/************************** Functions Implementation **************************/ +/******************************************************************************/ + +/** + * Find first set bit in word. + */ +uint32_t find_first_set_bit(uint32_t word) +{ + uint32_t first_set_bit = 0; + + while (word) { + if (word & 0x1) + return first_set_bit; + word >>= 1; + first_set_bit ++; + } + + return 32; +} + +/** + * Find last set bit in word. + */ +uint32_t find_last_set_bit(uint32_t word) +{ + uint32_t bit = 0; + uint32_t last_set_bit = 32; + + while (word) { + if (word & 0x1) + last_set_bit = bit; + word >>= 1; + bit ++; + } + + return last_set_bit; +} + +/** + * Locate the closest element in an array. + */ +uint32_t find_closest(int32_t val, + const int32_t *array, + uint32_t size) +{ + int32_t diff = abs(array[0] - val); + uint32_t ret = 0; + uint32_t i; + + for (i = 1; i < size; i++) { + if (abs(array[i] - val) < diff) { + diff = abs(array[i] - val); + ret = i; + } + } + + return ret; +} + +/** + * Shift the value and apply the specified mask. + */ +uint32_t field_prep(uint32_t mask, uint32_t val) +{ + return (val << find_first_set_bit(mask)) & mask; +} + +/** + * Get a field specified by a mask from a word. + */ +uint32_t field_get(uint32_t mask, uint32_t word) +{ + return (word & mask) >> find_first_set_bit(mask); +} + +/** + * Log base 2 of the given number. + */ +int32_t log_base_2(uint32_t x) +{ + return find_last_set_bit(x); +} + +/** + * Find greatest common divisor of the given two numbers. + */ +uint32_t greatest_common_divisor(uint32_t a, + uint32_t b) +{ + uint32_t div; + uint32_t common_div = 1; + + if ((a == 0) || (b == 0)) + return max(a, b); + + for (div = 1; (div <= a) && (div <= b); div++) + if (!(a % div) && !(b % div)) + common_div = div; + + return common_div; +} + +/** + * Calculate best rational approximation for a given fraction. + */ +void rational_best_approximation(uint32_t given_numerator, + uint32_t given_denominator, + uint32_t max_numerator, + uint32_t max_denominator, + uint32_t *best_numerator, + uint32_t *best_denominator) +{ + uint32_t gcd; + + gcd = greatest_common_divisor(given_numerator, given_denominator); + + *best_numerator = given_numerator / gcd; + *best_denominator = given_denominator / gcd; + + if ((*best_numerator > max_numerator) || + (*best_denominator > max_denominator)) { + *best_numerator = 0; + *best_denominator = 0; + } +} + +/** + * Calculate the number of set bits. + */ +uint32_t hweight8(uint32_t word) +{ + uint32_t count = 0; + + while (word) { + if (word & 0x1) + count++; + word >>= 1; + } + + return count; +} + +/** + * Calculate the quotient and the remainder of an integer division. + */ +uint64_t do_div(uint64_t* n, + uint64_t base) +{ + uint64_t mod = 0; + + mod = *n % base; + *n = *n / base; + + return mod; +} + +/** + * Unsigned 64bit divide with 64bit divisor and remainder + */ +uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder) +{ + *remainder = dividend % divisor; + + return dividend / divisor; +} + +/** + * Unsigned 64bit divide with 32bit divisor with remainder + */ +uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) +{ + *remainder = do_div(÷nd, divisor); + + return dividend; +} + +/** + * Signed 64bit divide with 32bit divisor with remainder + */ +int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +/** + * Unsigned 64bit divide with 32bit divisor + */ +uint64_t div_u64(uint64_t dividend, uint32_t divisor) +{ + uint32_t remainder; + + return div_u64_rem(dividend, divisor, &remainder); +} + +/** + * Signed 64bit divide with 32bit divisor + */ +int64_t div_s64(int64_t dividend, int32_t divisor) +{ + int32_t remainder; + return div_s64_rem(dividend, divisor, &remainder); +} + +/** + * Converts from string to int32_t + * @param *str + * @return int32_t + */ +int32_t str_to_int32(const char *str) +{ + char *end; + int32_t value = strtol(str, &end, 0); + + if (end == str) + return -EINVAL; + else + return value; +} + +/** + * Converts from string to uint32_t + * @param *str + * @return uint32_t + */ +uint32_t srt_to_uint32(const char *str) +{ + char *end; + uint32_t value = strtoul(str, &end, 0); + + if (end == str) + return -EINVAL; + else + return value; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/app_config.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/app_config.h new file mode 100644 index 00000000..d8ec3859 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/app_config.h @@ -0,0 +1,55 @@ +/***************************************************************************//** + * @file app_config.h + * @brief Config file of AD9361/API Driver. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2015(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef CONFIG_H_ +#define CONFIG_H_ + +#define XILINX_PLATFORM +#define SPI_INTERFACE_SPI_ENGINE + +#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ +#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/ + +#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */ +#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */ +#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */ + +#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */ +//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */ + +#endif diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/ad9361_reg_profile.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/ad9361_reg_profile.c new file mode 100644 index 00000000..6522be2a --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/ad9361_reg_profile.c @@ -0,0 +1,1243 @@ +#include "dev_profile.h" +#include "../app_config.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h" + +#define TIMEOUT_TH 2000 + +// ad9361-1 +static spi_init_param ad9361_1_reg_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_1, + .chip_select = SPI_CS_AD9361_1, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +static gpio_init_param ad9361_1_reg_gpio_resetb_init = { + .number = AD9361_1_RESET_B, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM +}; +struct ad9361_reg_init_param ad9361_1_reg_default_init_param = { + /* SPI */ + .spi_init = &ad9361_1_reg_spi_init, + .gpio_resetb = &ad9361_1_reg_gpio_resetb_init +}; + +// ad9361-2 +static spi_init_param ad9361_2_reg_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_1, + .chip_select = SPI_CS_AD9361_2, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +static gpio_init_param ad9361_2_reg_gpio_resetb_init = { + .number = AD9361_2_RESET_B, + .platform_ops = GPIO_OPS, + .extra = GPIO_PARAM +}; +struct ad9361_reg_init_param ad9361_2_reg_default_init_param = { + /* SPI */ + .spi_init = &ad9361_2_reg_spi_init, + .gpio_resetb = &ad9361_2_reg_gpio_resetb_init +}; + +uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){ + int32_t status = 0; + uint8_t value = 0; + int32_t time_out_cnt = 0; + +//************************************************************ +// AD9361 R2 Auto Generated Initialization Script: This script was +// generated using the AD9361 Customer software Version 2.1.3 +//************************************************************ +// Profile: Custom +// REFCLK_IN: 25.000 MHz + + + status = ad9361_reg_write(dev, 0x03DF, 0x01); // Required for proper operation + status = ad9361_reg_write(dev, 0x02A6, 0x0E); // Enable Master Bias + status = ad9361_reg_write(dev, 0x02A8, 0x0E); // Set Bandgap Trim + status = ad9361_reg_write(dev, 0x02AB, 0x07); // Set RF PLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x02AC, 0xFF); // Set RF PLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x0009, 0x17); // Enable Clocks + mdelay(20) ;// waits 20 ms + +//************************************************************ +// Set BBPLL Frequency: 1152.000000 +//************************************************************ + status = ad9361_reg_write(dev, 0x0045, 0x03); // Set BBPLL reflclk scale to REFCLK * 2 + status = ad9361_reg_write(dev, 0x0046, 0x03); // Set BBPLL Loop Filter Charge Pump current + status = ad9361_reg_write(dev, 0x0048, 0xE8); // Set BBPLL Loop Filter C1, R1 + status = ad9361_reg_write(dev, 0x0049, 0x5B); // Set BBPLL Loop Filter R2, C2, C1 + status = ad9361_reg_write(dev, 0x004A, 0x35); // Set BBPLL Loop Filter C3,R2 + status = ad9361_reg_write(dev, 0x004B, 0xE0); // Allow calibration to occur and set cal count to 1024 for max accuracy + status = ad9361_reg_write(dev, 0x004E, 0x10); // Set calibration clock to REFCLK/4 for more accuracy + status = ad9361_reg_write(dev, 0x0043, 0x66); // BBPLL Freq Word (Fractional[7:0]) + status = ad9361_reg_write(dev, 0x0042, 0x46); // BBPLL Freq Word (Fractional[15:8]) + status = ad9361_reg_write(dev, 0x0041, 0x01); // BBPLL Freq Word (Fractional[23:16]) + status = ad9361_reg_write(dev, 0x0044, 0x17); // BBPLL Freq Word (Integer[7:0]) + status = ad9361_reg_write(dev, 0x003F, 0x05); // Start BBPLL Calibration + status = ad9361_reg_write(dev, 0x003F, 0x01); // Clear BBPLL start calibration bit + status = ad9361_reg_write(dev, 0x004C, 0x86); // Increase BBPLL KV and phase margin + status = ad9361_reg_write(dev, 0x004D, 0x01); // Increase BBPLL KV and phase margin + status = ad9361_reg_write(dev, 0x004D, 0x05); // Increase BBPLL KV and phase margin + + // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 276.480 us (Done when 0x05E[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x005E, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + + status = ad9361_reg_write(dev, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels + status = ad9361_reg_write(dev, 0x0003, 0xE4); // Setup Rx Digital Filters/ Channels + status = ad9361_reg_write(dev, 0x0004, 0x03); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + status = ad9361_reg_write(dev, 0x000A, 0x12); // Set BBPLL post divide rate + +//************************************************************ +// Setup the Parallel Port (Digital Data Interface) +//************************************************************ + status = ad9361_reg_write(dev, 0x0010, 0xC8); // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK + status = ad9361_reg_write(dev, 0x0011, 0x00); // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data + status = ad9361_reg_write(dev, 0x0012, 0x02); // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits + status = ad9361_reg_write(dev, 0x0006, 0x00); // PPORT Rx Delay (adjusts Tco Dataclk->Data) + status = ad9361_reg_write(dev, 0x0007, 0x08); // PPORT TX Delay (adjusts setup/hold FBCLK->Data) + +//************************************************************ +// Setup AuxDAC +//************************************************************ + status = ad9361_reg_write(dev, 0x0018, 0x00); // AuxDAC1 Word[9:2] + status = ad9361_reg_write(dev, 0x0019, 0x00); // AuxDAC2 Word[9:2] + status = ad9361_reg_write(dev, 0x001A, 0x00); // AuxDAC1 Config and Word[1:0] + status = ad9361_reg_write(dev, 0x001B, 0x00); // AuxDAC2 Config and Word[1:0] + status = ad9361_reg_write(dev, 0x0023, 0xFF); // AuxDAC Manaul/Auto Control + status = ad9361_reg_write(dev, 0x0026, 0x00); // AuxDAC Manual Select Bit/GPO Manual Select + status = ad9361_reg_write(dev, 0x0030, 0x00); // AuxDAC1 Rx Delay + status = ad9361_reg_write(dev, 0x0031, 0x00); // AuxDAC1 Tx Delay + status = ad9361_reg_write(dev, 0x0032, 0x00); // AuxDAC2 Rx Delay + status = ad9361_reg_write(dev, 0x0033, 0x00); // AuxDAC2 Tx Delay + +//************************************************************ +// Setup AuxADC +//************************************************************ + status = ad9361_reg_write(dev, 0x000B, 0x00); // Temp Sensor Setup (Offset) + status = ad9361_reg_write(dev, 0x000C, 0x00); // Temp Sensor Setup (Temp Window) + status = ad9361_reg_write(dev, 0x000D, 0x03); // Temp Sensor Setup (Periodic Measure) + status = ad9361_reg_write(dev, 0x000F, 0x04); // Temp Sensor Setup (Decimation) + status = ad9361_reg_write(dev, 0x001C, 0x00); // AuxADC Setup (Clock Div) + status = ad9361_reg_write(dev, 0x001D, 0x01); // AuxADC Setup (Decimation/Enable) + +//************************************************************ +// Setup Control Outs +//************************************************************ + status = ad9361_reg_write(dev, 0x0035, 0x00); // Ctrl Out index + status = ad9361_reg_write(dev, 0x0036, 0xFF); // Ctrl Out [7:0] output enable + +//************************************************************ +// Setup GPO +//************************************************************ + status = ad9361_reg_write(dev, 0x003A, 0x18); // Set number of REFCLK cycles for 1us delay timer + status = ad9361_reg_write(dev, 0x0020, 0x00); // GPO Auto Enable Setup in RX and TX + status = ad9361_reg_write(dev, 0x0027, 0x00); // GPO Manual and GPO auto value in ALERT + status = ad9361_reg_write(dev, 0x0028, 0x00); // GPO_0 RX Delay + status = ad9361_reg_write(dev, 0x0029, 0x00); // GPO_1 RX Delay + status = ad9361_reg_write(dev, 0x002A, 0x00); // GPO_2 RX Delay + status = ad9361_reg_write(dev, 0x002B, 0x00); // GPO_3 RX Delay + status = ad9361_reg_write(dev, 0x002C, 0x00); // GPO_0 TX Delay + status = ad9361_reg_write(dev, 0x002D, 0x00); // GPO_1 TX Delay + status = ad9361_reg_write(dev, 0x002E, 0x00); // GPO_2 TX Delay + status = ad9361_reg_write(dev, 0x002F, 0x00); // GPO_3 TX Delay + +//************************************************************ +// Setup RF PLL non-frequency-dependent registers +//************************************************************ + status = ad9361_reg_write(dev, 0x0261, 0x00); // Set Rx LO Power mode + status = ad9361_reg_write(dev, 0x02A1, 0x00); // Set Tx LO Power mode + status = ad9361_reg_write(dev, 0x0248, 0x0B); // Enable Rx VCO LDO + status = ad9361_reg_write(dev, 0x0288, 0x0B); // Enable Tx VCO LDO + status = ad9361_reg_write(dev, 0x0246, 0x02); // Set VCO Power down TCF bits + status = ad9361_reg_write(dev, 0x0286, 0x02); // Set VCO Power down TCF bits + status = ad9361_reg_write(dev, 0x0249, 0x8E); // Set VCO cal length + status = ad9361_reg_write(dev, 0x0289, 0x8E); // Set VCO cal length + status = ad9361_reg_write(dev, 0x023B, 0x80); // Enable Rx VCO cal + status = ad9361_reg_write(dev, 0x027B, 0x80); // Enable Tx VCO cal + status = ad9361_reg_write(dev, 0x0243, 0x0D); // Set Rx prescaler bias + status = ad9361_reg_write(dev, 0x0283, 0x0D); // Set Tx prescaler bias + status = ad9361_reg_write(dev, 0x023D, 0x00); // Clear Half VCO cal clock setting + status = ad9361_reg_write(dev, 0x027D, 0x00); // Clear Half VCO cal clock setting + + status = ad9361_reg_write(dev, 0x0015, 0x0C); // Set Dual Synth mode bit + status = ad9361_reg_write(dev, 0x0014, 0x1D); // Set Force ALERT State bit + status = ad9361_reg_write(dev, 0x0013, 0x01); // Set ENSM FDD mode + mdelay(1); // waits 1 ms + + status = ad9361_reg_write(dev, 0x023D, 0x04); // Start RX CP cal + + // Wait for CP cal to complete, Max RXCP Cal time: 737.280 (us)(Done when 0x244[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0244, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x027D, 0x04); // Start TX CP cal + + // Wait for CP cal to complete, Max TXCP Cal time: 737.280 (us)(Done when 0x284[7]==1) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0284, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x80 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x023D, 0x00); // Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT + status = ad9361_reg_write(dev, 0x027D, 0x00); // Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT +//************************************************************ +// FDD RX,TX Synth Frequency: 125.000000,4125.000000 MHz +//************************************************************ +//************************************************************ +// Setup Rx Frequency-Dependent Syntheisizer Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x023A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0239, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0242, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0238, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0245, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0251, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0250, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x023B, 0x94); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x023E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x023F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0240, 0x0A); // Set Synth Loop Filter R3 + +//************************************************************ +// Setup Tx Frequency-Dependent Syntheisizer Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + +//************************************************************ +// Write Rx and Tx Frequency Words +//************************************************************ + status = ad9361_reg_write(dev, 0x0233, 0x00); // Write Rx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0234, 0x00); // Write Rx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0235, 0x00); // Write Rx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0232, 0x00); // Write Rx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0231, 0xA0); // Write Rx Synth Integer Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x05); // Set LO divider setting + +//************************************************************ +// Program Mixer GM Sub-table +//************************************************************ + status = ad9361_reg_write(dev, 0x013F, 0x02); // Start Clock + status = ad9361_reg_write(dev, 0x0138, 0x0F); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x78); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x00); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0E); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x74); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x0D); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0D); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x70); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x15); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0C); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x6C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x1B); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0B); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x68); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x21); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x0A); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x64); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x25); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x09); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x60); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x29); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x08); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x5C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x2C); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x07); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x58); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x2F); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x06); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x54); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x31); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x05); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x50); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x33); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x04); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x4C); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x34); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x03); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x48); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x35); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x02); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x30); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3A); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x01); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x18); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3D); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x0138, 0x00); // Addr Table Index + status = ad9361_reg_write(dev, 0x0139, 0x00); // Gain + status = ad9361_reg_write(dev, 0x013A, 0x00); // Bias + status = ad9361_reg_write(dev, 0x013B, 0x3E); // GM + status = ad9361_reg_write(dev, 0x013F, 0x06); // Write Words + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x013F, 0x02); // Clear Write Bit + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) + status = ad9361_reg_write(dev, 0x013C, 0x00); // Delay ~1us (Dummy Write) + status = ad9361_reg_write(dev, 0x013F, 0x00); // Stop Clock + +//************************************************************ +// Program Rx Gain Tables with GainTable800MHz.csv +//************************************************************ + + status = ad9361_reg_write(dev, 0x0137, 0x1A); // Start Gain Table Clock + status = ad9361_reg_write(dev, 0x0130, 0x00); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x01); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x02); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x03); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x01); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x04); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x02); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x05); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x03); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x06); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x04); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x07); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x05); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x08); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x03); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x09); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x04); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x05); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x06); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x07); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x08); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x09); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x0F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x10); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x11); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x12); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x13); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x01); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x14); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x09); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x15); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x16); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x17); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x18); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x19); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x0F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x10); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x02); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x28); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x1F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x29); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x20); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x21); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x04); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x22); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x24); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x20); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x23); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x24); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x21); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x24); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x20); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x25); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x21); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x26); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x22); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x27); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x23); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x28); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x24); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x29); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x25); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x26); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x27); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x28); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x29); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2A); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x2F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2B); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x30); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2C); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x31); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2D); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x32); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x33); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x34); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x30); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x35); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x31); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x36); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x44); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x32); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x37); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2E); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x38); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x2F); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x39); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x30); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x31); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x32); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x33); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x34); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x35); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x3F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x36); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x40); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x37); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x41); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x64); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x42); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x65); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x43); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x66); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x44); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x67); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x45); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x68); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x46); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x69); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x47); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6A); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x48); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6B); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x49); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6C); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6D); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4B); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6E); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4C); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x6F); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x38); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x20); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4D); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4E); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x4F); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x50); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x51); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x52); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x53); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x54); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x55); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x56); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x57); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x58); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x59); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0130, 0x5A); // Gain Table Index + status = ad9361_reg_write(dev, 0x0131, 0x00); // Ext LNA, Int LNA, & Mixer Gain Word + status = ad9361_reg_write(dev, 0x0132, 0x00); // TIA & LPF Word + status = ad9361_reg_write(dev, 0x0133, 0x00); // DC Cal bit & Dig Gain Word + status = ad9361_reg_write(dev, 0x0137, 0x1E); // Write Words + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay 3 ADCCLK/16 cycles + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0137, 0x1A); // Clear Write Bit + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0134, 0x00); // Dummy Write to delay ~1us + status = ad9361_reg_write(dev, 0x0137, 0x00); // Stop Gain Table Clock +//************************************************************ +// Setup Rx Manual Gain Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x00FA, 0xE0); // Gain Control Mode Select + status = ad9361_reg_write(dev, 0x00FB, 0x08); // Table, Digital Gain, Man Gain Ctrl + status = ad9361_reg_write(dev, 0x00FC, 0x23); // Incr Step Size, ADC Overrange Size + status = ad9361_reg_write(dev, 0x00FD, 0x4C); // Max Full/LMT Gain Table Index + status = ad9361_reg_write(dev, 0x00FE, 0x44); // Decr Step Size, Peak Overload Time + status = ad9361_reg_write(dev, 0x0100, 0x6F); // Max Digital Gain + status = ad9361_reg_write(dev, 0x0104, 0x2F); // ADC Small Overload Threshold + status = ad9361_reg_write(dev, 0x0105, 0x3A); // ADC Large Overload Threshold + status = ad9361_reg_write(dev, 0x0107, 0x2B); // Small LMT Overload Threshold + status = ad9361_reg_write(dev, 0x0108, 0x31); // Large LMT Overload Threshold + status = ad9361_reg_write(dev, 0x0109, 0x00); // Rx1 Full/LMT Gain Index + status = ad9361_reg_write(dev, 0x010A, 0x58); // Rx1 LPF Gain Index + status = ad9361_reg_write(dev, 0x010B, 0x00); // Rx1 Digital Gain Index + status = ad9361_reg_write(dev, 0x010C, 0x00); // Rx2 Full/LMT Gain Index + status = ad9361_reg_write(dev, 0x010D, 0x18); // Rx2 LPF Gain Index + status = ad9361_reg_write(dev, 0x010E, 0x00); // Rx2 Digital Gain Index + status = ad9361_reg_write(dev, 0x0114, 0x30); // Low Power Threshold + status = ad9361_reg_write(dev, 0x011A, 0x27); // Initial LMT Gain Limit + status = ad9361_reg_write(dev, 0x0081, 0x00); // Tx Symbol Gain Control +//************************************************************ +// RX Baseband Filter Tuning (Real BW: 20.000000 MHz) 3dB Filter +// Corner @ 28.000000 MHz) +//************************************************************ + status = ad9361_reg_write(dev, 0x01FB, 0x14); // RX Freq Corner (MHz) + status = ad9361_reg_write(dev, 0x01FC, 0x00); // RX Freq Corner (Khz) + status = ad9361_reg_write(dev, 0x01F8, 0x05); // Rx BBF Tune Divider[7:0] + status = ad9361_reg_write(dev, 0x01F9, 0x1E); // RX BBF Tune Divider[8] + + status = ad9361_reg_write(dev, 0x01D5, 0x3F); // Set Rx Mix LO CM + status = ad9361_reg_write(dev, 0x01C0, 0x03); // Set GM common mode + status = ad9361_reg_write(dev, 0x01E2, 0x02); // Enable Rx1 Filter Tuner + status = ad9361_reg_write(dev, 0x01E3, 0x02); // Enable Rx2 Filter Tuner + status = ad9361_reg_write(dev, 0x0016, 0x80); // Start RX Filter Tune + + // Wait for RX filter to tune, Max Cal Time: 2.648 us (Done when 0x016[7]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x80) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x01E2, 0x03); // Disable Rx Filter Tuner (Rx1) + status = ad9361_reg_write(dev, 0x01E3, 0x03); // Disable Rx Filter Tuner (Rx2) +//************************************************************ +// TX Baseband Filter Tuning (Real BW: 20.000000 MHz) 3dB Filter +// Corner @ 32.000000 MHz) +//************************************************************ + status = ad9361_reg_write(dev, 0x00D6, 0x04); // TX BBF Tune Divider[7:0] + status = ad9361_reg_write(dev, 0x00D7, 0x1E); // TX BBF Tune Divider[8] + + status = ad9361_reg_write(dev, 0x00CA, 0x22); // Enable Tx Filter Tuner + status = ad9361_reg_write(dev, 0x0016, 0x40); // Start Tx Filter Tune + + // Wait for TX filter to tune, Max Cal Time: 1.233 us (Done when 0x016[6]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x40) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x00CA, 0x26); // Disable Tx Filter Tuner (Both Channels) +//************************************************************ +// RX TIA Setup: Setup values scale based on RxBBF calibration +// results. See information in Calibration Guide. +//************************************************************ + status = ad9361_reg_write(dev, 0x01DB, 0x20); // Set TIA selcc[2:0] + status = ad9361_reg_write(dev, 0x01DD, 0x00); // Set RX TIA1 C MSB[6:0] + status = ad9361_reg_write(dev, 0x01DF, 0x00); // Set RX TIA2 C MSB[6:0] + status = ad9361_reg_write(dev, 0x01DC, 0x47); // Set RX TIA1 C LSB[5:0] + status = ad9361_reg_write(dev, 0x01DE, 0x47); // Set RX TIA2 C LSB[5:0] + +//************************************************************ +// TX Secondary Filter Calibration Setup: Real Bandwidth +// 20.000000MHz, 3dB Corner @ 100.000000MHz +//************************************************************ + status = ad9361_reg_write(dev, 0x00D2, 0x04); // TX Secondary Filter PDF Cap cal[5:0] + status = ad9361_reg_write(dev, 0x00D1, 0x0C); // TX Secondary Filter PDF Res cal[3:0] + status = ad9361_reg_write(dev, 0x00D0, 0x57); // Pdampbias + +//************************************************************ +// ADC Setup: Tune ADC Performance based on RX analog filter tune +// corner. Real Bandwidth: 18.155158 MHz, ADC Clock Frequency: +// 288.000000 MHz. The values in registers 0x200 - 0x227 need to be +// calculated using the equations in the Calibration Guide. +//************************************************************ + + status = ad9361_reg_write(dev, 0x0200, 0x00); + status = ad9361_reg_write(dev, 0x0201, 0x00); + status = ad9361_reg_write(dev, 0x0202, 0x00); + status = ad9361_reg_write(dev, 0x0203, 0x24); + status = ad9361_reg_write(dev, 0x0204, 0x24); + status = ad9361_reg_write(dev, 0x0205, 0x00); + status = ad9361_reg_write(dev, 0x0206, 0x00); + status = ad9361_reg_write(dev, 0x0207, 0x67); + status = ad9361_reg_write(dev, 0x0208, 0x55); + status = ad9361_reg_write(dev, 0x0209, 0x31); + status = ad9361_reg_write(dev, 0x020A, 0x3E); + status = ad9361_reg_write(dev, 0x020B, 0x35); + status = ad9361_reg_write(dev, 0x020C, 0x41); + status = ad9361_reg_write(dev, 0x020D, 0x34); + status = ad9361_reg_write(dev, 0x020E, 0x00); + status = ad9361_reg_write(dev, 0x020F, 0x6A); + status = ad9361_reg_write(dev, 0x0210, 0x6A); + status = ad9361_reg_write(dev, 0x0211, 0x6A); + status = ad9361_reg_write(dev, 0x0212, 0x3C); + status = ad9361_reg_write(dev, 0x0213, 0x3C); + status = ad9361_reg_write(dev, 0x0214, 0x3C); + status = ad9361_reg_write(dev, 0x0215, 0x3F); + status = ad9361_reg_write(dev, 0x0216, 0x3F); + status = ad9361_reg_write(dev, 0x0217, 0x3F); + status = ad9361_reg_write(dev, 0x0218, 0x2E); + status = ad9361_reg_write(dev, 0x0219, 0x9C); + status = ad9361_reg_write(dev, 0x021A, 0x1F); + status = ad9361_reg_write(dev, 0x021B, 0x15); + status = ad9361_reg_write(dev, 0x021C, 0x9C); + status = ad9361_reg_write(dev, 0x021D, 0x1F); + status = ad9361_reg_write(dev, 0x021E, 0x15); + status = ad9361_reg_write(dev, 0x021F, 0x9C); + status = ad9361_reg_write(dev, 0x0220, 0x1F); + status = ad9361_reg_write(dev, 0x0221, 0x2A); + status = ad9361_reg_write(dev, 0x0222, 0x2A); + status = ad9361_reg_write(dev, 0x0223, 0x40); + status = ad9361_reg_write(dev, 0x0224, 0x40); + status = ad9361_reg_write(dev, 0x0225, 0x2C); + status = ad9361_reg_write(dev, 0x0226, 0x00); + status = ad9361_reg_write(dev, 0x0227, 0x00); +//************************************************************ +// Setup and Run BB DC and RF DC Offset Calibrations +//************************************************************ + status = ad9361_reg_write(dev, 0x0193, 0x3F); + status = ad9361_reg_write(dev, 0x0190, 0x0F); // Set BBDC tracking shift M value, only applies when BB DC tracking enabled + status = ad9361_reg_write(dev, 0x0194, 0x01); // BBDC Cal setting + status = ad9361_reg_write(dev, 0x0016, 0x01); // Start BBDC offset cal + + // BBDC Max Cal Time: 8416.667 us. Cal done when 0x016[0]==0 + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x0185, 0x20); // Set RF DC offset Wait Count + status = ad9361_reg_write(dev, 0x0186, 0x32); // Set RF DC Offset Count[7:0] + status = ad9361_reg_write(dev, 0x0187, 0x24); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x018B, 0x83); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0188, 0x05); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0189, 0x30); // Settings for RF DC cal + status = ad9361_reg_write(dev, 0x0016, 0x02); // Start RFDC offset cal + + // RFDC Max Cal Time: 114511.250 us + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x01) != 0x00 && time_out_cnt <= TIMEOUT_TH); + +//************************************************************ +// Tx Quadrature Calibration Settings +//************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x5F); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0x80); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + // Wait for cal to complete (Done when 0x016[4]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH); + + status = ad9361_reg_write(dev, 0x016A, 0x75); // Set Kexp Phase + status = ad9361_reg_write(dev, 0x016B, 0x95); // Set Kexp Amplitude & Prevent Positive Gain Bit + status = ad9361_reg_write(dev, 0x0169, 0xCF); // Enable Rx Quadrature Calibration Tracking + status = ad9361_reg_write(dev, 0x018B, 0xAD); // Enable BB and RF DC Tracking Calibrations + status = ad9361_reg_write(dev, 0x0012, 0x02); // Cals done, Set PPORT Config + status = ad9361_reg_write(dev, 0x0013, 0x01); // Set ENSM FDD/TDD bit + status = ad9361_reg_write(dev, 0x0015, 0x0C); // Set Dual Synth Mode, FDD External Control bits properly + +//************************************************************ +// Set Tx Attenuation: Tx1: 0.00 dB, Tx2: 0.00 dB +//************************************************************ + status = ad9361_reg_write(dev, 0x0073, 0x00); + status = ad9361_reg_write(dev, 0x0074, 0x00); + status = ad9361_reg_write(dev, 0x0075, 0x00); + status = ad9361_reg_write(dev, 0x0076, 0x00); +//************************************************************ +// Setup RSSI and Power Measurement Duration Registers +//************************************************************ + status = ad9361_reg_write(dev, 0x0150, 0x0E); // RSSI Measurement Duration 0, 1 + status = ad9361_reg_write(dev, 0x0151, 0x00); // RSSI Measurement Duration 2, 3 + status = ad9361_reg_write(dev, 0x0152, 0xFF); // RSSI Weighted Multiplier 0 + status = ad9361_reg_write(dev, 0x0153, 0x00); // RSSI Weighted Multiplier 1 + status = ad9361_reg_write(dev, 0x0154, 0x00); // RSSI Weighted Multiplier 2 + status = ad9361_reg_write(dev, 0x0155, 0x00); // RSSI Weighted Multiplier 3 + status = ad9361_reg_write(dev, 0x0156, 0x00); // RSSI Delay + status = ad9361_reg_write(dev, 0x0157, 0x00); // RSSI Wait + status = ad9361_reg_write(dev, 0x0158, 0x0D); // RSSI Mode Select + status = ad9361_reg_write(dev, 0x015C, 0x67); // Power Measurement Duration + +//************************************************************ +// Enable External LO & External VCO Buffer +//************************************************************ + status |= ad9361_reg_write(dev, 0x0005, 0x07); + status |= ad9361_reg_write(dev, 0x0057, 0x1C); + + return status; +} diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/ad9516_profile.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/ad9516_profile.c new file mode 100644 index 00000000..65764aa3 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/ad9516_profile.c @@ -0,0 +1,89 @@ +#include "dev_profile.h" +#include "../app_config.h" +#include "../adi_noos/drivers/frequency/ad9516/ad9516.h" + + +static spi_init_param ad9516_spi_init = { + .device_id = SPI_DEVICE_ID, + .max_speed_hz = SPI_ENGINE_MAX_SPEED, + .mode = SPI_MODE_4, + .chip_select = SPI_CS_AD9516, + .platform_ops = SPI_OPS, + .extra = SPI_PARAM +}; + +struct ad9516_init_param ad9516_default_init_param = { + /* SPI */ + .spi_init = &ad9516_spi_init +}; + +const uint32_t ad9516_default_config_len = 66; +const struct ad9516_config ad9516_default_config[] = { + {0x0000,0x18}, // 16-bit instruction, MSB first, 3-wire SPI + {0x0004,0x00}, // reads back buffer registers + {0x0010,0x7C}, + {0x0011,0x04}, // R divider LSBs, R = 4 + {0x0012,0x00}, // R divider MSBs, R = 4 + {0x0013,0x08}, // A counter, A = 8 + {0x0014,0x09}, // B counter LSBs, B = 9 + {0x0015,0x00}, // B counter MSBs, B = 9 + {0x0016,0x04}, // Divide-by-8 (8/9 mode) + {0x0017,0x10}, // STATUS pin output: Prescaler output + {0x0018,0x06}, + {0x0019,0x80}, // R, A, B counters synchronous reset on SYNCB + {0x001A,0x00}, // LD pin output: Digital lock detect (high = lock, low = unlock) + {0x001B,0xA1}, // enables VCO, REF1 frequency monitor; REFMON pin output: REF1 clock + {0x001C,0x07}, // selects REF1; REF1, REF2 power on; differential reference mode + {0x001D,0x00}, + {0x001E,0x00}, + {0x00A0,0x01}, + {0x00A1,0x00}, + {0x00A2,0x00}, + {0x00A3,0x01}, + {0x00A4,0x00}, + {0x00A5,0x00}, + {0x00A6,0x01}, + {0x00A7,0x00}, + {0x00A8,0x00}, + {0x00A9,0x01}, + {0x00AA,0x00}, + {0x00AB,0x00}, + {0x00F0,0x08}, + {0x00F1,0x08}, + {0x00F2,0x08}, + {0x00F3,0x08}, + {0x00F4,0x08}, + {0x00F5,0x08}, + {0x0140,0x59}, + {0x0141,0x5A}, + {0x0142,0x5A}, + {0x0143,0x42}, + {0x0190,0x33}, + {0x0191,0x40}, + {0x0192,0x00}, + {0x0193,0x33}, + {0x0194,0x40}, + {0x0195,0x00}, + {0x0196,0x44}, + {0x0197,0x40}, + {0x0198,0x00}, + {0x0199,0x99}, // divider 3.1, Low Cycles = 10, High Cycles = 10 + {0x019A,0x00}, + {0x019B,0x00}, // divider 3.1, Low Cycles = 1, High Cycles = 1 + {0x019C,0x00}, + {0x019D,0x00}, +// {0x019E,0xFF}, + {0x019E,0x11}, + {0x019F,0x00}, + {0x01A0,0x11}, + {0x01A1,0x20}, + {0x01A2,0x00}, + {0x01A3,0x00}, + {0x01E0,0x00}, + {0x01E1,0x02}, + {0x0230,0x00}, + {0x0231,0x00}, + {0x0232,0x01}, // Update all registers + {0x0018,0x07}, // initiate the VCO calibration + {0x0232,0x01} // Update all registers +}; diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/dev_profile.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/dev_profile.h new file mode 100644 index 00000000..11393c26 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/dev_profile/dev_profile.h @@ -0,0 +1,43 @@ +#ifndef DEV_PROFILE_H_ +#define DEV_PROFILE_H_ + +#include +#include "../app_config.h" +#include "../parameters.h" +#include "../adi_noos/include/spi.h" +#include "../adi_noos/include/gpio.h" +#include "../adi_noos/include/delay.h" +#include "../adi_noos/include/irq.h" +#include "../adi_noos/include/error.h" +#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h" +#include "../adi_noos/drivers/frequency/ad9516/ad9516.h" + +// Platform includes +#include "../adi_noos/drivers/platform/spi_extra.h" +#include "../adi_noos/drivers/platform/gpio_extra.h" +#include "../adi_noos/drivers/platform/irq_extra.h" + +// AXI-Cores includes +#include "../adi_noos/drivers/axi_core/spi_engine/spi_engine.h" + +// Declare in mian.c +extern struct spi_engine_init_param spi_engine_param; +extern struct xil_gpio_init_param xil_gpio_param; + +#define GPIO_PARAM &xil_gpio_param +#define SPI_PARAM &spi_engine_param +#define GPIO_OPS &xil_gpio_ops +#define SPI_OPS &spi_eng_platform_ops + +extern struct ad9516_init_param ad9516_default_init_param; +extern const struct ad9516_config ad9516_default_config[]; +extern const uint32_t ad9516_default_config_len; + +extern struct ad9361_reg_init_param ad9361_1_reg_default_init_param; +extern struct ad9361_reg_init_param ad9361_2_reg_default_init_param; + +uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev); +uint32_t ad9361_1_reg_config(struct ad9361_reg_dev *dev); +uint32_t ad9361_2_reg_config(struct ad9361_reg_dev *dev); + +#endif /* SRC_DEV_PROFILE_H_ */ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/lscript.ld b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/lscript.ld new file mode 100644 index 00000000..bf23f9ef --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/lscript.ld @@ -0,0 +1,212 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: 2019.1.3 */ +/* */ +/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : MicroBlaze Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x4000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8000; + +/* Define Memories in the system */ + +MEMORY +{ + microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem : ORIGIN = 0x50, LENGTH = 0x3FFB0 +} + +/* Specify the default entry point to the program */ + +ENTRY(_start) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.vectors.reset 0x0 : { + KEEP (*(.vectors.reset)) +} + +.vectors.sw_exception 0x8 : { + KEEP (*(.vectors.sw_exception)) +} + +.vectors.interrupt 0x10 : { + KEEP (*(.vectors.interrupt)) +} + +.vectors.hw_exception 0x20 : { + KEEP (*(.vectors.hw_exception)) +} + +.text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.init : { + KEEP (*(.init)) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.fini : { + KEEP (*(.fini)) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + PROVIDE(__DTOR_END__ = .); + PROVIDE(___DTORS_END___ = .); +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.sdata2 : { + . = ALIGN(8); + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + . = ALIGN(8); + __sdata2_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.data : { + . = ALIGN(4); + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __data_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.got : { + *(.got) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.got1 : { + *(.got1) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.got2 : { + *(.got2) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.eh_frame : { + *(.eh_frame) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.jcr : { + *(.jcr) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.gcc_except_table : { + *(.gcc_except_table) +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.sdata : { + . = ALIGN(8); + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.sbss (NOLOAD) : { + . = ALIGN(4); + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + . = ALIGN(8); + __sbss_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.bss (NOLOAD) : { + . = ALIGN(4); + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(8); + _heap = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +.stack (NOLOAD) : { + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(8); + _stack = .; + __stack = _stack; +} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem + +_end = .; +} + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/main.c b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/main.c new file mode 100644 index 00000000..4ddde31c --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/main.c @@ -0,0 +1,420 @@ +/***************************************************************************//** + * @file ad9361/src/main.c + * @brief Implementation of Main Function. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +// Platform includes +#include +#include "xparameters.h" +#include "xil_assert.h" +#include "xgpio.h" +// ADI Drivers +#include "app_config.h" +#include "dev_profile/dev_profile.h" +#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h" +// AXI-Cores includes +#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h" +#include "adi_noos/drivers/platform/gpio_extra.h" + +/******************************************************************************/ +/************************ Variables Definitions *******************************/ +/******************************************************************************/ + +struct spi_engine_init_param spi_engine_param = { + .ref_clk_hz = SPI_ENGINE_REF_CLK, + .type = SPI_ENGINE, + .spi_engine_baseaddr = SPI_ENGINE_BASEADDR, + .cs_delay = SPI_ENGINE_CS_DELAY, + .data_width = SPI_ENGINE_DATA_WIDTH +}; + +struct xil_gpio_init_param xil_gpio_param = { + .type = GPIO_PS, + .device_id = GPIO_DEVICE_ID +}; + +struct ad9516_dev *ad9516_inst; +struct ad9361_reg_dev *ad9361_1_reg_inst; +struct ad9361_reg_dev *ad9361_2_reg_inst; +struct ad9361_rf_phy *ad9361_phy; + +XGpio Gpio; + +int XGpio_WritePin(XGpio *InstPtr, unsigned Channel, u32 Pin, u8 Value); +int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq); + +/***************************************************************************//** + * @brief main +*******************************************************************************/ +int main(void) +{ + int32_t Status; + Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + XGpio_SetDataDirection(&Gpio, GPIO_BANK_OUT, 0x00000000); // Bank 1 output + XGpio_SetDataDirection(&Gpio, GPIO_BANK_IN, 0xFFFFFFFF); // Bank 0 input + + XGpio_DiscreteWrite(&Gpio, GPIO_BANK_OUT, 0x00000000); + + /**********************************************************/ + /****************** AD9516 Configuration ******************/ + /**********************************************************/ + Status = ad9516_init(&ad9516_inst, &ad9516_default_init_param); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_POWEDOWN_B, 1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_RESET_B, 0); + mdelay(200); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_RESET_B, 1); + for(int i = 0; i < ad9516_default_config_len; i++){ + Status = ad9516_write(ad9516_inst, ad9516_default_config[i].addr, ad9516_default_config[i].value); + if (ad9516_default_config[i].addr == 0x0000){ + mdelay(500); + } + } + + uint8_t rd_back; + Status = ad9516_read(ad9516_inst, 0x0003, &rd_back); + do + { + Status = ad9516_read(ad9516_inst, 0x001F, &rd_back); + } + while((rd_back & 0x01) != 0x01); + + /**********************************************************/ + /***************** AD9361-1 Configuration *****************/ + /**********************************************************/ + ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_RESET_B, 0); + mdelay(200); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_RESET_B, 1); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_ENABLE, 0); + ad9361_reg_config(ad9361_1_reg_inst); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_ENABLE, 1); + + /**********************************************************/ + /***************** AD9361-2 Configuration *****************/ + /**********************************************************/ + ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_RESET_B, 0); + mdelay(200); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_RESET_B, 1); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_ENABLE, 0); + ad9361_reg_config(ad9361_2_reg_inst); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_ENABLE, 1); + + /**********************************************************/ + /******* AD9361 Baseband Multichip Synchronization ********/ + /**********************************************************/ + // sync clock output + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 0); + mdelay(500); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 1); + + // SYNC BBPLL and DIGITAL SAMPLING CLOCKS + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D); // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D); + ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80); // MCS refclk Scale Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0); + mdelay(20); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin + mdelay(500); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0); + mdelay(2000); + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B); // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin + mdelay(500); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0); + ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08); // clear MCS bits + ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08); + + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 0); + mdelay(20); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 1); + mdelay(20); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 0); + + /**********************************************************/ + /********* AD9361 Multichip Rx Phase Calibration **********/ + /**********************************************************/ + // switch to lower frequency + Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_125); + mdelay(20); + + // switch rx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30); + Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30); + + // enable dual ad9361 tx channels + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4); // Setup Tx Digital Filters/ Channels + +#ifdef DL814_BOARD_V3 + // switch ad9361 tx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + mdelay(20); +#endif + + // begin to calibrate the 1st ad9361 + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 0); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 1); + mdelay(1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 0); + + // read calibration status + int32_t time_out_cnt = 0; + do{ + mdelay(1);// Wait 1ms + time_out_cnt++; + }while((((XGpio_DiscreteRead(&Gpio, GPIO_BANK_IN) >> AD9361_1_CAL_DONE) & 0x00000001) == 0) && time_out_cnt <= TIMEOUT_TH); + + if (time_out_cnt == TIMEOUT_TH){ + return FAILURE; + } + +#ifdef DL814_BOARD_V2 + // switch ad9361 tx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70); // Select Rx input pin(A,B,C)/ Tx out pin (A,B) + mdelay(20); +#endif + + // begin to calibrate the 2nd ad9361 + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_CAL_START, 1); + mdelay(1); + XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_CAL_START, 0); + + // read calibration status + time_out_cnt = 0; + do{ + mdelay(1);// Wait 1ms + time_out_cnt++; + }while((((XGpio_DiscreteRead(&Gpio, GPIO_BANK_IN) >> AD9361_2_CAL_DONE) & 0x00000001) == 0) && time_out_cnt <= TIMEOUT_TH); + + if (time_out_cnt == TIMEOUT_TH){ + return FAILURE; + } + + // enable single ad9361 tx channels + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels + + // switch ad9361 tx & rx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03); + Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03); + + // switch to higher frequency + Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125); + + print("Done.\n"); + + return 0; +} + +int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq){ + int32_t status = 0; + uint8_t value = 0; + int32_t time_out_cnt = 0; + + switch(freq){ + case TX_FREQ_125: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x94); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Tx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA0); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + case TX_FREQ_126: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Tx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x06); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0xD7); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x23); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA1); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x57); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x22); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x00); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + case TX_FREQ_4125: { + //************************************************************ + // Setup Tx Frequency-Dependent Syntheisizer Registers + //************************************************************ + status = ad9361_reg_write(dev, 0x027A, 0x4A); // Set VCO Output level[3:0] + status = ad9361_reg_write(dev, 0x0279, 0xC1); // Set Init ALC Value[3:0] and VCO Varactor[3:0] + status = ad9361_reg_write(dev, 0x0282, 0x0E); // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] + status = ad9361_reg_write(dev, 0x0278, 0x78); // Set VCO Cal Offset[3:0] + status = ad9361_reg_write(dev, 0x0285, 0x00); // Set VCO Cal Ref Tcf[2:0] + status = ad9361_reg_write(dev, 0x0291, 0x0B); // Set VCO Varactor Reference[3:0] + status = ad9361_reg_write(dev, 0x0290, 0x70); // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] + status = ad9361_reg_write(dev, 0x027B, 0x93); // Set Synth Loop Filter charge pump current (Icp) + status = ad9361_reg_write(dev, 0x027E, 0xF4); // Set Synth Loop Filter C2 and C1 + status = ad9361_reg_write(dev, 0x027F, 0xDF); // Set Synth Loop Filter R1 and C3 + status = ad9361_reg_write(dev, 0x0280, 0x0A); // Set Synth Loop Filter R3 + + //************************************************************ + // Write Rx Frequency Words + //************************************************************ + status = ad9361_reg_write(dev, 0x0273, 0x00); // Write Tx Synth Fractional Freq Word[7:0] + status = ad9361_reg_write(dev, 0x0274, 0x00); // Write Tx Synth Fractional Freq Word[15:8] + status = ad9361_reg_write(dev, 0x0275, 0x00); // Write Tx Synth Fractional Freq Word[22:16] + status = ad9361_reg_write(dev, 0x0272, 0x00); // Write Tx Synth Integer Freq Word[10:8] + status = ad9361_reg_write(dev, 0x0271, 0xA5); // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) + status = ad9361_reg_write(dev, 0x0005, 0x07); // Set LO divider setting + + //************************************************************ + // Tx Quadrature Calibration Settings + //************************************************************ + status = ad9361_reg_write(dev, 0x00A0, 0x75); // Set TxQuadcal NCO frequency + status = ad9361_reg_write(dev, 0x00A3, 0xC0); // Set TxQuadcal NCO frequency (Only update bits [7:6]) + status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable + status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count + status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp + status = ad9361_reg_write(dev, 0x00A5, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00A6, 0x01); // Set Tx Quad Cal Magnitude Threshhold + status = ad9361_reg_write(dev, 0x00AA, 0x28); // Set Tx Quad Cal Gain Table index + status = ad9361_reg_write(dev, 0x00A4, 0xF0); // Set Tx Quad Cal Settle Count + status = ad9361_reg_write(dev, 0x00AE, 0x04); // Set Tx Quad Cal LPF Gain index incase Split table mode used + + status = ad9361_reg_write(dev, 0x0169, 0xC0); // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration + status = ad9361_reg_write(dev, 0x0016, 0x10); // Start Tx Quad cal + + break; + } + + // Wait for cal to complete (Done when 0x016[4]==0) + time_out_cnt = 0; + do{ + status |= ad9361_reg_read(dev, 0x0016, &value); + mdelay(1);// Wait 1ms + time_out_cnt++; + } while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH); + } + + return status; +} +int XGpio_WritePin(XGpio *InstPtr, unsigned Channel, u32 Pin, u8 Value){ + Xil_AssertNonvoid(Pin <= 31 && Pin >=0 ); + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(InstPtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((Channel == 1) || + ((Channel == 2) && (InstPtr->IsDual == TRUE))); + u32 CurrValue = XGpio_DiscreteRead(InstPtr, Channel); + CurrValue = (Value == 0)? (CurrValue & (~(0x00000001 << Pin))) : (CurrValue | (0x00000001 << Pin)); + XGpio_DiscreteWrite(InstPtr, Channel, CurrValue); + return XST_SUCCESS; +} + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/parameters.h b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/parameters.h new file mode 100644 index 00000000..de68bf0d --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M/src/parameters.h @@ -0,0 +1,136 @@ +/***************************************************************************//** + * @file ad9361/src/parameters.h + * @brief Parameters Definitions. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2013(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ +#ifndef __PARAMETERS_H__ +#define __PARAMETERS_H__ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include "app_config.h" + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ +#ifdef XILINX_PLATFORM + +#define FCLK_CLK0_HZ 25000000 + +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID + +#define GPIO_DEVICE_ID XPAR_AXI_GPIO_DEVICE_ID +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +#define AD9516_POWEDOWN_B 0 +#define AD9516_RESET_B 1 +#define AD9516_SYNC_B 2 +#define AD9361_1_TXNRX 3 +#define AD9361_1_ENABLE 4 +#define AD9361_1_EN_AGC 5 +#define AD9361_1_RESET_B 6 +#define AD9361_1_CTRL_IN_0 7 +#define AD9361_1_CTRL_IN_1 8 +#define AD9361_1_CTRL_IN_2 9 +#define AD9361_1_CTRL_IN_3 10 +#define AD9361_2_TXNRX 11 +#define AD9361_2_ENABLE 12 +#define AD9361_2_EN_AGC 13 +#define AD9361_2_RESET_B 14 +#define AD9361_2_CTRL_IN_0 15 +#define AD9361_2_CTRL_IN_1 16 +#define AD9361_2_CTRL_IN_2 17 +#define AD9361_2_CTRL_IN_3 18 +#define AD9361_SYNC 19 +#define AD9361_RX_FIFO_RST 20 +#define AD9361_1_CAL_START 21 +#define AD9361_2_CAL_START 22 +#define AD9361_RECAL 23 + +#define AD9361_1_CTRL_OUT_0 0 +#define AD9361_1_CTRL_OUT_1 1 +#define AD9361_1_CTRL_OUT_2 2 +#define AD9361_1_CTRL_OUT_3 3 +#define AD9361_1_CTRL_OUT_4 4 +#define AD9361_1_CTRL_OUT_5 5 +#define AD9361_1_CTRL_OUT_6 6 +#define AD9361_1_CTRL_OUT_7 7 +#define AD9361_2_CTRL_OUT_0 8 +#define AD9361_2_CTRL_OUT_1 9 +#define AD9361_2_CTRL_OUT_2 10 +#define AD9361_2_CTRL_OUT_3 11 +#define AD9361_2_CTRL_OUT_4 12 +#define AD9361_2_CTRL_OUT_5 13 +#define AD9361_2_CTRL_OUT_6 14 +#define AD9361_2_CTRL_OUT_7 15 +#define AD9516_REFMON 16 +#define AD9516_LOCKDETECT 17 +#define AD9516_STARUS 18 +#define AD9361_1_CAL_DONE 19 +#define AD9361_2_CAL_DONE 20 +#define AD9361_CAL_RESULT 21 + +#define GPIO_BANK_OUT 1 +#define GPIO_BANK_IN 2 + +#define SPI_DEVICE_ID 0 +#define SPI_ENGINE_REF_CLK FCLK_CLK0_HZ +#define SPI_ENGINE_MAX_SPEED 5000000 +#define SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR +#define SPI_ENGINE_DATA_WIDTH 8 +#define SPI_ENGINE_CS_DELAY 3 +#define SPI_CS_AD9516 0x00 +#define SPI_CS_AD9361_1 0x01 +#define SPI_CS_AD9361_2 0x02 + +#define DL814_BOARD_V3 +#define TIMEOUT_TH 2000 + +typedef enum +{ + TX_FREQ_125, + TX_FREQ_126, + TX_FREQ_4125 +} ad9361TxFreq; + +#endif + +#endif // __PARAMETERS_H__ diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.cproject b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.cproject new file mode 100644 index 00000000..ddd07f14 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.cproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.project b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.project new file mode 100644 index 00000000..ada07ff9 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.project @@ -0,0 +1,75 @@ + + + dl814_k7_48M_bsp + Created by SDK v2019.1 + + + + + org.eclipse.cdt.make.core.makeBuilder + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.sdkproject b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.sdkproject new file mode 100644 index 00000000..59355a37 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/.sdkproject @@ -0,0 +1,4 @@ +THIRPARTY=false +HW_PROJECT_REFERENCE=system_top_hw_platform_0 +PROCESSOR=microblaze_ps +MSS_FILE=system.mss diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/Makefile b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/Makefile new file mode 100644 index 00000000..1beff569 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/Makefile @@ -0,0 +1,35 @@ +# Makefile generated by Xilinx. + +PROCESSOR = microblaze_ps +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: libs + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +libs: $(addsuffix /make.libs,$(SUBDIRS)) + +clean: $(addsuffix /make.clean,$(SUBDIRS)) + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v11.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ARCHIVER=mb-ar" "COMPILER_FLAGS= -O2 -c -mcpu=v11.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-ffunction-sections -fdata-sections -Wall -Wextra" + +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean +clean: + rm -f ${PROCESSOR}/lib/libxil.a diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/system.mss b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/system.mss new file mode 100644 index 00000000..a220fb06 --- /dev/null +++ b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/dl814_k7_48M_bsp/system.mss @@ -0,0 +1,44 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 7.0 + PARAMETER PROC_INSTANCE = microblaze_ps +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 2.9 + PARAMETER HW_INSTANCE = microblaze_ps + PARAMETER compiler_flags = -mlittle-endian -mxl-soft-mul -mcpu=v11.0 +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 4.4 + PARAMETER HW_INSTANCE = axi_gpio +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 4.3 + PARAMETER HW_INSTANCE = microblaze_ps_local_memory_dlmb_bram_if_cntlr +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 4.3 + PARAMETER HW_INSTANCE = microblaze_ps_local_memory_ilmb_bram_if_cntlr +END + + diff --git a/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/system_top.hdf b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/system_top.hdf new file mode 100644 index 00000000..2c935684 Binary files /dev/null and b/projects/datalink_814/dl814_k7_beam/project/dl814_k7_beam/dl814_k7_beam.sdk/system_top.hdf differ diff --git a/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/rx_pre_process.v b/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/rx_pre_process.v index c6134d93..da983a22 100644 --- a/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/rx_pre_process.v +++ b/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/rx_pre_process.v @@ -51,8 +51,9 @@ module rx_pre_process parameter SNAPSHOT_NUM = 256, parameter PS_PL_WIDTH = 32 , parameter WEIGHT_TRUNC_WIDTH = 16 , - parameter CMPLX_DIM = 2 -) + parameter CMPLX_DIM = 2 , + parameter OUTPUT_DATA_WIDTH = ADC_DATA_WIDTH +) ( // clock & reset input sys_clk , // sync to adc data @@ -86,8 +87,8 @@ module rx_pre_process output accor_stream_data , // sync to [clk_96m] input weight_stream_data , // sync to [clk_96m] output rx_data_valid , // sync to [sys_clk] - output [ADC_DATA_WIDTH-1:0] rx_data_i , // sync to [sys_clk] - output [ADC_DATA_WIDTH-1:0] rx_data_q // sync to [sys_clk] + output [OUTPUT_DATA_WIDTH-1:0] rx_data_i, // sync to [sys_clk] + output [OUTPUT_DATA_WIDTH-1:0] rx_data_q // sync to [sys_clk] ); localparam ACORR_WIDTH = 2*ADC_DATA_WIDTH; @@ -421,8 +422,8 @@ assign filter_adc_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q // output data wire filter_dout_valid; -wire [ADC_DATA_WIDTH-1 : 0] filter_dout_real; -wire [ADC_DATA_WIDTH-1 : 0] filter_dout_imag; +wire [OUTPUT_DATA_WIDTH-1 : 0] filter_dout_real; +wire [OUTPUT_DATA_WIDTH-1 : 0] filter_dout_imag; assign rx_data_valid = filter_dout_valid; assign rx_data_i = filter_dout_real; @@ -432,7 +433,7 @@ spatial_filter #( .CHANNEL_NUM (CHANNEL_NUM ), .WEIGHT_WIDTH (WEIGHT_TRUNC_WIDTH ), .ADC_WIDTH (ADC_DATA_WIDTH ), - .FILTER_O_WIDTH (ADC_DATA_WIDTH ) + .FILTER_O_WIDTH (OUTPUT_DATA_WIDTH ) ) u_spatial_filter ( // clock & reset @@ -445,7 +446,7 @@ spatial_filter #( .din_weight_imag (filter_weight_imag ), // input adc data - .hop_start_flag (hop_start_flag_cdc ), + .hop_start_flag (1'b0 ), .din_adc_valid (filter_adc_valid ), .din_adc_real (filter_adc_real ), .din_adc_imag (filter_adc_imag ), diff --git a/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/spatial_filter.v b/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/spatial_filter.v index 27db92de..8c4f6a64 100644 --- a/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/spatial_filter.v +++ b/projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/spatial_filter.v @@ -176,9 +176,9 @@ for(i = 0; i < CHANNEL_NUM; i = i + 1) begin: spatial_filter_cmpy cmpy_16x12 u_cmpy_16x12 ( .aclk (clk ), // input wire aclk - .s_axis_a_tvalid (last_hop_valid ), // input wire s_axis_a_tvalid + .s_axis_a_tvalid (din_adc_valid ), // input wire s_axis_a_tvalid .s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata - .s_axis_b_tvalid (last_hop_valid ), // input wire s_axis_b_tvalid + .s_axis_b_tvalid (din_adc_valid ), // input wire s_axis_b_tvalid .s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata .m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid .m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata diff --git a/projects/datalink_814/dl814_k7_beam/rtl/system_top.v b/projects/datalink_814/dl814_k7_beam/rtl/system_top.v index 82c589ec..4d929824 100644 --- a/projects/datalink_814/dl814_k7_beam/rtl/system_top.v +++ b/projects/datalink_814/dl814_k7_beam/rtl/system_top.v @@ -518,26 +518,26 @@ assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk; // assign ad9361_2_tx_frame = ad9361_1_tx_frame ; // assign ad9361_2_tx_data = ad9361_1_tx_data ; -tx_pre_process u_tx_pre_process -( - // clock & reset - .clk (sys_clk ), - .rst (sys_rst ), - // input data - .tx_data_ch1_i (tx_data_i ), - .tx_data_ch1_q (tx_data_q ), - .tx_data_ch2_i (tx_data_i ), - .tx_data_ch2_q (tx_data_q ), - // ad9361 calibration interface - .ad9361_tx_switch (ad9361_tx_switch ), - // - .bb_rshift (bb_rshift ), - // output data - .tx_ch1_i (tx_ch1_i ), - .tx_ch1_q (tx_ch1_q ), - .tx_ch2_i (tx_ch2_i ), - .tx_ch2_q (tx_ch2_q ) -); +// tx_pre_process u_tx_pre_process +// ( +// // clock & reset +// .clk (sys_clk ), +// .rst (sys_rst ), +// // input data +// .tx_data_ch1_i (tx_data_i ), +// .tx_data_ch1_q (tx_data_q ), +// .tx_data_ch2_i (tx_data_i ), +// .tx_data_ch2_q (tx_data_q ), +// // ad9361 calibration interface +// .ad9361_tx_switch (ad9361_tx_switch ), +// // +// .bb_rshift (bb_rshift ), +// // output data +// .tx_ch1_i (tx_ch1_i ), +// .tx_ch1_q (tx_ch1_q ), +// .tx_ch2_i (tx_ch2_i ), +// .tx_ch2_q (tx_ch2_q ) +// ); // <---------------------------------------------------------------------------> // <--------------------- insert transmitter logic below ----------------------> @@ -571,7 +571,7 @@ wire [11:0] rx_ch3_i, rx_ch3_q; wire [11:0] rx_ch4_i, rx_ch4_q; wire rx_data_valid; -wire [11:0] rx_data_i, rx_data_q; +wire [29:0] rx_data_i, rx_data_q; wire hop_start_flag ; wire accor_stream_valid ; @@ -619,7 +619,9 @@ ad9361_rx_map_cmos_dual u_ad9361_2_rx_map .rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q ); -rx_pre_process u_rx_pre_process +rx_pre_process #( + .OUTPUT_DATA_WIDTH (30 ) +) u_rx_pre_process ( // clock & reset .sys_clk (sys_clk ), // sync to adc data @@ -645,7 +647,7 @@ rx_pre_process u_rx_pre_process .ad9361_cal_valid (ad9361_cal_valid ), .ad9361_recal (ad9361_recal ), // nulling algotithm interface - .hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x] + .hop_start_flag (1'b0 ), // sync to [sys_clk_4x] .accor_stream_valid (accor_stream_valid ), // sync to [clk_96m] .accor_stream_data (accor_stream_data ), // sync to [clk_96m] .weight_stream_data (weight_stream_data ), // sync to [clk_96m] @@ -793,56 +795,77 @@ vio_ant_rd u_vio_ant_rd ( .probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5 ); -ila_tx_rx u_ila_tx_rx +ila_rx u_ila_rx ( .clk (sys_clk ), // input wire clk - .probe0 (tx_ch1_i ), // input wire [11:0] probe0 - .probe1 (tx_ch1_q ), // input wire [11:0] probe1 - .probe2 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe2 - .probe3 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe3 - .probe4 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe4 - .probe5 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe5 - .probe6 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe6 - .probe7 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe7 - .probe8 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe8 - .probe9 (u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe9 + .probe0 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe0 + .probe1 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe1 + .probe2 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe2 + .probe3 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe3 + .probe4 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe4 + .probe5 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe5 + .probe6 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe6 + .probe7 (u_rx_pre_process.rx_cal_ch4_q ), // input wire [11:0] probe7 + .probe8 (rx_data_i ), // input wire [29:0] probe8 + .probe9 (rx_data_q ) // input wire [29:0] probe9 ); -ila_cal u_ila_cal +ila_tx u_ila_tx ( - .clk (sys_clk ), // input wire clk - .probe0 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0 - .probe1 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1 - .probe2 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2 - .probe3 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3 - .probe4 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4 - .probe5 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5 - .probe6 (u_rx_pre_process.u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6 - .probe7 (rx_ch2_i ), // input wire [11:0] probe7 - .probe8 (rx_ch2_q ), // input wire [11:0] probe8 - .probe9 (rx_ch4_i ), // input wire [11:0] probe9 - .probe10(rx_ch4_q ), // input wire [11:0] probe10 - .probe11(u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe11 - .probe12(u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe12 - .probe13(u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe13 - .probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14 + .clk (sys_clk ), // input wire clk + .probe0 (tx_data_i ), // input wire [11:0] probe0 + .probe1 (tx_data_q ) // input wire [11:0] probe1 ); -vio_cal u_vio_cal -( - .clk (sys_clk ), // input wire clk - .probe_in0 (u_rx_pre_process.u_ad9361_phase_cal.relative_delay ), // input wire [4 : 0] probe_in0 - .probe_in1 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff_raw ), // input wire [15 : 0] probe_in1 - .probe_in2 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff ) // input wire [15 : 0] probe_in2 -); -ila_rx_pre u_ila_rx_pre +// ila_cal u_ila_cal +// ( +// .clk (sys_clk ), // input wire clk +// .probe0 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0 +// .probe1 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1 +// .probe2 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2 +// .probe3 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3 +// .probe4 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4 +// .probe5 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5 +// .probe6 (u_rx_pre_process.u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6 +// .probe7 (rx_ch2_i ), // input wire [11:0] probe7 +// .probe8 (rx_ch2_q ), // input wire [11:0] probe8 +// .probe9 (rx_ch4_i ), // input wire [11:0] probe9 +// .probe10(rx_ch4_q ), // input wire [11:0] probe10 +// .probe11(u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe11 +// .probe12(u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe12 +// .probe13(u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe13 +// .probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14 +// ); + +// vio_cal u_vio_cal +// ( +// .clk (sys_clk ), // input wire clk +// .probe_in0 (u_rx_pre_process.u_ad9361_phase_cal.relative_delay ), // input wire [4 : 0] probe_in0 +// .probe_in1 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff_raw ), // input wire [15 : 0] probe_in1 +// .probe_in2 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff ) // input wire [15 : 0] probe_in2 +// ); + +// ila_rx_pre u_ila_rx_pre +// ( +// .clk (clk_96m ), // input wire clk +// .probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0 +// .probe1 (accor_stream_valid ), // input wire [0:0] probe1 +// .probe2 (accor_stream_data ), // input wire [0:0] probe2 +// .probe3 (weight_stream_data ) // input wire [0:0] probe3 +// ); + +vio_weight u_vio_weight ( - .clk (clk_96m ), // input wire clk - .probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0 - .probe1 (accor_stream_valid ), // input wire [0:0] probe1 - .probe2 (accor_stream_data ), // input wire [0:0] probe2 - .probe3 (weight_stream_data ) // input wire [0:0] probe3 + .clk (sys_clk ), // input wire clk + .probe_out0 (u_rx_pre_process.weight_ch1_i ), // output wire [15 : 0] probe_out0 + .probe_out1 (u_rx_pre_process.weight_ch1_q ), // output wire [15 : 0] probe_out1 + .probe_out2 (u_rx_pre_process.weight_ch2_i ), // output wire [15 : 0] probe_out2 + .probe_out3 (u_rx_pre_process.weight_ch2_q ), // output wire [15 : 0] probe_out3 + .probe_out4 (u_rx_pre_process.weight_ch3_i ), // output wire [15 : 0] probe_out4 + .probe_out5 (u_rx_pre_process.weight_ch3_q ), // output wire [15 : 0] probe_out5 + .probe_out6 (u_rx_pre_process.weight_ch4_i ), // output wire [15 : 0] probe_out6 + .probe_out7 (u_rx_pre_process.weight_ch4_q ) // output wire [15 : 0] probe_out7 ); vio_manual_ctrl u_vio_manual_ctrl diff --git a/projects/datalink_814/dl814_k7_beam/testbenches/tb_rx_pre.v b/projects/datalink_814/dl814_k7_beam/testbenches/tb_rx_pre.v index d8ef806f..bfe5b584 100644 --- a/projects/datalink_814/dl814_k7_beam/testbenches/tb_rx_pre.v +++ b/projects/datalink_814/dl814_k7_beam/testbenches/tb_rx_pre.v @@ -211,9 +211,11 @@ wire accor_stream_valid; wire accor_stream_data; wire weight_stream_data; wire rx_data_valid; -wire [11:0] rx_data_i, rx_data_q; +wire [29:0] rx_data_i, rx_data_q; -rx_pre_process u_rx_pre_process +rx_pre_process #( + .OUTPUT_DATA_WIDTH (30 ) +) u_rx_pre_process ( // clock & reset .sys_clk (sys_clk ), // input sys_clk @@ -248,14 +250,14 @@ rx_pre_process u_rx_pre_process .rx_data_q (rx_data_q ) ); -assign u_rx_pre_process.weight_ch1_i = 16'd26075; -assign u_rx_pre_process.weight_ch1_q = 16'd15596; -assign u_rx_pre_process.weight_ch2_i = 16'd22431; -assign u_rx_pre_process.weight_ch2_q = 16'd22561; -assign u_rx_pre_process.weight_ch3_i = 16'd23212; -assign u_rx_pre_process.weight_ch3_q = -16'd23129; -assign u_rx_pre_process.weight_ch4_i = 16'd24805; -assign u_rx_pre_process.weight_ch4_q = -16'd15029; +assign u_rx_pre_process.weight_ch1_i = 16'd22858; +assign u_rx_pre_process.weight_ch1_q = -16'd23478; +assign u_rx_pre_process.weight_ch2_i = 16'd19522; +assign u_rx_pre_process.weight_ch2_q = -16'd24955; +assign u_rx_pre_process.weight_ch3_i = 16'd19529; +assign u_rx_pre_process.weight_ch3_q = 16'd24955; +assign u_rx_pre_process.weight_ch4_i = 16'd22853; +assign u_rx_pre_process.weight_ch4_q = 16'd23478; // system clock generation always begin @@ -333,8 +335,8 @@ initial begin end initial begin - r_file_real = $fopen("../xs1_real.csv","r"); - r_file_imag = $fopen("../xs1_imag.csv","r"); + r_file_real = $fopen("../../../../../../testbenches/xs1_real.csv","r"); + r_file_imag = $fopen("../../../../../../testbenches/xs1_imag.csv","r"); @(posedge ad9361_cal_valid) #200; diff --git a/projects/datalink_814/dl814_k7_beam/testbenches/xs1_imag.csv b/projects/datalink_814/dl814_k7_beam/testbenches/xs1_imag.csv index 5ff62f0e..e58c1d62 100644 --- a/projects/datalink_814/dl814_k7_beam/testbenches/xs1_imag.csv +++ b/projects/datalink_814/dl814_k7_beam/testbenches/xs1_imag.csv @@ -1,256 +1,256 @@ --809,-1081,1898,1367 --389,-491,2047,1465 -64,149,1986,1411 -512,770,1738,1218 -913,1317,1315,913 -1221,1742,769,514 -1413,1987,146,62 -1461,2039,-490,-385 -1370,1890,-1079,-810 -1140,1568,-1565,-1141 -806,1078,-1895,-1374 -392,489,-2036,-1467 --69,-141,-1988,-1411 --511,-768,-1739,-1223 --912,-1317,-1320,-915 --1228,-1741,-771,-517 --1410,-1988,-145,-65 --1461,-2038,493,394 --1374,-1895,1081,802 --1139,-1564,1569,1149 --808,-1085,1890,1373 --389,-491,2040,1469 -65,144,1980,1418 -512,770,1738,1226 -923,1319,1314,911 -1216,1741,771,513 -1412,1986,148,63 -1467,2038,-492,-383 -1372,1898,-1079,-811 -1149,1559,-1565,-1145 -803,1080,-1894,-1372 -391,490,-2041,-1463 --62,-154,-1986,-1412 --517,-766,-1736,-1223 --910,-1317,-1320,-910 --1223,-1736,-773,-506 --1414,-1987,-148,-64 --1467,-2040,487,391 --1367,-1898,1082,805 --1143,-1565,1565,1152 --799,-1084,1897,1376 --387,-493,2037,1464 -72,151,1986,1410 -515,769,1734,1224 -916,1319,1319,914 -1226,1735,766,517 -1411,1984,147,70 -1461,2039,-490,-390 -1373,1894,-1078,-806 -1147,1564,-1565,-1148 -811,1077,-1891,-1369 -390,490,-2036,-1469 --67,-147,-1984,-1411 --518,-770,-1736,-1221 --910,-1318,-1317,-913 --1223,-1736,-771,-514 --1414,-1985,-146,-65 --1460,-2043,493,389 --1374,-1895,1082,805 --1144,-1561,1570,1150 --810,-1081,1891,1370 --387,-491,2044,1462 -64,145,1981,1413 -516,772,1740,1224 -914,1318,1324,910 -1222,1732,766,512 -1415,1980,140,64 -1471,2043,-489,-391 -1378,1894,-1079,-801 -1146,1565,-1564,-1147 -808,1086,-1892,-1374 -389,490,-2041,-1465 --64,-143,-1986,-1413 --513,-770,-1737,-1225 --920,-1321,-1319,-912 --1224,-1731,-767,-513 --1411,-1987,-143,-67 --1465,-2042,486,387 --1379,-1898,1079,809 --1144,-1567,1564,1147 --814,-1082,1895,1374 --388,-489,2039,1469 -63,151,1983,1418 -511,771,1734,1226 -916,1317,1322,911 -1224,1737,771,518 -1418,1987,146,64 -1460,2042,-500,-393 -1371,1898,-1077,-811 -1150,1567,-1570,-1138 -809,1081,-1895,-1377 -392,491,-2041,-1461 --63,-143,-1982,-1410 --519,-764,-1735,-1224 --914,-1316,-1315,-910 --1223,-1737,-772,-513 --1407,-1986,-150,-64 --1463,-2047,494,389 --1369,-1891,1082,808 --1143,-1559,1566,1149 --806,-1082,1894,1377 --395,-490,2034,1463 -65,149,1984,1408 -511,767,1740,1221 -914,1318,1312,909 -1221,1735,770,515 -1412,1988,144,66 -1463,2039,-494,-388 -1381,1892,-1084,-807 -1152,1565,-1565,-1146 -809,1079,-1893,-1374 -394,495,-2043,-1470 --64,-148,-1988,-1415 --520,-773,-1732,-1226 --913,-1319,-1317,-909 --1224,-1736,-765,-514 --1413,-1986,-142,-65 --1465,-2041,491,386 --1375,-1896,1079,809 --1143,-1566,1566,1148 --806,-1085,1891,1375 --391,-491,2038,1456 -65,149,1991,1411 -513,769,1735,1219 -912,1315,1319,916 -1223,1735,767,516 -1415,1987,144,67 -1464,2045,-491,-392 -1372,1901,-1079,-807 -1145,1566,-1565,-1146 -810,1080,-1893,-1370 -388,499,-2046,-1464 --66,-146,-1983,-1413 --517,-773,-1738,-1221 --912,-1316,-1317,-912 --1226,-1735,-768,-513 --1409,-1985,-146,-66 --1461,-2037,490,387 --1376,-1894,1080,815 --1144,-1559,1562,1147 --813,-1078,1897,1369 --391,-494,2042,1463 -64,142,1985,1414 -509,769,1736,1224 -911,1314,1314,914 -1222,1739,770,518 -1414,1984,145,65 -1464,2035,-492,-385 -1373,1892,-1081,-814 -1142,1564,-1565,-1148 -808,1081,-1900,-1372 -397,490,-2041,-1461 --62,-149,-1985,-1414 --518,-771,-1730,-1225 --912,-1319,-1321,-911 --1222,-1738,-768,-515 --1414,-1988,-146,-64 --1462,-2040,492,389 --1375,-1894,1076,801 --1143,-1562,1564,1148 --805,-1081,1905,1375 --391,-494,2039,1465 -68,145,1985,1407 -514,770,1739,1225 -908,1315,1320,914 -1225,1735,767,511 -1414,1987,141,61 -1464,2043,-491,-388 -1368,1896,-1082,-808 -1146,1565,-1566,-1147 -807,1078,-1892,-1373 -391,490,-2037,-1463 --64,-146,-1986,-1408 --511,-769,-1738,-1217 --918,-1312,-1318,-916 --1225,-1734,-771,-519 --1410,-1979,-148,-64 --1460,-2039,488,388 --1371,-1892,1084,806 --1148,-1564,1565,1143 --807,-1083,1899,1367 --392,-491,2042,1463 -67,149,1984,1409 -511,771,1735,1218 -917,1319,1314,908 -1220,1734,769,513 -1413,1982,144,68 -1462,2039,-491,-390 -1370,1890,-1081,-811 -1145,1569,-1562,-1146 -811,1081,-1894,-1370 -388,491,-2036,-1458 --69,-146,-1990,-1418 --508,-766,-1737,-1218 --913,-1315,-1317,-908 --1223,-1736,-769,-514 --1410,-1977,-142,-66 --1466,-2042,487,390 --1368,-1892,1080,811 --1149,-1563,1565,1140 --803,-1085,1892,1376 --387,-490,2041,1466 -66,143,1990,1410 -517,770,1734,1228 -909,1314,1317,912 -1228,1733,769,513 -1412,1989,147,61 -1462,2036,-493,-385 -1369,1898,-1080,-808 -1148,1564,-1563,-1147 -812,1083,-1894,-1370 -392,493,-2042,-1456 --62,-149,-1987,-1411 --515,-769,-1737,-1221 --910,-1319,-1322,-914 --1227,-1733,-769,-514 --1415,-1984,-149,-58 --1461,-2042,495,393 --1370,-1893,1083,805 --1146,-1562,1564,1148 --810,-1083,1891,1372 --391,-489,2039,1461 -63,145,1989,1414 -511,774,1732,1224 -910,1320,1316,911 -1221,1741,774,513 -1416,1988,148,63 -1463,2041,-490,-388 -1368,1895,-1082,-805 -1149,1563,-1562,-1145 -812,1086,-1892,-1378 -398,488,-2042,-1465 --66,-146,-1986,-1412 --515,-769,-1737,-1225 --912,-1323,-1313,-912 --1223,-1737,-768,-512 --1410,-1982,-150,-65 --1466,-2039,492,389 --1369,-1902,1080,807 --1148,-1562,1560,1147 --806,-1082,1895,1375 --392,-494,2041,1465 -68,146,1984,1410 -509,766,1739,1223 -915,1311,1317,906 -1219,1739,768,515 -1406,1982,149,59 -1468,2038,-494,-391 -1371,1891,-1077,-806 -1143,1560,-1566,-1148 -808,1074,-1900,-1374 -388,492,-2043,-1462 --64,-149,-1985,-1411 --511,-767,-1741,-1221 --913,-1316,-1319,-914 --1223,-1735,-770,-515 +641,-138,534,-629 +-407,977,1666,-1081 +-1477,1563,1906,-1063 +-1946,1435,1106,-689 +-1382,713,-159,-236 +1,-210,-1054,94 +1366,-849,-1176,359 +1863,-962,-794,739 +1310,-721,-421,1167 +271,-490,-240,1223 +-523,-383,-22,513 +-797,-137,457,-771 +-771,498,1039,-1840 +-725,1297,1294,-1914 +-657,1611,925,-903 +-371,982,29,533 +200,-352,-992,1536 +860,-1572,-1666,1680 +1293,-1942,-1634,1094 +1250,-1318,-799,189 +642,-138,535,-629 +-407,977,1666,-1081 +-1477,1563,1906,-1063 +-1945,1435,1105,-689 +-1382,713,-160,-236 +1,-210,-1055,94 +1366,-849,-1176,359 +1863,-962,-795,740 +1310,-720,-420,1167 +271,-490,-239,1221 +-524,-383,-21,513 +-798,-137,457,-772 +-770,497,1039,-1840 +-725,1297,1294,-1914 +-657,1611,926,-902 +-370,982,30,533 +200,-351,-992,1536 +860,-1572,-1666,1681 +1293,-1942,-1635,1093 +1250,-1317,-798,189 +643,-137,534,-629 +-408,977,1667,-1081 +-1477,1563,1905,-1063 +-1946,1434,1106,-690 +-1381,713,-160,-236 +1,-210,-1055,94 +1366,-849,-1176,360 +1863,-962,-794,739 +1310,-720,-421,1167 +271,-490,-239,1222 +-524,-384,-22,513 +-797,-138,457,-771 +-771,497,1039,-1840 +-725,1296,1293,-1914 +-657,1611,925,-902 +-371,982,30,533 +200,-351,-992,1536 +860,-1573,-1666,1681 +1293,-1942,-1634,1093 +1250,-1318,-798,189 +642,-137,535,-629 +-408,977,1666,-1081 +-1477,1563,1906,-1064 +-1945,1434,1105,-689 +-1381,713,-160,-236 +1,-211,-1054,94 +1366,-850,-1175,360 +1863,-962,-795,739 +1310,-720,-421,1167 +271,-490,-240,1222 +-524,-383,-22,514 +-798,-138,458,-771 +-771,497,1039,-1841 +-725,1296,1294,-1914 +-657,1611,925,-902 +-371,982,30,532 +200,-351,-992,1536 +860,-1573,-1666,1681 +1293,-1942,-1634,1093 +1250,-1317,-798,189 +642,-137,535,-629 +-407,977,1666,-1081 +-1477,1563,1905,-1063 +-1946,1435,1106,-690 +-1381,713,-160,-236 +1,-210,-1055,94 +1366,-849,-1176,359 +1863,-962,-794,739 +1310,-720,-421,1168 +271,-490,-239,1222 +-523,-384,-21,514 +-797,-138,457,-771 +-770,498,1039,-1841 +-725,1296,1294,-1914 +-657,1611,925,-902 +-371,982,30,532 +200,-351,-992,1537 +860,-1573,-1666,1681 +1292,-1942,-1634,1094 +1250,-1317,-798,189 +642,-138,534,-629 +-408,978,1666,-1082 +-1478,1563,1906,-1064 +-1945,1434,1105,-689 +-1381,713,-160,-236 +0,-210,-1054,94 +1366,-849,-1176,359 +1863,-962,-794,739 +1310,-720,-421,1167 +271,-490,-240,1222 +-523,-383,-21,513 +-797,-137,458,-771 +-770,498,1039,-1840 +-726,1296,1294,-1914 +-657,1611,925,-902 +-371,982,29,533 +200,-351,-992,1536 +859,-1572,-1666,1680 +1293,-1942,-1635,1093 +1250,-1318,-798,189 +643,-138,535,-629 +-407,978,1667,-1081 +-1477,1562,1906,-1064 +-1946,1435,1106,-690 +-1381,713,-160,-236 +1,-211,-1054,95 +1366,-849,-1176,359 +1863,-962,-794,739 +1310,-720,-421,1168 +271,-490,-239,1222 +-523,-384,-21,513 +-797,-137,457,-771 +-770,497,1039,-1840 +-725,1296,1294,-1914 +-657,1611,925,-903 +-371,982,30,533 +200,-351,-992,1536 +860,-1573,-1666,1681 +1292,-1942,-1634,1094 +1250,-1318,-798,189 +642,-137,534,-629 +-407,977,1666,-1081 +-1477,1563,1906,-1064 +-1946,1434,1106,-690 +-1381,713,-160,-236 +1,-210,-1055,94 +1367,-849,-1175,359 +1863,-962,-794,738 +1310,-721,-421,1168 +271,-490,-239,1223 +-523,-383,-21,513 +-797,-138,458,-771 +-770,497,1039,-1840 +-725,1296,1294,-1915 +-657,1611,925,-902 +-370,982,29,532 +200,-352,-991,1536 +860,-1572,-1666,1681 +1293,-1942,-1635,1093 +1250,-1318,-798,189 +642,-137,534,-629 +-408,977,1666,-1081 +-1477,1562,1905,-1063 +-1946,1434,1105,-690 +-1381,713,-160,-236 +1,-210,-1055,95 +1366,-849,-1175,359 +1863,-962,-794,739 +1310,-720,-421,1169 +271,-490,-239,1223 +-523,-383,-21,513 +-797,-138,457,-771 +-771,497,1039,-1840 +-725,1297,1293,-1914 +-657,1612,925,-902 +-371,982,30,533 +200,-351,-992,1536 +860,-1573,-1666,1681 +1293,-1941,-1635,1093 +1251,-1317,-798,189 +643,-137,534,-628 +-407,977,1667,-1081 +-1477,1563,1906,-1064 +-1945,1435,1105,-689 +-1382,713,-160,-236 +1,-211,-1055,95 +1366,-850,-1176,360 +1863,-962,-794,739 +1310,-721,-421,1167 +271,-489,-240,1222 +-524,-383,-21,513 +-797,-138,458,-771 +-771,497,1040,-1840 +-725,1297,1293,-1914 +-657,1611,925,-902 +-371,982,30,533 +200,-351,-993,1537 +860,-1573,-1666,1681 +1293,-1942,-1635,1093 +1250,-1317,-798,190 +643,-137,535,-629 +-408,978,1666,-1081 +-1477,1563,1905,-1064 +-1946,1435,1106,-690 +-1381,713,-160,-236 +1,-210,-1054,94 +1366,-849,-1176,360 +1863,-962,-794,739 +1310,-720,-421,1168 +272,-490,-239,1222 +-524,-383,-21,513 +-797,-138,458,-771 +-771,497,1039,-1841 +-725,1295,1294,-1914 +-656,1611,925,-902 +-370,982,30,533 +200,-351,-992,1536 +860,-1573,-1666,1681 +1293,-1942,-1635,1094 +1250,-1317,-798,190 +642,-138,535,-629 +-407,977,1666,-1081 +-1477,1563,1906,-1063 +-1945,1434,1106,-689 +-1381,713,-160,-236 +1,-210,-1054,94 +1366,-849,-1176,359 +1863,-962,-794,739 +1310,-720,-421,1168 +271,-489,-240,1221 +-523,-383,-22,513 +-797,-138,457,-771 +-771,497,1039,-1841 +-725,1296,1294,-1914 +-657,1611,925,-902 +-370,982,29,532 +200,-351,-991,1536 +860,-1572,-1666,1680 +1293,-1942,-1635,1093 +1250,-1317,-798,189 +642,-138,534,-629 +-407,977,1667,-1081 +-1477,1563,1906,-1064 +-1945,1435,1106,-689 +-1382,713,-160,-236 +1,-210,-1055,94 +1366,-849,-1177,360 +1863,-962,-794,739 +1310,-720,-421,1167 +271,-491,-239,1223 +-524,-384,-21,514 +-797,-138,457,-771 +-770,497,1039,-1841 +-725,1296,1294,-1914 +-657,1612,925,-902 +-371,982,30,533 diff --git a/projects/datalink_814/dl814_k7_beam/testbenches/xs1_real.csv b/projects/datalink_814/dl814_k7_beam/testbenches/xs1_real.csv index b09e2e19..e10c567d 100644 --- a/projects/datalink_814/dl814_k7_beam/testbenches/xs1_real.csv +++ b/projects/datalink_814/dl814_k7_beam/testbenches/xs1_real.csv @@ -1,256 +1,256 @@ --1231,-1735,-772,-511 --1411,-1983,-149,-60 --1461,-2040,490,393 --1373,-1900,1079,810 --1146,-1563,1560,1147 --809,-1081,1896,1373 --391,-490,2043,1464 -69,147,1982,1413 -517,769,1736,1220 -910,1321,1322,913 -1225,1735,772,516 -1412,1982,147,63 -1461,2038,-494,-388 -1373,1893,-1085,-809 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