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update duifei_basic_v1.0 and module ad9361_mapping

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in duifei_basic_v1.0, ila of tx and rx signal is seperated into two ilas; in module ad9361_mapping, the DDR_CLK_MODE of rx mapping iddr is changed to SAME_EDGE, and the output iq of iddr is swappedto satisfy ad9361 data interface
This commit is contained in:
josh
2023-04-06 11:16:56 +08:00
parent 6fb7ff1a34
commit e1399346b7
216 changed files with 1739814 additions and 528146 deletions
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modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v
+22 -22
View File
@@ -54,18 +54,18 @@ generate
for (m=0; m<12; m=m+1) begin : rx_data_iddr
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
.DDR_CLK_EDGE ("SAME_EDGE" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
) i_rx_data_iddr (
.CE (1'b1 ),
.R (1'b0 ),
.S (1'b0 ),
.C (clk_2x_in ),
.D (rx_data[m] ),
.Q1 (rx_data_i[m] ),
.Q2 (rx_data_q[m] )
.CE (1'b1 ),
.R (1'b0 ),
.S (1'b0 ),
.C (clk_2x_in ),
.D (rx_data[m] ),
.Q1 (rx_data_q[m] ),
.Q2 (rx_data_i[m] )
);
end
@@ -76,18 +76,18 @@ wire rx_frame_i;
wire rx_frame_q;
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
.DDR_CLK_EDGE ("SAME_EDGE" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
) i_rx_frame_iddr (
.CE (1'b1 ),
.R (1'b0 ),
.S (1'b0 ),
.C (clk_2x_in ),
.D (rx_frame ),
.Q1 (rx_frame_i ),
.Q2 (rx_frame_q )
.CE (1'b1 ),
.R (1'b0 ),
.S (1'b0 ),
.C (clk_2x_in ),
.D (rx_frame ),
.Q1 (rx_frame_q ),
.Q2 (rx_frame_i )
);
// divide rx_data to dual channel
modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_single.v
+11 -11
View File
@@ -52,18 +52,18 @@ generate
for (m=0; m<12; m=m+1) begin : rx_data_iddr
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
.DDR_CLK_EDGE ("SAME_EDGE" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
) i_rx_data_iddr (
.CE (1'b1 ),
.R (1'b0 ),
.S (1'b0 ),
.C (clk_in ),
.D (rx_data[m] ),
.Q1 (rx_raw_i[m] ),
.Q2 (rx_raw_q[m] )
.CE (1'b1 ),
.R (1'b0 ),
.S (1'b0 ),
.C (clk_in ),
.D (rx_data[m] ),
.Q1 (rx_raw_q[m] ),
.Q2 (rx_raw_i[m] )
);
end
modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_lvds_dual.v
+22 -22
View File
@@ -66,18 +66,18 @@ IBUFDS #(
);
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
.DDR_CLK_EDGE ("SAME_EDGE" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
) u_rx_data_iddr (
.CE (1'b1 ), // clock enable
.R (1'b0 ), // iddr reset
.S (1'b0 ), // iddr set
.C (clk_4x_in ), // iddr clock
.D (rx_data[m] ), // ddr data
.Q1 (rx_data_i[m] ), // sdr data at rising edge
.Q2 (rx_data_q[m] ) // sdr data at falling edge
.CE (1'b1 ), // clock enable
.R (1'b0 ), // iddr reset
.S (1'b0 ), // iddr set
.C (clk_4x_in ), // iddr clock
.D (rx_data[m] ), // ddr data
.Q1 (rx_data_q[m] ), // sdr data at rising edge
.Q2 (rx_data_i[m] ) // sdr data at falling edge
);
end
@@ -98,18 +98,18 @@ IBUFDS #(
);
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
.DDR_CLK_EDGE ("SAME_EDGE" ),
.INIT_Q1 (1'b0 ),
.INIT_Q2 (1'b0 ),
.SRTYPE ("ASYNC" )
) u_rx_frame_iddr (
.CE (1'b1 ), // clock enable
.R (1'b0 ), // iddr reset
.S (1'b0 ), // iddr set
.C (clk_4x_in ), // iddr clock
.D (rx_frame ), // ddr data
.Q1 (rx_frame_i ), // sdr data at rising edge
.Q2 (rx_frame_q ) // sdr data at falling edge
.CE (1'b1 ), // clock enable
.R (1'b0 ), // iddr reset
.S (1'b0 ), // iddr set
.C (clk_4x_in ), // iddr clock
.D (rx_frame ), // ddr data
.Q1 (rx_frame_q ), // sdr data at rising edge
.Q2 (rx_frame_i ) // sdr data at falling edge
);
// unpack rx frame & data