update duifei_basic_v1.0 and module ad9361_mapping

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in duifei_basic_v1.0, ila of tx and rx signal is seperated into two ilas; in module ad9361_mapping, the DDR_CLK_MODE of rx mapping iddr is changed to SAME_EDGE, and the output iq of iddr is swappedto satisfy ad9361 data interface

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josh

2023-04-06 11:16:56 +08:00

parent 6fb7ff1a34

commit e1399346b7

216 changed files with 1739814 additions and 528146 deletions

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projects/duifei/duifei_basic/project/project.sdk/system_top.hdf

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