josh/vivado-202304
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

add dl814_k7_basic; update dl814_z7 ps project

Browse Source 
dl814_k7_basic is the driver instance of board smq7k410t_b9361, along with basic clock, adc and dac configurations; include nulling algorithm into dl814_z7 project
This commit is contained in:
josh
2023-03-29 17:34:49 +08:00
parent cd256a8cd6
commit e8a34c95e0
2060 changed files with 4678610 additions and 198681 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/264e4d8f5de713c2/264e4d8f5de713c2.xci
+89
View File
@@ -0,0 +1,89 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>264e4d8f5de713c2</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>selectio_lvds_tx</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="selectio_wiz" spirit:version="5.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACTIVE_EDGE">RISING</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_DIR">OUTPUTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_DELAY">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_TAP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IO_STD">LVCMOS33</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_TAP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_SIG_TYPE">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_RESET">NOT_APP</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_WRAP">NOT_APP</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BUF">BUFIO2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DELAY">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_EN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_IO_STD">LVCMOS33</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SIG_TYPE">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IO_STD">LVCMOS18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_TAP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONFIG_CLK_FWD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">selectio_lvds_tx</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_ALIGNMENT">C0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_CLK_BUF">BUFR</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BITSLIP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TRAIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDELAY_HIGH_PERF_MODE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL_BUFG">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ACTIVE_EDGE">SDR</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_DELAY">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_TAP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_TAP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_BUF">BUFIO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_IO_STD">LVCMOS33</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_DDR_ALIGNMENT">SAME_EDGE_PIPELINED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ODDR_ALIGNMENT">SAME_EDGE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SERIALIZATION_FACTOR">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYSTEM_DATA_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRAIN_CONSTANT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_DETECTOR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SERIALIZATION">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_TEMPLATE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">264e4d8f5de713c2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">selectio_lvds_tx</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">af96b0bc</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/264e4d8f5de713c2/selectio_lvds_tx.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/264e4d8f5de713c2/selectio_lvds_tx_sim_netlist.v
+189
View File
@@ -0,0 +1,189 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 29 15:36:55 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.v
// Design : selectio_lvds_tx
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* DEV_W = "2" *) (* SYS_W = "2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(data_out_from_device,
data_out_to_pins,
clk_in,
clk_out,
io_reset);
input [1:0]data_out_from_device;
output [1:0]data_out_to_pins;
input clk_in;
output clk_out;
input io_reset;
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in;
wire clk_out;
wire [1:0]data_out_from_device;
(* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [1:0]data_out_to_pins;
wire io_reset;
(* DEV_W = "2" *)
(* SYS_W = "2" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz inst
(.clk_in(clk_in),
.clk_out(clk_out),
.data_out_from_device(data_out_from_device),
.data_out_to_pins(data_out_to_pins),
.io_reset(io_reset));
endmodule
(* DEV_W = "2" *) (* SYS_W = "2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz
(data_out_from_device,
data_out_to_pins,
clk_in,
clk_out,
io_reset);
input [1:0]data_out_from_device;
output [1:0]data_out_to_pins;
input clk_in;
output clk_out;
input io_reset;
wire clk_in;
wire clk_in_int;
wire clk_out;
wire [1:0]data_out_from_device;
wire [1:0]data_out_to_pins;
wire io_reset;
wire \pins[0].data_out_from_device_q ;
wire \pins[1].data_out_from_device_q ;
(* BOX_TYPE = "PRIMITIVE" *)
BUFR #(
.BUFR_DIVIDE("BYPASS"),
.SIM_DEVICE("7SERIES"))
clkout_buf_inst
(.CE(1'b1),
.CLR(1'b0),
.I(clk_in_int),
.O(clk_out));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF ibuf_clk_inst
(.I(clk_in),
.O(clk_in_int));
(* BOX_TYPE = "PRIMITIVE" *)
(* IOB = "TRUE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\pins[0].fdre_out_inst
(.C(clk_out),
.CE(1'b1),
.D(data_out_from_device[0]),
.Q(\pins[0].data_out_from_device_q ),
.R(io_reset));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
OBUF \pins[0].obuf_inst
(.I(\pins[0].data_out_from_device_q ),
.O(data_out_to_pins[0]));
(* BOX_TYPE = "PRIMITIVE" *)
(* IOB = "TRUE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\pins[1].fdre_out_inst
(.C(clk_out),
.CE(1'b1),
.D(data_out_from_device[1]),
.Q(\pins[1].data_out_from_device_q ),
.R(io_reset));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
OBUF \pins[1].obuf_inst
(.I(\pins[1].data_out_from_device_q ),
.O(data_out_to_pins[1]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/264e4d8f5de713c2/selectio_lvds_tx_sim_netlist.vhdl
+143
View File
@@ -0,0 +1,143 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 29 15:36:55 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.vhdl
-- Design : selectio_lvds_tx
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz is
port (
data_out_from_device : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
io_reset : in STD_LOGIC
);
attribute DEV_W : integer;
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz : entity is 2;
attribute SYS_W : integer;
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz : entity is 2;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz is
signal clk_in_int : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal \pins[0].data_out_from_device_q\ : STD_LOGIC;
signal \pins[1].data_out_from_device_q\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE";
attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO";
attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE";
attribute IOB : string;
attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE";
attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE";
attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE";
attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE";
attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE";
attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE";
attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE";
begin
clk_out <= \^clk_out\;
clkout_buf_inst: unisim.vcomponents.BUFR
generic map(
BUFR_DIVIDE => "BYPASS",
SIM_DEVICE => "7SERIES"
)
port map (
CE => '1',
CLR => '0',
I => clk_in_int,
O => \^clk_out\
);
ibuf_clk_inst: unisim.vcomponents.IBUF
port map (
I => clk_in,
O => clk_in_int
);
\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => \^clk_out\,
CE => '1',
D => data_out_from_device(0),
Q => \pins[0].data_out_from_device_q\,
R => io_reset
);
\pins[0].obuf_inst\: unisim.vcomponents.OBUF
port map (
I => \pins[0].data_out_from_device_q\,
O => data_out_to_pins(0)
);
\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => \^clk_out\,
CE => '1',
D => data_out_from_device(1),
Q => \pins[1].data_out_from_device_q\,
R => io_reset
);
\pins[1].obuf_inst\: unisim.vcomponents.OBUF
port map (
I => \pins[1].data_out_from_device_q\,
O => data_out_to_pins(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
data_out_from_device : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
io_reset : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute DEV_W : integer;
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2;
attribute SYS_W : integer;
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute DEV_W of inst : label is 2;
attribute SYS_W of inst : label is 2;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz
port map (
clk_in => clk_in,
clk_out => clk_out,
data_out_from_device(1 downto 0) => data_out_from_device(1 downto 0),
data_out_to_pins(1 downto 0) => data_out_to_pins(1 downto 0),
io_reset => io_reset
);
end STRUCTURE;
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/264e4d8f5de713c2/selectio_lvds_tx_stub.v
+24
View File
@@ -0,0 +1,24 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 29 15:36:55 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.v
// Design : selectio_lvds_tx
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_out_from_device, data_out_to_pins,
clk_in, clk_out, io_reset)
/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[1:0],data_out_to_pins[1:0],clk_in,clk_out,io_reset" */;
input [1:0]data_out_from_device;
output [1:0]data_out_to_pins;
input clk_in;
output clk_out;
input io_reset;
endmodule
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/264e4d8f5de713c2/selectio_lvds_tx_stub.vhdl
+32
View File
@@ -0,0 +1,32 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 29 15:36:55 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.vhdl
-- Design : selectio_lvds_tx
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
data_out_from_device : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
io_reset : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "data_out_from_device[1:0],data_out_to_pins[1:0],clk_in,clk_out,io_reset";
begin
end;
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
+8 -7
View File
@@ -1,30 +1,31 @@
version:1
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3130:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3139:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:36:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6577697070726f6a65637477697a6172645f69705f6c6f636174696f6e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6577697070726f6a65637477697a6172645f70617274:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f6578697374696e675f6970:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f70726f706572746965735f77696e646f77:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f70726f706572746965735f77696e646f77:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f6c6f63616c5f636f70795f6f665f74686573655f66696c65735f696e746f:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:34:00:00
eof:3545337028
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:31:00:00
eof:153380683
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf
+4 -2
View File
@@ -3,5 +3,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:33:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:31:00:00
eof:3496878934
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:33:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:32:00:00
eof:3170208671
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc
+1 -1
View File
@@ -1,3 +1,3 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:1
6d6f64655f636f756e7465727c4755494d6f6465:2
eof:
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf
+5 -8
View File
@@ -1,7 +1,7 @@
version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3034356666673930302d32:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f6265616d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:73656c656374696f5f6c7664735f7478:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@@ -33,10 +33,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a323973:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323333352e3035314d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3931362e3831364d42:00:00
eof:315750305
f:398234019
842
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a303973:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323030392e3430364d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3630372e3438384d42:00:00
eof:3619445103
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
+13 -10
View File
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Mar 28 16:24:08 2023">
<application name="pa" timeStamp="Wed Mar 29 15:47:46 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="90f17e81ee8c43b98bd8d5d76165bd09" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -21,42 +21,45 @@ This means code written to parse this file will need to be revisited each subseq
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
<property name="OpenPreviousIPHandler" value="1" type="JavaHandler"/>
<property name="RecustomizeCore" value="3" type="JavaHandler"/>
<property name="ShowView" value="2" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="4" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="4" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="10" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="19" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_PROPERTIES_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_PROPERTIES_WINDOW" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="2" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="3" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_DOCUMENTATION" value="4" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="43" type="GuiMode"/>
<property name="GuiMode" value="47" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="30" type="TclMode"/>
<property name="TclMode" value="32" type="TclMode"/>
</item>
</section>
</application>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml
+8
View File
@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="selectio_lvds_tx_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/c2c_rx_ila_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="c2c_rx_ila_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991652">
<File Type="VDS-TIMING-PB" Name="c2c_rx_ila_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="c2c_rx_ila_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="c2c_rx_ila.dcp"/>
<File Type="REPORTS-TCL" Name="c2c_rx_ila_reports.tcl"/>
<File Type="PA-TCL" Name="c2c_rx_ila.tcl"/>
<File Type="RDS-RDS" Name="c2c_rx_ila.vds"/>
<File Type="RDS-PROPCONSTRS" Name="c2c_rx_ila_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="c2c_rx_ila_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="c2c_rx_ila_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="c2c_rx_ila_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="c2c_rx_ila.vds"/>
<File Type="RDS-DCP" Name="c2c_rx_ila.dcp"/>
<File Type="PA-TCL" Name="c2c_rx_ila.tcl"/>
<File Type="REPORTS-TCL" Name="c2c_rx_ila_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/c2c_rx_ila">
<File Path="$PPRDIR/../c2c_rx_ila/c2c_rx_ila.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/c2c_tx_ila_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="c2c_tx_ila_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="c2c_tx_ila_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="c2c_tx_ila_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="c2c_tx_ila.dcp"/>
<File Type="REPORTS-TCL" Name="c2c_tx_ila_reports.tcl"/>
<File Type="PA-TCL" Name="c2c_tx_ila.tcl"/>
<File Type="RDS-RDS" Name="c2c_tx_ila.vds"/>
<File Type="RDS-PROPCONSTRS" Name="c2c_tx_ila_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="c2c_tx_ila_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="c2c_tx_ila_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="c2c_tx_ila_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="c2c_tx_ila.vds"/>
<File Type="RDS-DCP" Name="c2c_tx_ila.dcp"/>
<File Type="PA-TCL" Name="c2c_tx_ila.tcl"/>
<File Type="REPORTS-TCL" Name="c2c_tx_ila_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/c2c_tx_ila">
<File Path="$PPRDIR/../c2c_tx_ila/c2c_tx_ila.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/clk_wiz_25m_1to3_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="clk_wiz_25m_1to3_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="clk_wiz_25m_1to3_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_25m_1to3_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="clk_wiz_25m_1to3.dcp"/>
<File Type="REPORTS-TCL" Name="clk_wiz_25m_1to3_reports.tcl"/>
<File Type="PA-TCL" Name="clk_wiz_25m_1to3.tcl"/>
<File Type="RDS-RDS" Name="clk_wiz_25m_1to3.vds"/>
<File Type="RDS-PROPCONSTRS" Name="clk_wiz_25m_1to3_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="clk_wiz_25m_1to3_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="clk_wiz_25m_1to3_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="clk_wiz_25m_1to3_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="clk_wiz_25m_1to3.vds"/>
<File Type="RDS-DCP" Name="clk_wiz_25m_1to3.dcp"/>
<File Type="PA-TCL" Name="clk_wiz_25m_1to3.tcl"/>
<File Type="REPORTS-TCL" Name="clk_wiz_25m_1to3_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_25m_1to3">
<File Path="$PPRDIR/../clk_wiz_25m_1to3/clk_wiz_25m_1to3.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/clk_wiz_96m_1to1_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="clk_wiz_96m_1to1_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="clk_wiz_96m_1to1_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_96m_1to1_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="clk_wiz_96m_1to1.dcp"/>
<File Type="REPORTS-TCL" Name="clk_wiz_96m_1to1_reports.tcl"/>
<File Type="PA-TCL" Name="clk_wiz_96m_1to1.tcl"/>
<File Type="RDS-RDS" Name="clk_wiz_96m_1to1.vds"/>
<File Type="RDS-PROPCONSTRS" Name="clk_wiz_96m_1to1_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="clk_wiz_96m_1to1_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="clk_wiz_96m_1to1_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="clk_wiz_96m_1to1_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="clk_wiz_96m_1to1.vds"/>
<File Type="RDS-DCP" Name="clk_wiz_96m_1to1.dcp"/>
<File Type="PA-TCL" Name="clk_wiz_96m_1to1.tcl"/>
<File Type="REPORTS-TCL" Name="clk_wiz_96m_1to1_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_96m_1to1">
<File Path="$PPRDIR/../clk_wiz_96m_1to1/clk_wiz_96m_1to1.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/clk_wiz_beam_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="clk_wiz_beam_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="clk_wiz_beam_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_beam_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="clk_wiz_beam.dcp"/>
<File Type="REPORTS-TCL" Name="clk_wiz_beam_reports.tcl"/>
<File Type="PA-TCL" Name="clk_wiz_beam.tcl"/>
<File Type="RDS-RDS" Name="clk_wiz_beam.vds"/>
<File Type="RDS-PROPCONSTRS" Name="clk_wiz_beam_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="clk_wiz_beam_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="clk_wiz_beam_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="clk_wiz_beam_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="clk_wiz_beam.vds"/>
<File Type="RDS-DCP" Name="clk_wiz_beam.dcp"/>
<File Type="PA-TCL" Name="clk_wiz_beam.tcl"/>
<File Type="REPORTS-TCL" Name="clk_wiz_beam_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_beam">
<File Path="$PPRDIR/../clk_wiz_beam/clk_wiz_beam.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/clk_wiz_glink_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="clk_wiz_glink_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="clk_wiz_glink_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_glink_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="clk_wiz_glink.dcp"/>
<File Type="REPORTS-TCL" Name="clk_wiz_glink_reports.tcl"/>
<File Type="PA-TCL" Name="clk_wiz_glink.tcl"/>
<File Type="RDS-RDS" Name="clk_wiz_glink.vds"/>
<File Type="RDS-PROPCONSTRS" Name="clk_wiz_glink_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="clk_wiz_glink_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="clk_wiz_glink_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="clk_wiz_glink_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="clk_wiz_glink.vds"/>
<File Type="RDS-DCP" Name="clk_wiz_glink.dcp"/>
<File Type="PA-TCL" Name="clk_wiz_glink.tcl"/>
<File Type="REPORTS-TCL" Name="clk_wiz_glink_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_glink">
<File Path="$PPRDIR/../clk_wiz_glink/clk_wiz_glink.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/clk_wiz_lvds_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="clk_wiz_lvds_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="clk_wiz_lvds_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_lvds_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="clk_wiz_lvds.dcp"/>
<File Type="REPORTS-TCL" Name="clk_wiz_lvds_reports.tcl"/>
<File Type="PA-TCL" Name="clk_wiz_lvds.tcl"/>
<File Type="RDS-RDS" Name="clk_wiz_lvds.vds"/>
<File Type="RDS-PROPCONSTRS" Name="clk_wiz_lvds_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="clk_wiz_lvds_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="clk_wiz_lvds_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="clk_wiz_lvds_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="clk_wiz_lvds.vds"/>
<File Type="RDS-DCP" Name="clk_wiz_lvds.dcp"/>
<File Type="PA-TCL" Name="clk_wiz_lvds.tcl"/>
<File Type="REPORTS-TCL" Name="clk_wiz_lvds_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_lvds">
<File Path="$PPRDIR/../clk_wiz_lvds/clk_wiz_lvds.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/fifo_en_creat_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="fifo_en_creat_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="fifo_en_creat_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="fifo_en_creat_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="fifo_en_creat.dcp"/>
<File Type="REPORTS-TCL" Name="fifo_en_creat_reports.tcl"/>
<File Type="PA-TCL" Name="fifo_en_creat.tcl"/>
<File Type="RDS-RDS" Name="fifo_en_creat.vds"/>
<File Type="RDS-PROPCONSTRS" Name="fifo_en_creat_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="fifo_en_creat_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="fifo_en_creat_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="fifo_en_creat_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="fifo_en_creat.vds"/>
<File Type="RDS-DCP" Name="fifo_en_creat.dcp"/>
<File Type="PA-TCL" Name="fifo_en_creat.tcl"/>
<File Type="REPORTS-TCL" Name="fifo_en_creat_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_en_creat">
<File Path="$PPRDIR/../fifo_en_creat/fifo_en_creat.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_beam_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_beam_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="ila_beam_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_beam_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_beam.dcp"/>
<File Type="REPORTS-TCL" Name="ila_beam_reports.tcl"/>
<File Type="PA-TCL" Name="ila_beam.tcl"/>
<File Type="RDS-RDS" Name="ila_beam.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_beam_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_beam_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_beam_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_beam_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_beam.vds"/>
<File Type="RDS-DCP" Name="ila_beam.dcp"/>
<File Type="PA-TCL" Name="ila_beam.tcl"/>
<File Type="REPORTS-TCL" Name="ila_beam_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_beam">
<File Path="$PPRDIR/../ila_beam/ila_beam.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_c2c_dma_rx_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_c2c_dma_rx_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991653">
<File Type="VDS-TIMING-PB" Name="ila_c2c_dma_rx_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_c2c_dma_rx_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_c2c_dma_rx.dcp"/>
<File Type="REPORTS-TCL" Name="ila_c2c_dma_rx_reports.tcl"/>
<File Type="PA-TCL" Name="ila_c2c_dma_rx.tcl"/>
<File Type="RDS-RDS" Name="ila_c2c_dma_rx.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_c2c_dma_rx_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_c2c_dma_rx_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_c2c_dma_rx_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_c2c_dma_rx_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_c2c_dma_rx.vds"/>
<File Type="RDS-DCP" Name="ila_c2c_dma_rx.dcp"/>
<File Type="PA-TCL" Name="ila_c2c_dma_rx.tcl"/>
<File Type="REPORTS-TCL" Name="ila_c2c_dma_rx_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_c2c_dma_rx">
<File Path="$PPRDIR/../ila_c2c_dma_rx/ila_c2c_dma_rx.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_c2c_dma_tx_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_c2c_dma_tx_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991654">
<File Type="VDS-TIMING-PB" Name="ila_c2c_dma_tx_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_c2c_dma_tx_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_c2c_dma_tx.dcp"/>
<File Type="REPORTS-TCL" Name="ila_c2c_dma_tx_reports.tcl"/>
<File Type="PA-TCL" Name="ila_c2c_dma_tx.tcl"/>
<File Type="RDS-RDS" Name="ila_c2c_dma_tx.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_c2c_dma_tx_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_c2c_dma_tx_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_c2c_dma_tx_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_c2c_dma_tx_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_c2c_dma_tx.vds"/>
<File Type="RDS-DCP" Name="ila_c2c_dma_tx.dcp"/>
<File Type="PA-TCL" Name="ila_c2c_dma_tx.tcl"/>
<File Type="REPORTS-TCL" Name="ila_c2c_dma_tx_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_c2c_dma_tx">
<File Path="$PPRDIR/../ila_c2c_dma_tx/ila_c2c_dma_tx.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_dma_fifo_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_dma_fifo_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991654">
<File Type="VDS-TIMING-PB" Name="ila_dma_fifo_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_dma_fifo_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_dma_fifo.dcp"/>
<File Type="REPORTS-TCL" Name="ila_dma_fifo_reports.tcl"/>
<File Type="PA-TCL" Name="ila_dma_fifo.tcl"/>
<File Type="RDS-RDS" Name="ila_dma_fifo.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_dma_fifo_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_dma_fifo_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_dma_fifo_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_dma_fifo_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_dma_fifo.vds"/>
<File Type="RDS-DCP" Name="ila_dma_fifo.dcp"/>
<File Type="PA-TCL" Name="ila_dma_fifo.tcl"/>
<File Type="REPORTS-TCL" Name="ila_dma_fifo_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_dma_fifo">
<File Path="$PPRDIR/../ila_dma_fifo/ila_dma_fifo.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_en_creat_in_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_en_creat_in_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991654">
<File Type="VDS-TIMING-PB" Name="ila_en_creat_in_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_en_creat_in_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_en_creat_in.dcp"/>
<File Type="REPORTS-TCL" Name="ila_en_creat_in_reports.tcl"/>
<File Type="PA-TCL" Name="ila_en_creat_in.tcl"/>
<File Type="RDS-RDS" Name="ila_en_creat_in.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_en_creat_in_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_en_creat_in_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_en_creat_in_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_en_creat_in_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_en_creat_in.vds"/>
<File Type="RDS-DCP" Name="ila_en_creat_in.dcp"/>
<File Type="PA-TCL" Name="ila_en_creat_in.tcl"/>
<File Type="REPORTS-TCL" Name="ila_en_creat_in_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_en_creat_in">
<File Path="$PPRDIR/../ila_en_creat_in/ila_en_creat_in.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_en_creat_out_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_en_creat_out_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991654">
<File Type="VDS-TIMING-PB" Name="ila_en_creat_out_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_en_creat_out_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_en_creat_out.dcp"/>
<File Type="REPORTS-TCL" Name="ila_en_creat_out_reports.tcl"/>
<File Type="PA-TCL" Name="ila_en_creat_out.tcl"/>
<File Type="RDS-RDS" Name="ila_en_creat_out.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_en_creat_out_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_en_creat_out_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_en_creat_out_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_en_creat_out_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_en_creat_out.vds"/>
<File Type="RDS-DCP" Name="ila_en_creat_out.dcp"/>
<File Type="PA-TCL" Name="ila_en_creat_out.tcl"/>
<File Type="REPORTS-TCL" Name="ila_en_creat_out_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_en_creat_out">
<File Path="$PPRDIR/../ila_en_creat_out/ila_en_creat_out.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_glink_2_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_glink_2_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991655">
<File Type="VDS-TIMING-PB" Name="ila_glink_2_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_glink_2_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_glink_2.dcp"/>
<File Type="REPORTS-TCL" Name="ila_glink_2_reports.tcl"/>
<File Type="PA-TCL" Name="ila_glink_2.tcl"/>
<File Type="RDS-RDS" Name="ila_glink_2.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_glink_2_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_glink_2_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_glink_2_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_glink_2_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_glink_2.vds"/>
<File Type="RDS-DCP" Name="ila_glink_2.dcp"/>
<File Type="PA-TCL" Name="ila_glink_2.tcl"/>
<File Type="REPORTS-TCL" Name="ila_glink_2_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_glink_2">
<File Path="$PPRDIR/../ila_glink_2/ila_glink_2.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/ila_glink_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_glink_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991654">
<File Type="VDS-TIMING-PB" Name="ila_glink_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="ila_glink_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ila_glink.dcp"/>
<File Type="REPORTS-TCL" Name="ila_glink_reports.tcl"/>
<File Type="PA-TCL" Name="ila_glink.tcl"/>
<File Type="RDS-RDS" Name="ila_glink.vds"/>
<File Type="RDS-PROPCONSTRS" Name="ila_glink_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="ila_glink_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_glink_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_glink_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_glink.vds"/>
<File Type="RDS-DCP" Name="ila_glink.dcp"/>
<File Type="PA-TCL" Name="ila_glink.tcl"/>
<File Type="REPORTS-TCL" Name="ila_glink_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_glink">
<File Path="$PPRDIR/../ila_glink/ila_glink.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/gen_run.xml
+6 -11
View File
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="selectio_lvds_rx_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991655">
<File Type="VDS-TIMING-PB" Name="selectio_lvds_rx_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="selectio_lvds_rx_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="selectio_lvds_rx.dcp"/>
<File Type="REPORTS-TCL" Name="selectio_lvds_rx_reports.tcl"/>
<File Type="PA-TCL" Name="selectio_lvds_rx.tcl"/>
<File Type="RDS-RDS" Name="selectio_lvds_rx.vds"/>
<File Type="RDS-PROPCONSTRS" Name="selectio_lvds_rx_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="selectio_lvds_rx_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="selectio_lvds_rx_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="selectio_lvds_rx_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="selectio_lvds_rx.vds"/>
<File Type="RDS-DCP" Name="selectio_lvds_rx.dcp"/>
<File Type="PA-TCL" Name="selectio_lvds_rx.tcl"/>
<File Type="REPORTS-TCL" Name="selectio_lvds_rx_reports.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/selectio_lvds_rx">
<File Path="$PPRDIR/../selectio_lvds_rx/selectio_lvds_rx.xci">
<FileInfo>
@@ -56,9 +53,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/.vivado.begin.rst
+1 -1
View File
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="66209" HostCore="20" HostMemory="65589000">
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="50954" HostCore="20" HostMemory="65588996">
</Process>
</ProcessHandle>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/gen_run.xml
+10 -12
View File
@@ -1,23 +1,23 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="selectio_lvds_tx_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1679991655">
<GenRun Id="selectio_lvds_tx_synth_1" LaunchPart="xc7z045ffg900-2" LaunchTime="1680075398">
<File Type="VDS-TIMING-PB" Name="selectio_lvds_tx_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="selectio_lvds_tx_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="selectio_lvds_tx.dcp"/>
<File Type="RDS-UTIL-PB" Name="selectio_lvds_tx_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="selectio_lvds_tx_utilization_synth.rpt"/>
<File Type="RDS-PROPCONSTRS" Name="selectio_lvds_tx_drc_synth.rpt"/>
<File Type="RDS-RDS" Name="selectio_lvds_tx.vds"/>
<File Type="REPORTS-TCL" Name="selectio_lvds_tx_reports.tcl"/>
<File Type="PA-TCL" Name="selectio_lvds_tx.tcl"/>
<File Type="RDS-RDS" Name="selectio_lvds_tx.vds"/>
<File Type="RDS-PROPCONSTRS" Name="selectio_lvds_tx_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="selectio_lvds_tx_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="selectio_lvds_tx_utilization_synth.pb"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/selectio_lvds_tx">
<File Path="$PPRDIR/../selectio_lvds_tx/selectio_lvds_tx.xci">
<File Path="$PPRDIR/../selectio_lvds_tx.xcix">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../selectio_lvds_tx.xcix">
<File Path="$PPRDIR/../selectio_lvds_tx/selectio_lvds_tx.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@@ -30,14 +30,14 @@
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/selectio_lvds_tx">
<File Path="$PPRDIR/../selectio_lvds_tx/selectio_lvds_tx.xci">
<File Path="$PPRDIR/../selectio_lvds_tx.xcix">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../selectio_lvds_tx.xcix">
<File Path="$PPRDIR/../selectio_lvds_tx/selectio_lvds_tx.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@@ -56,9 +56,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/project.wdf
+8 -8
View File
@@ -38,12 +38,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3432:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3432:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3432:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3432:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3432:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3432:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3432:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3664343331376333633832373434316539393231333933366261306366656163:506172656e742050412070726f6a656374204944:00
eof:4079222727
eof:4155969153
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds
+40 -40
View File
@@ -2,8 +2,8 @@
# Vivado v2019.1.3 (64-bit)
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
# Start of session at: Tue Mar 28 16:20:56 2023
# Process ID: 66769
# Start of session at: Wed Mar 29 15:36:39 2023
# Process ID: 50994
# Current directory: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1
# Command line: vivado -log selectio_lvds_tx.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl
# Log file: /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.vds
@@ -16,16 +16,16 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z045'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z045'
INFO: [Device 21-403] Loading part xc7z045ffg900-2
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 67008
INFO: Helper process launched with PID 51257
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1832.777 ; gain = 153.688 ; free physical = 5722 ; free virtual = 45010
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1834.125 ; gain = 151.688 ; free physical = 844 ; free virtual = 54763
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_tx' [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/selectio_lvds_tx/selectio_lvds_tx.v:58]
Parameter SYS_W bound to: 1 - type: integer
Parameter DEV_W bound to: 1 - type: integer
Parameter SYS_W bound to: 2 - type: integer
Parameter DEV_W bound to: 2 - type: integer
INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_tx_selectio_wiz' [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v:56]
Parameter SYS_W bound to: 1 - type: integer
Parameter DEV_W bound to: 1 - type: integer
Parameter SYS_W bound to: 2 - type: integer
Parameter DEV_W bound to: 2 - type: integer
INFO: [Synth 8-6157] synthesizing module 'OBUF' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:45998]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter DRIVE bound to: 12 - type: integer
@@ -52,7 +52,7 @@ INFO: [Synth 8-6155] done synthesizing module 'BUFR' (4#1) [/tools/Xilinx/Vivado
INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_tx_selectio_wiz' (5#1) [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/selectio_lvds_tx/selectio_lvds_tx_selectio_wiz.v:56]
INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_tx' (6#1) [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/selectio_lvds_tx/selectio_lvds_tx.v:58]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1889.496 ; gain = 210.406 ; free physical = 5162 ; free virtual = 44453
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1890.844 ; gain = 208.406 ; free physical = 867 ; free virtual = 54794
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -65,10 +65,10 @@ Report Check Netlist:
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1893.465 ; gain = 214.375 ; free physical = 5109 ; free virtual = 44402
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1893.812 ; gain = 211.375 ; free physical = 862 ; free virtual = 54791
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1893.465 ; gain = 214.375 ; free physical = 5109 ; free virtual = 44402
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1893.812 ; gain = 211.375 ; free physical = 862 ; free virtual = 54791
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
@@ -86,30 +86,30 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1995.152 ; gain = 0.000 ; free physical = 4491 ; free virtual = 43800
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2003.469 ; gain = 0.000 ; free physical = 775 ; free virtual = 54718
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2001.090 ; gain = 5.938 ; free physical = 4485 ; free virtual = 43794
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2009.406 ; gain = 5.938 ; free physical = 775 ; free virtual = 54718
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4667 ; free virtual = 43983
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 787 ; free virtual = 54758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z045ffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4666 ; free virtual = 43981
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 787 ; free virtual = 54758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4664 ; free virtual = 43980
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 787 ; free virtual = 54757
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4649 ; free virtual = 43966
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 773 ; free virtual = 54745
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -145,7 +145,7 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4619 ; free virtual = 43939
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 764 ; free virtual = 54742
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -157,13 +157,13 @@ Report RTL Partitions:
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4147 ; free virtual = 43490
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 610 ; free virtual = 54630
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4147 ; free virtual = 43490
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 610 ; free virtual = 54630
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -175,7 +175,7 @@ Report RTL Partitions:
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 4142 ; free virtual = 43484
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 609 ; free virtual = 54630
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -199,7 +199,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3949 ; free virtual = 43291
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 611 ; free virtual = 54640
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -212,7 +212,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3948 ; free virtual = 43291
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 611 ; free virtual = 54640
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -224,25 +224,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3948 ; free virtual = 43291
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 611 ; free virtual = 54640
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3948 ; free virtual = 43290
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 611 ; free virtual = 54640
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3948 ; free virtual = 43290
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 611 ; free virtual = 54640
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3948 ; free virtual = 43290
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 611 ; free virtual = 54640
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -259,46 +259,46 @@ Report Cell Usage:
| |Cell |Count |
+------+-----+------+
|1 |BUFR | 1|
|2 |FDRE | 1|
|2 |FDRE | 2|
|3 |IBUF | 1|
|4 |OBUF | 1|
|4 |OBUF | 2|
+------+-----+------+
Report Instance Areas:
+------+---------+------------------------------+------+
| |Instance |Module |Cells |
+------+---------+------------------------------+------+
|1 |top | | 4|
|2 | inst |selectio_lvds_tx_selectio_wiz | 4|
|1 |top | | 6|
|2 | inst |selectio_lvds_tx_selectio_wiz | 6|
+------+---------+------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3948 ; free virtual = 43291
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 611 ; free virtual = 54640
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2001.090 ; gain = 214.375 ; free physical = 3984 ; free virtual = 43327
Synthesis Optimization Complete : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2001.090 ; gain = 322.000 ; free physical = 3986 ; free virtual = 43329
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2009.406 ; gain = 211.375 ; free physical = 664 ; free virtual = 54693
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2009.406 ; gain = 326.969 ; free physical = 664 ; free virtual = 54693
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2007.832 ; gain = 0.000 ; free physical = 3732 ; free virtual = 43075
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2009.406 ; gain = 0.000 ; free physical = 613 ; free virtual = 54647
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2007.832 ; gain = 538.098 ; free physical = 3820 ; free virtual = 43163
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2007.832 ; gain = 0.000 ; free physical = 3820 ; free virtual = 43163
synth_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2009.406 ; gain = 614.426 ; free physical = 699 ; free virtual = 54734
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2009.406 ; gain = 0.000 ; free physical = 699 ; free virtual = 54734
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP selectio_lvds_tx, cache-ID = 8bb5b2cf5e761daa
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2007.832 ; gain = 0.000 ; free physical = 3987 ; free virtual = 43332
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP selectio_lvds_tx, cache-ID = 264e4d8f5de713c2
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2009.406 ; gain = 0.000 ; free physical = 695 ; free virtual = 54733
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Mar 28 16:21:23 2023...
INFO: [Common 17-206] Exiting Vivado at Wed Mar 29 15:36:55 2023...
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v
+37 -18
View File
@@ -1,7 +1,7 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Tue Mar 28 16:21:23 2023
// Date : Wed Mar 29 15:36:55 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v
@@ -12,7 +12,7 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* DEV_W = "1" *) (* SYS_W = "1" *)
(* DEV_W = "2" *) (* SYS_W = "2" *)
(* NotValidForBitStream *)
module selectio_lvds_tx
(data_out_from_device,
@@ -20,20 +20,20 @@ module selectio_lvds_tx
clk_in,
clk_out,
io_reset);
input [0:0]data_out_from_device;
output [0:0]data_out_to_pins;
input [1:0]data_out_from_device;
output [1:0]data_out_to_pins;
input clk_in;
output clk_out;
input io_reset;
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in;
wire clk_out;
wire [0:0]data_out_from_device;
(* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [0:0]data_out_to_pins;
wire [1:0]data_out_from_device;
(* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [1:0]data_out_to_pins;
wire io_reset;
(* DEV_W = "1" *)
(* SYS_W = "1" *)
(* DEV_W = "2" *)
(* SYS_W = "2" *)
selectio_lvds_tx_selectio_lvds_tx_selectio_wiz inst
(.clk_in(clk_in),
.clk_out(clk_out),
@@ -42,15 +42,15 @@ module selectio_lvds_tx
.io_reset(io_reset));
endmodule
(* DEV_W = "1" *) (* ORIG_REF_NAME = "selectio_lvds_tx_selectio_wiz" *) (* SYS_W = "1" *)
(* DEV_W = "2" *) (* ORIG_REF_NAME = "selectio_lvds_tx_selectio_wiz" *) (* SYS_W = "2" *)
module selectio_lvds_tx_selectio_lvds_tx_selectio_wiz
(data_out_from_device,
data_out_to_pins,
clk_in,
clk_out,
io_reset);
input [0:0]data_out_from_device;
output [0:0]data_out_to_pins;
input [1:0]data_out_from_device;
output [1:0]data_out_to_pins;
input clk_in;
output clk_out;
input io_reset;
@@ -58,10 +58,11 @@ module selectio_lvds_tx_selectio_lvds_tx_selectio_wiz
wire clk_in;
wire clk_in_int;
wire clk_out;
wire [0:0]data_out_from_device;
wire [0:0]data_out_to_pins;
wire data_out_to_pins_int;
wire [1:0]data_out_from_device;
wire [1:0]data_out_to_pins;
wire io_reset;
wire \pins[0].data_out_from_device_q ;
wire \pins[1].data_out_from_device_q ;
(* BOX_TYPE = "PRIMITIVE" *)
BUFR #(
@@ -89,14 +90,32 @@ module selectio_lvds_tx_selectio_lvds_tx_selectio_wiz
\pins[0].fdre_out_inst
(.C(clk_out),
.CE(1'b1),
.D(data_out_from_device),
.Q(data_out_to_pins_int),
.D(data_out_from_device[0]),
.Q(\pins[0].data_out_from_device_q ),
.R(io_reset));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
OBUF \pins[0].obuf_inst
(.I(data_out_to_pins_int),
.O(data_out_to_pins));
(.I(\pins[0].data_out_from_device_q ),
.O(data_out_to_pins[0]));
(* BOX_TYPE = "PRIMITIVE" *)
(* IOB = "TRUE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\pins[1].fdre_out_inst
(.C(clk_out),
.CE(1'b1),
.D(data_out_from_device[1]),
.Q(\pins[1].data_out_from_device_q ),
.R(io_reset));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
OBUF \pins[1].obuf_inst
(.I(\pins[1].data_out_from_device_q ),
.O(data_out_to_pins[1]));
endmodule
`ifndef GLBL
`define GLBL
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl
+40 -16
View File
@@ -1,7 +1,7 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Tue Mar 28 16:21:23 2023
-- Date : Wed Mar 29 15:36:55 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl
@@ -16,24 +16,25 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is
port (
data_out_from_device : in STD_LOGIC_VECTOR ( 0 to 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 0 to 0 );
data_out_from_device : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
io_reset : in STD_LOGIC
);
attribute DEV_W : integer;
attribute DEV_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 1;
attribute DEV_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is "selectio_lvds_tx_selectio_wiz";
attribute SYS_W : integer;
attribute SYS_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 1;
attribute SYS_W of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz : entity is 2;
end selectio_lvds_tx_selectio_lvds_tx_selectio_wiz;
architecture STRUCTURE of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is
signal clk_in_int : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal data_out_to_pins_int : STD_LOGIC;
signal \pins[0].data_out_from_device_q\ : STD_LOGIC;
signal \pins[1].data_out_from_device_q\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE";
attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE";
@@ -48,6 +49,10 @@ architecture STRUCTURE of selectio_lvds_tx_selectio_lvds_tx_selectio_wiz is
attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE";
attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE";
attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE";
attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE";
attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE";
attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE";
attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE";
begin
clk_out <= \^clk_out\;
clkout_buf_inst: unisim.vcomponents.BUFR
@@ -77,14 +82,33 @@ ibuf_clk_inst: unisim.vcomponents.IBUF
C => \^clk_out\,
CE => '1',
D => data_out_from_device(0),
Q => data_out_to_pins_int,
Q => \pins[0].data_out_from_device_q\,
R => io_reset
);
\pins[0].obuf_inst\: unisim.vcomponents.OBUF
port map (
I => data_out_to_pins_int,
I => \pins[0].data_out_from_device_q\,
O => data_out_to_pins(0)
);
\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => \^clk_out\,
CE => '1',
D => data_out_from_device(1),
Q => \pins[1].data_out_from_device_q\,
R => io_reset
);
\pins[1].obuf_inst\: unisim.vcomponents.OBUF
port map (
I => \pins[1].data_out_from_device_q\,
O => data_out_to_pins(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -92,8 +116,8 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity selectio_lvds_tx is
port (
data_out_from_device : in STD_LOGIC_VECTOR ( 0 to 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 0 to 0 );
data_out_from_device : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
io_reset : in STD_LOGIC
@@ -101,21 +125,21 @@ entity selectio_lvds_tx is
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of selectio_lvds_tx : entity is true;
attribute DEV_W : integer;
attribute DEV_W of selectio_lvds_tx : entity is 1;
attribute DEV_W of selectio_lvds_tx : entity is 2;
attribute SYS_W : integer;
attribute SYS_W of selectio_lvds_tx : entity is 1;
attribute SYS_W of selectio_lvds_tx : entity is 2;
end selectio_lvds_tx;
architecture STRUCTURE of selectio_lvds_tx is
attribute DEV_W of inst : label is 1;
attribute SYS_W of inst : label is 1;
attribute DEV_W of inst : label is 2;
attribute SYS_W of inst : label is 2;
begin
inst: entity work.selectio_lvds_tx_selectio_lvds_tx_selectio_wiz
port map (
clk_in => clk_in,
clk_out => clk_out,
data_out_from_device(0) => data_out_from_device(0),
data_out_to_pins(0) => data_out_to_pins(0),
data_out_from_device(1 downto 0) => data_out_from_device(1 downto 0),
data_out_to_pins(1 downto 0) => data_out_to_pins(1 downto 0),
io_reset => io_reset
);
end STRUCTURE;
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v
+4 -4
View File
@@ -1,7 +1,7 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Tue Mar 28 16:21:23 2023
// Date : Wed Mar 29 15:36:55 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v
@@ -15,9 +15,9 @@
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module selectio_lvds_tx(data_out_from_device, data_out_to_pins,
clk_in, clk_out, io_reset)
/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[0:0],data_out_to_pins[0:0],clk_in,clk_out,io_reset" */;
input [0:0]data_out_from_device;
output [0:0]data_out_to_pins;
/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[1:0],data_out_to_pins[1:0],clk_in,clk_out,io_reset" */;
input [1:0]data_out_from_device;
output [1:0]data_out_to_pins;
input clk_in;
output clk_out;
input io_reset;
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl
+4 -4
View File
@@ -1,7 +1,7 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Tue Mar 28 16:21:23 2023
-- Date : Wed Mar 29 15:36:55 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl
@@ -14,8 +14,8 @@ use IEEE.STD_LOGIC_1164.ALL;
entity selectio_lvds_tx is
Port (
data_out_from_device : in STD_LOGIC_VECTOR ( 0 to 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 0 to 0 );
data_out_from_device : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_out_to_pins : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
io_reset : in STD_LOGIC
@@ -27,6 +27,6 @@ architecture stub of selectio_lvds_tx is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "data_out_from_device[0:0],data_out_to_pins[0:0],clk_in,clk_out,io_reset";
attribute black_box_pad_pin of stub : architecture is "data_out_from_device[1:0],data_out_to_pins[1:0],clk_in,clk_out,io_reset";
begin
end;
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.pb
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_utilization_synth.rpt
+7 -7
View File
@@ -1,7 +1,7 @@
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
| Date : Tue Mar 28 16:21:23 2023
| Date : Wed Mar 29 15:36:55 2023
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
| Command : report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb
| Design : selectio_lvds_tx
@@ -33,8 +33,8 @@ Table of Contents
| Slice LUTs* | 0 | 0 | 218600 | 0.00 |
| LUT as Logic | 0 | 0 | 218600 | 0.00 |
| LUT as Memory | 0 | 0 | 70400 | 0.00 |
| Slice Registers | 1 | 1 | 437200 | <0.01 |
| Register as Flip Flop | 1 | 1 | 437200 | <0.01 |
| Slice Registers | 2 | 2 | 437200 | <0.01 |
| Register as Flip Flop | 2 | 2 | 437200 | <0.01 |
| Register as Latch | 0 | 0 | 437200 | 0.00 |
| F7 Muxes | 0 | 0 | 109300 | 0.00 |
| F8 Muxes | 0 | 0 | 54650 | 0.00 |
@@ -57,7 +57,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 1 | Yes | Reset | - |
| 2 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -90,7 +90,7 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 2 | 0 | 362 | 0.55 |
| Bonded IOB | 3 | 0 | 362 | 0.83 |
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
@@ -152,9 +152,9 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| OBUF | 1 | IO |
| OBUF | 2 | IO |
| FDRE | 2 | Flop & Latch |
| IBUF | 1 | IO |
| FDRE | 1 | Flop & Latch |
| BUFR | 1 | Clock |
+----------+------+---------------------+
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/vivado.pb
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_z7/ip/managed_ip_project/managed_ip_project.xpr
+46 -121
View File
@@ -39,13 +39,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="42"/>
<Option Name="WTModelSimExportSim" Val="42"/>
<Option Name="WTQuestaExportSim" Val="42"/>
<Option Name="WTIesExportSim" Val="42"/>
<Option Name="WTVcsExportSim" Val="42"/>
<Option Name="WTRivieraExportSim" Val="42"/>
<Option Name="WTActivehdlExportSim" Val="42"/>
<Option Name="WTXSimExportSim" Val="43"/>
<Option Name="WTModelSimExportSim" Val="43"/>
<Option Name="WTQuestaExportSim" Val="43"/>
<Option Name="WTIesExportSim" Val="43"/>
<Option Name="WTVcsExportSim" Val="43"/>
<Option Name="WTRivieraExportSim" Val="43"/>
<Option Name="WTActivehdlExportSim" Val="43"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -72,6 +72,7 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
@@ -474,9 +475,7 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
@@ -484,9 +483,7 @@
</Run>
<Run Id="c2c_rx_ila_synth_1" Type="Ft3:Synth" SrcSet="c2c_rx_ila" Part="xc7z045ffg900-2" ConstrsSet="c2c_rx_ila" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/c2c_rx_ila_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -495,9 +492,7 @@
</Run>
<Run Id="c2c_tx_ila_synth_1" Type="Ft3:Synth" SrcSet="c2c_tx_ila" Part="xc7z045ffg900-2" ConstrsSet="c2c_tx_ila" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/c2c_tx_ila_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -506,9 +501,7 @@
</Run>
<Run Id="clk_wiz_25m_1to3_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_25m_1to3" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_25m_1to3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_25m_1to3_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -517,9 +510,7 @@
</Run>
<Run Id="clk_wiz_96m_1to1_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_96m_1to1" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_96m_1to1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_96m_1to1_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -528,9 +519,7 @@
</Run>
<Run Id="clk_wiz_beam_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_beam" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_beam" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_beam_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -539,9 +528,7 @@
</Run>
<Run Id="clk_wiz_glink_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_glink" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_glink" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_glink_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -550,9 +537,7 @@
</Run>
<Run Id="clk_wiz_lvds_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_lvds" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_lvds" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_lvds_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -561,9 +546,7 @@
</Run>
<Run Id="fifo_en_creat_synth_1" Type="Ft3:Synth" SrcSet="fifo_en_creat" Part="xc7z045ffg900-2" ConstrsSet="fifo_en_creat" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_en_creat_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -572,9 +555,7 @@
</Run>
<Run Id="ila_beam_synth_1" Type="Ft3:Synth" SrcSet="ila_beam" Part="xc7z045ffg900-2" ConstrsSet="ila_beam" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_beam_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -583,9 +564,7 @@
</Run>
<Run Id="ila_c2c_dma_rx_synth_1" Type="Ft3:Synth" SrcSet="ila_c2c_dma_rx" Part="xc7z045ffg900-2" ConstrsSet="ila_c2c_dma_rx" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_c2c_dma_rx_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -594,9 +573,7 @@
</Run>
<Run Id="ila_c2c_dma_tx_synth_1" Type="Ft3:Synth" SrcSet="ila_c2c_dma_tx" Part="xc7z045ffg900-2" ConstrsSet="ila_c2c_dma_tx" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_c2c_dma_tx_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -605,9 +582,7 @@
</Run>
<Run Id="ila_dma_fifo_synth_1" Type="Ft3:Synth" SrcSet="ila_dma_fifo" Part="xc7z045ffg900-2" ConstrsSet="ila_dma_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_dma_fifo_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -616,9 +591,7 @@
</Run>
<Run Id="ila_en_creat_in_synth_1" Type="Ft3:Synth" SrcSet="ila_en_creat_in" Part="xc7z045ffg900-2" ConstrsSet="ila_en_creat_in" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_en_creat_in_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -627,9 +600,7 @@
</Run>
<Run Id="ila_en_creat_out_synth_1" Type="Ft3:Synth" SrcSet="ila_en_creat_out" Part="xc7z045ffg900-2" ConstrsSet="ila_en_creat_out" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_en_creat_out_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -638,9 +609,7 @@
</Run>
<Run Id="ila_glink_synth_1" Type="Ft3:Synth" SrcSet="ila_glink" Part="xc7z045ffg900-2" ConstrsSet="ila_glink" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_glink_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -649,9 +618,7 @@
</Run>
<Run Id="ila_glink_2_synth_1" Type="Ft3:Synth" SrcSet="ila_glink_2" Part="xc7z045ffg900-2" ConstrsSet="ila_glink_2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_glink_2_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -660,9 +627,7 @@
</Run>
<Run Id="selectio_lvds_rx_synth_1" Type="Ft3:Synth" SrcSet="selectio_lvds_rx" Part="xc7z045ffg900-2" ConstrsSet="selectio_lvds_rx" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/selectio_lvds_rx_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -671,9 +636,7 @@
</Run>
<Run Id="selectio_lvds_tx_synth_1" Type="Ft3:Synth" SrcSet="selectio_lvds_tx" Part="xc7z045ffg900-2" ConstrsSet="selectio_lvds_tx" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/selectio_lvds_tx_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -682,9 +645,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -700,9 +661,7 @@
</Run>
<Run Id="c2c_rx_ila_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="c2c_rx_ila" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="c2c_rx_ila_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -718,9 +677,7 @@
</Run>
<Run Id="c2c_tx_ila_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="c2c_tx_ila" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="c2c_tx_ila_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -736,9 +693,7 @@
</Run>
<Run Id="clk_wiz_25m_1to3_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_25m_1to3" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_25m_1to3_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -754,9 +709,7 @@
</Run>
<Run Id="clk_wiz_96m_1to1_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_96m_1to1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_96m_1to1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -772,9 +725,7 @@
</Run>
<Run Id="clk_wiz_beam_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_beam" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_beam_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -790,9 +741,7 @@
</Run>
<Run Id="clk_wiz_glink_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_glink" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_glink_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -808,9 +757,7 @@
</Run>
<Run Id="clk_wiz_lvds_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="clk_wiz_lvds" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_lvds_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -826,9 +773,7 @@
</Run>
<Run Id="fifo_en_creat_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="fifo_en_creat" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_en_creat_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -844,9 +789,7 @@
</Run>
<Run Id="ila_beam_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_beam" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_beam_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -862,9 +805,7 @@
</Run>
<Run Id="ila_c2c_dma_rx_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_c2c_dma_rx" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_c2c_dma_rx_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -880,9 +821,7 @@
</Run>
<Run Id="ila_c2c_dma_tx_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_c2c_dma_tx" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_c2c_dma_tx_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -898,9 +837,7 @@
</Run>
<Run Id="ila_dma_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_dma_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_dma_fifo_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -916,9 +853,7 @@
</Run>
<Run Id="ila_en_creat_in_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_en_creat_in" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_en_creat_in_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -934,9 +869,7 @@
</Run>
<Run Id="ila_en_creat_out_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_en_creat_out" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_en_creat_out_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -952,9 +885,7 @@
</Run>
<Run Id="ila_glink_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_glink" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_glink_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -970,9 +901,7 @@
</Run>
<Run Id="ila_glink_2_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_glink_2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_glink_2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -988,9 +917,7 @@
</Run>
<Run Id="selectio_lvds_rx_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="selectio_lvds_rx" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="selectio_lvds_rx_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -1006,9 +933,7 @@
</Run>
<Run Id="selectio_lvds_tx_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="selectio_lvds_tx" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="selectio_lvds_tx_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>