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add dl814_k7_basic; update dl814_z7 ps project

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dl814_k7_basic is the driver instance of board smq7k410t_b9361, along with basic clock, adc and dac configurations; include nulling algorithm into dl814_z7 project
This commit is contained in:
josh
2023-03-29 17:34:49 +08:00
parent cd256a8cd6
commit e8a34c95e0
2060 changed files with 4678610 additions and 198681 deletions
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projects/datalink_814/dl814_k7_basic/.gitignore
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################################################################################
########################### Single Project Specific ############################
################################################################################
# ------------------------------------------------------------------------------
# ------------------------------ Vivado Specific -------------------------------
# ------------------------------------------------------------------------------
# exclude everything in project directory
project/**
# include hardware manager projects and sources
# 1. include `.hw` directory
# 2. include everything in `.hw` directory
!project/*.hw/
!project/*.hw/**
# include design run results
# 1. include `*.runs` directory
# 2. exclude everything in `.runs` directory
# 3. include `.impl_*` directory
# 4. include `*.bit` file in `.impl_*` directory
# 5. include `*.ltx` file in `.impl_*` directory
!/project/*.runs/
/project/*.runs/**
!/project/*.runs/impl_*/
!/project/*.runs/impl_*/*.bit
!/project/*.runs/impl_*/*.ltx
# ------------------------------------------------------------------------------
# -------------------------------- SDK Specific --------------------------------
# ------------------------------------------------------------------------------
# include sdk directory and everything in it
!/project/*.sdk/
!/project/*.sdk/**
/project/*.sdk/**.log
# exclude some obscure hidden SDK folders
/project/*.sdk/.metadata/
/project/*.sdk/.sdk/
/project/*.sdk/RemoteSystemsTempFiles/
/project/*.sdk/webtalk/
# hw_platform: exclude the entire hw_platform folder, as everything can be
# generated from the .hdf file. Make sure to include the bitstream in the .hdf
# file when exporting from Vivado!
/project/*.sdk/*_hw_platform_*/
# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
# Makefile, ps lib files are regenerated automatically
/project/*.sdk/*_bsp/*
!/project/*.sdk/*_bsp/*.cproject
!/project/*.sdk/*_bsp/*.project
!/project/*.sdk/*_bsp/*.sdkproject
!/project/*.sdk/*_bsp/system.mss
!/project/*.sdk/*_bsp/Makefile
# Application: ignored file patterns, exclude Debug & Release folders
/project/*.sdk/**/*.o
/project/*.sdk/**/*.d
/project/*.sdk/**/*.a
/project/*.sdk/*/Debug/
/project/*.sdk/*/Release/
################################################################################
# ############################ Multi Project Specific ############################
# ################################################################################
# # ------------------------------------------------------------------------------
# # ------------------------------ Vivado Specific -------------------------------
# # ------------------------------------------------------------------------------
# # exclude everything in project directory expect for top level directory
# project/**
# !/project/*/
# # include hardware manager projects and sources
# # 1. include `.hw` directory
# # 2. include everything in `.hw` directory
# !project/*/*.hw/
# !project/*/*.hw/**
# # include design run results
# # 1. include `*.runs` directory
# # 2. exclude everything in `.runs` directory
# # 3. include `.impl_*` directory
# # 4. include `*.bit` file in `.impl_*` directory
# # 5. include `*.ltx` file in `.impl_*` directory
# !/project/*/*.runs/
# /project/*/*.runs/**
# !/project/*/*.runs/impl_*/
# !/project/*/*.runs/impl_*/*.bit
# !/project/*/*.runs/impl_*/*.ltx
# # ------------------------------------------------------------------------------
# # -------------------------------- SDK Specific --------------------------------
# # ------------------------------------------------------------------------------
# # include sdk directory and everything in it
# !/project/*/*.sdk/
# !/project/*/*.sdk/**
# /project/*/*.sdk/**.log
# # exclude some obscure hidden SDK folders
# /project/*/*.sdk/.metadata/
# /project/*/*.sdk/.sdk/
# /project/*/*.sdk/RemoteSystemsTempFiles/
# /project/*/*.sdk/webtalk/
# # hw_platform: exclude the entire hw_platform folder, as everything can be
# # generated from the .hdf file. Make sure to include the bitstream in the .hdf
# # file when exporting from Vivado!
# /project/*/*.sdk/*_hw_platform_*/
# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
# # Makefile, ps lib files are regenerated automatically
# /project/*/*.sdk/*_bsp/*
# !/project/*/*.sdk/*_bsp/*.cproject
# !/project/*/*.sdk/*_bsp/*.project
# !/project/*/*.sdk/*_bsp/*.sdkproject
# !/project/*/*.sdk/*_bsp/system.mss
# !/project/*/*.sdk/*_bsp/Makefile
# # Application: ignored file patterns, exclude Debug & Release folders
# /project/*/*.sdk/**/*.o
# /project/*/*.sdk/**/*.d
# /project/*/*.sdk/**/*.a
# /project/*/*.sdk/*/Debug/
# /project/*/*.sdk/*/Release/
projects/datalink_814/dl814_k7_basic/constraints/k7401t_ad9516_2ad9361_physical.xdc
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# smq7k410t_b9361
## Timing Assertions Section
## Physical Constraints Section
# Clocks
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P
set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT
# HMC7044-1 Interface
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO
set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO
set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON
set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB
# AD9361-1 Interface
set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK
set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N
set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N
set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P
set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N
set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P
set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N
set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P
set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N
set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P
set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N
set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P
set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK
set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME
set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N
set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P
set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N
set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P
set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N
set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P
set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N
set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P
set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N
set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P
set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE
set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3
set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC
# AD9361-2 Interface
set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N
set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N
set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7
# Phased-Array Control
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN
# RF Synthesizer Control
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1
set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3
set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX
# LVDS for Time Synchronization
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2
# Debug IO
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P
# FLASH
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
projects/datalink_814/dl814_k7_basic/constraints/k7410t_ad9516_2ad9361_timing.xdc
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen.v
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// file: ad9361_clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____48.000______0.000______50.0______139.139_____89.958
// clk_out2____96.000______0.000______50.0______120.859_____89.958
// clk_out3___144.000______0.000______50.0______112.241_____89.958
// clk_out4___192.000______0.000______50.0______106.524_____89.958
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ad9361_clk_gen,clk_wiz_v6_0_3_0_0,{component_name=ad9361_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.417,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ad9361_clk_gen
(
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
output locked,
// Clock in ports
input clk_in1
);
ad9361_clk_gen_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4),
// Status and control signals
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen.veo
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//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____48.000______0.000______50.0______139.139_____89.958
// clk_out2____96.000______0.000______50.0______120.859_____89.958
// clk_out3___144.000______0.000______50.0______112.241_____89.958
// clk_out4___192.000______0.000______50.0______106.524_____89.958
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ad9361_clk_gen instance_name
(
// Clock out ports
.clk_out1(clk_out1), // output clk_out1
.clk_out2(clk_out2), // output clk_out2
.clk_out3(clk_out3), // output clk_out3
.clk_out4(clk_out4), // output clk_out4
// Status and control signals
.locked(locked), // output locked
// Clock in ports
.clk_in1(clk_in1)); // input clk_in1
// INST_TAG_END ------ End INSTANTIATION Template ---------
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v
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// file: ad9361_clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____48.000______0.000______50.0______139.139_____89.958
// clk_out2____96.000______0.000______50.0______120.859_____89.958
// clk_out3___144.000______0.000______50.0______112.241_____89.958
// clk_out4___192.000______0.000______50.0______106.524_____89.958
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
`timescale 1ps/1ps
module ad9361_clk_gen_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_ad9361_clk_gen;
wire clk_in2_ad9361_clk_gen;
IBUF clkin1_ibufg
(.O (clk_in1_ad9361_clk_gen),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_ad9361_clk_gen;
wire clk_out2_ad9361_clk_gen;
wire clk_out3_ad9361_clk_gen;
wire clk_out4_ad9361_clk_gen;
wire clk_out5_ad9361_clk_gen;
wire clk_out6_ad9361_clk_gen;
wire clk_out7_ad9361_clk_gen;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_ad9361_clk_gen;
wire clkfbout_buf_ad9361_clk_gen;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (12.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (24.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (12),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (8),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (6),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.417))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_ad9361_clk_gen),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_ad9361_clk_gen),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_ad9361_clk_gen),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_out3_ad9361_clk_gen),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clk_out4_ad9361_clk_gen),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_ad9361_clk_gen),
.CLKIN1 (clk_in1_ad9361_clk_gen),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_ad9361_clk_gen),
.I (clkfbout_ad9361_clk_gen));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_ad9361_clk_gen));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_ad9361_clk_gen));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_ad9361_clk_gen));
BUFG clkout4_buf
(.O (clk_out4),
.I (clk_out4_ad9361_clk_gen));
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_sim_netlist.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top ad9361_clk_gen -prefix
// ad9361_clk_gen_ ad9361_clk_gen_sim_netlist.v
// Design : ad9361_clk_gen
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module ad9361_clk_gen
(clk_out1,
clk_out2,
clk_out3,
clk_out4,
locked,
clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire clk_out2;
wire clk_out3;
wire clk_out4;
wire locked;
ad9361_clk_gen_ad9361_clk_gen_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4),
.locked(locked));
endmodule
module ad9361_clk_gen_ad9361_clk_gen_clk_wiz
(clk_out1,
clk_out2,
clk_out3,
clk_out4,
locked,
clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_ad9361_clk_gen;
wire clk_out1;
wire clk_out1_ad9361_clk_gen;
wire clk_out2;
wire clk_out2_ad9361_clk_gen;
wire clk_out3;
wire clk_out3_ad9361_clk_gen;
wire clk_out4;
wire clk_out4_ad9361_clk_gen;
wire clkfbout_ad9361_clk_gen;
wire clkfbout_buf_ad9361_clk_gen;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ad9361_clk_gen),
.O(clkfbout_buf_ad9361_clk_gen));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_ad9361_clk_gen));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_ad9361_clk_gen),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_out2_ad9361_clk_gen),
.O(clk_out2));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(clk_out3_ad9361_clk_gen),
.O(clk_out3));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout4_buf
(.I(clk_out4_ad9361_clk_gen),
.O(clk_out4));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(12.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.417000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(24.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(12),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(8),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(6),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ad9361_clk_gen),
.CLKFBOUT(clkfbout_ad9361_clk_gen),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_ad9361_clk_gen),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_ad9361_clk_gen),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_out2_ad9361_clk_gen),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(clk_out3_ad9361_clk_gen),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(clk_out4_ad9361_clk_gen),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_sim_netlist.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top ad9361_clk_gen -prefix
-- ad9361_clk_gen_ ad9361_clk_gen_sim_netlist.vhdl
-- Design : ad9361_clk_gen
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ad9361_clk_gen_ad9361_clk_gen_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end ad9361_clk_gen_ad9361_clk_gen_clk_wiz;
architecture STRUCTURE of ad9361_clk_gen_ad9361_clk_gen_clk_wiz is
signal clk_in1_ad9361_clk_gen : STD_LOGIC;
signal clk_out1_ad9361_clk_gen : STD_LOGIC;
signal clk_out2_ad9361_clk_gen : STD_LOGIC;
signal clk_out3_ad9361_clk_gen : STD_LOGIC;
signal clk_out4_ad9361_clk_gen : STD_LOGIC;
signal clkfbout_ad9361_clk_gen : STD_LOGIC;
signal clkfbout_buf_ad9361_clk_gen : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ad9361_clk_gen,
O => clkfbout_buf_ad9361_clk_gen
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_ad9361_clk_gen
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_ad9361_clk_gen,
O => clk_out1
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_out2_ad9361_clk_gen,
O => clk_out2
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk_out3_ad9361_clk_gen,
O => clk_out3
);
clkout4_buf: unisim.vcomponents.BUFG
port map (
I => clk_out4_ad9361_clk_gen,
O => clk_out4
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 12.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.417000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 24.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 12,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 8,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 6,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ad9361_clk_gen,
CLKFBOUT => clkfbout_ad9361_clk_gen,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_ad9361_clk_gen,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_ad9361_clk_gen,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_out2_ad9361_clk_gen,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk_out3_ad9361_clk_gen,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => clk_out4_ad9361_clk_gen,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ad9361_clk_gen is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ad9361_clk_gen : entity is true;
end ad9361_clk_gen;
architecture STRUCTURE of ad9361_clk_gen is
begin
inst: entity work.ad9361_clk_gen_ad9361_clk_gen_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
clk_out2 => clk_out2,
clk_out3 => clk_out3,
clk_out4 => clk_out4,
locked => locked
);
end STRUCTURE;
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top ad9361_clk_gen -prefix
// ad9361_clk_gen_ ad9361_clk_gen_stub.v
// Design : ad9361_clk_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ad9361_clk_gen(clk_out1, clk_out2, clk_out3, clk_out4, locked,
clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top ad9361_clk_gen -prefix
-- ad9361_clk_gen_ ad9361_clk_gen_stub.vhdl
-- Design : ad9361_clk_gen
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ad9361_clk_gen is
Port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end ad9361_clk_gen;
architecture stub of ad9361_clk_gen is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
begin
end;
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.v
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// file: ant_clk_gen_stg1.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____96.000______0.000______50.0______168.397____161.614
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________250____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ant_clk_gen_stg1,clk_wiz_v6_0_3_0_0,{component_name=ant_clk_gen_stg1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ant_clk_gen_stg1
(
// Clock out ports
output clk_out1,
// Status and control signals
output locked,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
ant_clk_gen_stg1_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.locked(locked),
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n)
);
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.veo
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//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____96.000______0.000______50.0______168.397____161.614
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________250____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ant_clk_gen_stg1 instance_name
(
// Clock out ports
.clk_out1(clk_out1), // output clk_out1
// Status and control signals
.locked(locked), // output locked
// Clock in ports
.clk_in1_p(clk_in1_p), // input clk_in1_p
.clk_in1_n(clk_in1_n)); // input clk_in1_n
// INST_TAG_END ------ End INSTANTIATION Template ---------
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1_clk_wiz.v
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// file: ant_clk_gen_stg1.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____96.000______0.000______50.0______168.397____161.614
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________250____________0.010
`timescale 1ps/1ps
module ant_clk_gen_stg1_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
output locked,
input clk_in1_p,
input clk_in1_n
);
// Input buffering
//------------------------------------
wire clk_in1_ant_clk_gen_stg1;
wire clk_in2_ant_clk_gen_stg1;
IBUFDS clkin1_ibufgds
(.O (clk_in1_ant_clk_gen_stg1),
.I (clk_in1_p),
.IB (clk_in1_n));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_ant_clk_gen_stg1;
wire clk_out2_ant_clk_gen_stg1;
wire clk_out3_ant_clk_gen_stg1;
wire clk_out4_ant_clk_gen_stg1;
wire clk_out5_ant_clk_gen_stg1;
wire clk_out6_ant_clk_gen_stg1;
wire clk_out7_ant_clk_gen_stg1;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_ant_clk_gen_stg1;
wire clkfbout_buf_ant_clk_gen_stg1;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (18.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (9.375),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (4.000))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_ant_clk_gen_stg1),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_ant_clk_gen_stg1),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_ant_clk_gen_stg1),
.CLKIN1 (clk_in1_ant_clk_gen_stg1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_ant_clk_gen_stg1),
.I (clkfbout_ant_clk_gen_stg1));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_ant_clk_gen_stg1));
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1_sim_netlist.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top ant_clk_gen_stg1 -prefix
// ant_clk_gen_stg1_ ant_clk_gen_stg1_sim_netlist.v
// Design : ant_clk_gen_stg1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module ant_clk_gen_stg1
(clk_out1,
locked,
clk_in1_p,
clk_in1_n);
output clk_out1;
output locked;
input clk_in1_p;
input clk_in1_n;
(* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
(* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
wire clk_out1;
wire locked;
ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz inst
(.clk_in1_n(clk_in1_n),
.clk_in1_p(clk_in1_p),
.clk_out1(clk_out1),
.locked(locked));
endmodule
module ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz
(clk_out1,
locked,
clk_in1_p,
clk_in1_n);
output clk_out1;
output locked;
input clk_in1_p;
input clk_in1_n;
wire clk_in1_ant_clk_gen_stg1;
wire clk_in1_n;
wire clk_in1_p;
wire clk_out1;
wire clk_out1_ant_clk_gen_stg1;
wire clkfbout_ant_clk_gen_stg1;
wire clkfbout_buf_ant_clk_gen_stg1;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ant_clk_gen_stg1),
.O(clkfbout_buf_ant_clk_gen_stg1));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUFDS #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufgds
(.I(clk_in1_p),
.IB(clk_in1_n),
.O(clk_in1_ant_clk_gen_stg1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_ant_clk_gen_stg1),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(18.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(4.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(9.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ant_clk_gen_stg1),
.CLKFBOUT(clkfbout_ant_clk_gen_stg1),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_ant_clk_gen_stg1),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_ant_clk_gen_stg1),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1_sim_netlist.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top ant_clk_gen_stg1 -prefix
-- ant_clk_gen_stg1_ ant_clk_gen_stg1_sim_netlist.vhdl
-- Design : ant_clk_gen_stg1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1_p : in STD_LOGIC;
clk_in1_n : in STD_LOGIC
);
end ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz;
architecture STRUCTURE of ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz is
signal clk_in1_ant_clk_gen_stg1 : STD_LOGIC;
signal clk_out1_ant_clk_gen_stg1 : STD_LOGIC;
signal clkfbout_ant_clk_gen_stg1 : STD_LOGIC;
signal clkfbout_buf_ant_clk_gen_stg1 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ant_clk_gen_stg1,
O => clkfbout_buf_ant_clk_gen_stg1
);
clkin1_ibufgds: unisim.vcomponents.IBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1_p,
IB => clk_in1_n,
O => clk_in1_ant_clk_gen_stg1
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_ant_clk_gen_stg1,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 18.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 4.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 9.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ant_clk_gen_stg1,
CLKFBOUT => clkfbout_ant_clk_gen_stg1,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_ant_clk_gen_stg1,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_ant_clk_gen_stg1,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ant_clk_gen_stg1 is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1_p : in STD_LOGIC;
clk_in1_n : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ant_clk_gen_stg1 : entity is true;
end ant_clk_gen_stg1;
architecture STRUCTURE of ant_clk_gen_stg1 is
begin
inst: entity work.ant_clk_gen_stg1_ant_clk_gen_stg1_clk_wiz
port map (
clk_in1_n => clk_in1_n,
clk_in1_p => clk_in1_p,
clk_out1 => clk_out1,
locked => locked
);
end STRUCTURE;
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top ant_clk_gen_stg1 -prefix
// ant_clk_gen_stg1_ ant_clk_gen_stg1_stub.v
// Design : ant_clk_gen_stg1
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ant_clk_gen_stg1(clk_out1, locked, clk_in1_p, clk_in1_n)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */;
output clk_out1;
output locked;
input clk_in1_p;
input clk_in1_n;
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top ant_clk_gen_stg1 -prefix
-- ant_clk_gen_stg1_ ant_clk_gen_stg1_stub.vhdl
-- Design : ant_clk_gen_stg1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ant_clk_gen_stg1 is
Port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1_p : in STD_LOGIC;
clk_in1_n : in STD_LOGIC
);
end ant_clk_gen_stg1;
architecture stub of ant_clk_gen_stg1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n";
begin
end;
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.v
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// file: ant_clk_gen_stg2.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____96.000______0.000______50.0______136.435____101.715
// clk_out2____48.000______0.000______50.0______158.351____101.715
// clk_out3____32.000______0.000______50.0______172.426____101.715
// clk_out4____19.200______0.000______50.0______190.665____101.715
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ant_clk_gen_stg2,clk_wiz_v6_0_3_0_0,{component_name=ant_clk_gen_stg2,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.417,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ant_clk_gen_stg2
(
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
output locked,
// Clock in ports
input clk_in1
);
ant_clk_gen_stg2_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4),
// Status and control signals
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.veo
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//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____96.000______0.000______50.0______136.435____101.715
// clk_out2____48.000______0.000______50.0______158.351____101.715
// clk_out3____32.000______0.000______50.0______172.426____101.715
// clk_out4____19.200______0.000______50.0______190.665____101.715
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ant_clk_gen_stg2 instance_name
(
// Clock out ports
.clk_out1(clk_out1), // output clk_out1
.clk_out2(clk_out2), // output clk_out2
.clk_out3(clk_out3), // output clk_out3
.clk_out4(clk_out4), // output clk_out4
// Status and control signals
.locked(locked), // output locked
// Clock in ports
.clk_in1(clk_in1)); // input clk_in1
// INST_TAG_END ------ End INSTANTIATION Template ---------
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg2/ant_clk_gen_stg2_clk_wiz.v
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// file: ant_clk_gen_stg2.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____96.000______0.000______50.0______136.435____101.715
// clk_out2____48.000______0.000______50.0______158.351____101.715
// clk_out3____32.000______0.000______50.0______172.426____101.715
// clk_out4____19.200______0.000______50.0______190.665____101.715
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
`timescale 1ps/1ps
module ant_clk_gen_stg2_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_ant_clk_gen_stg2;
wire clk_in2_ant_clk_gen_stg2;
BUFG clkin1_bufg
(.O (clk_in1_ant_clk_gen_stg2),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_ant_clk_gen_stg2;
wire clk_out2_ant_clk_gen_stg2;
wire clk_out3_ant_clk_gen_stg2;
wire clk_out4_ant_clk_gen_stg2;
wire clk_out5_ant_clk_gen_stg2;
wire clk_out6_ant_clk_gen_stg2;
wire clk_out7_ant_clk_gen_stg2;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_ant_clk_gen_stg2;
wire clkfbout_buf_ant_clk_gen_stg2;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (20),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (30),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (50),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.417))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_ant_clk_gen_stg2),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_ant_clk_gen_stg2),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_ant_clk_gen_stg2),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_out3_ant_clk_gen_stg2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clk_out4_ant_clk_gen_stg2),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_ant_clk_gen_stg2),
.CLKIN1 (clk_in1_ant_clk_gen_stg2),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_ant_clk_gen_stg2),
.I (clkfbout_ant_clk_gen_stg2));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_ant_clk_gen_stg2));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_ant_clk_gen_stg2));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_ant_clk_gen_stg2));
BUFG clkout4_buf
(.O (clk_out4),
.I (clk_out4_ant_clk_gen_stg2));
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg2/ant_clk_gen_stg2_sim_netlist.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top ant_clk_gen_stg2 -prefix
// ant_clk_gen_stg2_ ant_clk_gen_stg2_sim_netlist.v
// Design : ant_clk_gen_stg2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module ant_clk_gen_stg2
(clk_out1,
clk_out2,
clk_out3,
clk_out4,
locked,
clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
wire clk_in1;
wire clk_out1;
wire clk_out2;
wire clk_out3;
wire clk_out4;
wire locked;
ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4),
.locked(locked));
endmodule
module ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz
(clk_out1,
clk_out2,
clk_out3,
clk_out4,
locked,
clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_ant_clk_gen_stg2;
wire clk_out1;
wire clk_out1_ant_clk_gen_stg2;
wire clk_out2;
wire clk_out2_ant_clk_gen_stg2;
wire clk_out3;
wire clk_out3_ant_clk_gen_stg2;
wire clk_out4;
wire clk_out4_ant_clk_gen_stg2;
wire clkfbout_ant_clk_gen_stg2;
wire clkfbout_buf_ant_clk_gen_stg2;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ant_clk_gen_stg2),
.O(clkfbout_buf_ant_clk_gen_stg2));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkin1_bufg
(.I(clk_in1),
.O(clk_in1_ant_clk_gen_stg2));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_ant_clk_gen_stg2),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_out2_ant_clk_gen_stg2),
.O(clk_out2));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(clk_out3_ant_clk_gen_stg2),
.O(clk_out3));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout4_buf
(.I(clk_out4_ant_clk_gen_stg2),
.O(clk_out4));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.417000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(20),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(30),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(50),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ant_clk_gen_stg2),
.CLKFBOUT(clkfbout_ant_clk_gen_stg2),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_ant_clk_gen_stg2),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_ant_clk_gen_stg2),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_out2_ant_clk_gen_stg2),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(clk_out3_ant_clk_gen_stg2),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(clk_out4_ant_clk_gen_stg2),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg2/ant_clk_gen_stg2_sim_netlist.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top ant_clk_gen_stg2 -prefix
-- ant_clk_gen_stg2_ ant_clk_gen_stg2_sim_netlist.vhdl
-- Design : ant_clk_gen_stg2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz;
architecture STRUCTURE of ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz is
signal clk_in1_ant_clk_gen_stg2 : STD_LOGIC;
signal clk_out1_ant_clk_gen_stg2 : STD_LOGIC;
signal clk_out2_ant_clk_gen_stg2 : STD_LOGIC;
signal clk_out3_ant_clk_gen_stg2 : STD_LOGIC;
signal clk_out4_ant_clk_gen_stg2 : STD_LOGIC;
signal clkfbout_ant_clk_gen_stg2 : STD_LOGIC;
signal clkfbout_buf_ant_clk_gen_stg2 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_bufg : label is "PRIMITIVE";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ant_clk_gen_stg2,
O => clkfbout_buf_ant_clk_gen_stg2
);
clkin1_bufg: unisim.vcomponents.BUFG
port map (
I => clk_in1,
O => clk_in1_ant_clk_gen_stg2
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_ant_clk_gen_stg2,
O => clk_out1
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_out2_ant_clk_gen_stg2,
O => clk_out2
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk_out3_ant_clk_gen_stg2,
O => clk_out3
);
clkout4_buf: unisim.vcomponents.BUFG
port map (
I => clk_out4_ant_clk_gen_stg2,
O => clk_out4
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.417000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 20,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 30,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 50,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ant_clk_gen_stg2,
CLKFBOUT => clkfbout_ant_clk_gen_stg2,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_ant_clk_gen_stg2,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_ant_clk_gen_stg2,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_out2_ant_clk_gen_stg2,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk_out3_ant_clk_gen_stg2,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => clk_out4_ant_clk_gen_stg2,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ant_clk_gen_stg2 is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ant_clk_gen_stg2 : entity is true;
end ant_clk_gen_stg2;
architecture STRUCTURE of ant_clk_gen_stg2 is
begin
inst: entity work.ant_clk_gen_stg2_ant_clk_gen_stg2_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
clk_out2 => clk_out2,
clk_out3 => clk_out3,
clk_out4 => clk_out4,
locked => locked
);
end STRUCTURE;
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg2/ant_clk_gen_stg2_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top ant_clk_gen_stg2 -prefix
// ant_clk_gen_stg2_ ant_clk_gen_stg2_stub.v
// Design : ant_clk_gen_stg2
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ant_clk_gen_stg2(clk_out1, clk_out2, clk_out3, clk_out4, locked,
clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
endmodule
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ant_clk_gen_stg2/ant_clk_gen_stg2_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top ant_clk_gen_stg2 -prefix
-- ant_clk_gen_stg2_ ant_clk_gen_stg2_stub.vhdl
-- Design : ant_clk_gen_stg2
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ant_clk_gen_stg2 is
Port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end ant_clk_gen_stg2;
architecture stub of ant_clk_gen_stg2 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
begin
end;
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ip/ila_tx_rx/ila_tx_rx.veo
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// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ila_tx_rx your_instance_name (
.clk(clk), // input wire clk
.probe0(probe0), // input wire [11:0] probe0
.probe1(probe1), // input wire [11:0] probe1
.probe2(probe2), // input wire [11:0] probe2
.probe3(probe3), // input wire [11:0] probe3
.probe4(probe4), // input wire [11:0] probe4
.probe5(probe5), // input wire [11:0] probe5
.probe6(probe6), // input wire [11:0] probe6
.probe7(probe7), // input wire [11:0] probe7
.probe8(probe8), // input wire [11:0] probe8
.probe9(probe9) // input wire [11:0] probe9
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file ila_tx_rx when simulating
// the core, ila_tx_rx. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:39:48 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top ila_tx_rx -prefix
// ila_tx_rx_ ila_tx_rx_stub.v
// Design : ila_tx_rx
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
module ila_tx_rx(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[11:0]" */;
input clk;
input [11:0]probe0;
input [11:0]probe1;
input [11:0]probe2;
input [11:0]probe3;
input [11:0]probe4;
input [11:0]probe5;
input [11:0]probe6;
input [11:0]probe7;
input [11:0]probe8;
input [11:0]probe9;
endmodule
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:39:48 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top ila_tx_rx -prefix
-- ila_tx_rx_ ila_tx_rx_stub.vhdl
-- Design : ila_tx_rx
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ila_tx_rx is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end ila_tx_rx;
architecture stub of ila_tx_rx is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[11:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
begin
end;
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// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`timescale 1ns / 1ps
module ila_tx_rx (
clk,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9
);
input clk;
input [11 : 0] probe0;
input [11 : 0] probe1;
input [11 : 0] probe2;
input [11 : 0] probe3;
input [11 : 0] probe4;
input [11 : 0] probe5;
input [11 : 0] probe6;
input [11 : 0] probe7;
input [11 : 0] probe8;
input [11 : 0] probe9;
endmodule
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// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`timescale 1ns / 1ps
module vio_manual_ctrl (
clk,
probe_out0,
probe_out1,
probe_out2,
probe_out3,
probe_out4
);
input clk;
output reg [1 : 0] probe_out0 = 'h0 ;
output reg [0 : 0] probe_out1 = 'h0 ;
output reg [31 : 0] probe_out2 = 'h00000000 ;
output reg [1 : 0] probe_out3 = 'h3 ;
output reg [3 : 0] probe_out4 = 'h0 ;
endmodule
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:vio:3.0
// IP Revision: 20
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
vio_manual_ctrl your_instance_name (
.clk(clk), // input wire clk
.probe_out0(probe_out0), // output wire [1 : 0] probe_out0
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
.probe_out4(probe_out4) // output wire [3 : 0] probe_out4
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file vio_manual_ctrl.v when simulating
// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:vio:3.0
-- IP Revision: 20
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT vio_manual_ctrl
PORT (
clk : IN STD_LOGIC;
probe_out0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : vio_manual_ctrl
PORT MAP (
clk => clk,
probe_out0 => probe_out0,
probe_out1 => probe_out1,
probe_out2 => probe_out2,
probe_out3 => probe_out3,
probe_out4 => probe_out4
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating
-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 29 16:41:24 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_basic/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
// Design : vio_manual_ctrl
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
probe_out3, probe_out4)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
input clk;
output [1:0]probe_out0;
output [0:0]probe_out1;
output [31:0]probe_out2;
output [1:0]probe_out3;
output [3:0]probe_out4;
endmodule
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 29 16:41:24 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_basic/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
-- Design : vio_manual_ctrl
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vio_manual_ctrl is
Port (
clk : in STD_LOGIC;
probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end vio_manual_ctrl;
architecture stub of vio_manual_ctrl is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
end;
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26688)
`protect data_block
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projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
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projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
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projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
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projects/datalink_814/dl814_k7_basic/ip/ip_user_files/ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd
+418
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@@ -0,0 +1,418 @@
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/README.txt
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################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun Mar 26 00:46:36 CST 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_clk_gen.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
./ad9361_clk_gen.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_clk_gen.sh -noclean_files
For more information on the script, please type './ad9361_clk_gen.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/ad9361_clk_gen.sh
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_clk_gen.sh
# Simulator : Aldec Active-HDL Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun Mar 26 00:46:36 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_clk_gen.sh [-help]
# usage: ad9361_clk_gen.sh [-lib_map_path]
# usage: ad9361_clk_gen.sh [-noclean_files]
# usage: ad9361_clk_gen.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
map_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
map_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Map library.cfg file
map_setup_file()
{
file="library.cfg"
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_clk_gen.sh [-help]\n\
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
Usage: ad9361_clk_gen.sh [-reset_run]\n\
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/ad9361_clk_gen.udo
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projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/compile.do
+23
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vlib work
vlib activehdl
vlib activehdl/xil_defaultlib
vlib activehdl/xpm
vmap xil_defaultlib activehdl/xil_defaultlib
vmap xpm activehdl/xpm
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
vlog -work xil_defaultlib \
"glbl.v"
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/file_info.txt
+6
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@@ -0,0 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/glbl.v
+71
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/simulate.do
+17
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onbreak {quit -force}
onerror {quit -force}
asim -t 1ps +access +r +m+ad9361_clk_gen -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ad9361_clk_gen xil_defaultlib.glbl
do {wave.do}
view wave
view structure
do {ad9361_clk_gen.udo}
run -all
endsim
quit -force
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/activehdl/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/ies/README.txt
+48
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@@ -0,0 +1,48 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun Mar 26 00:46:36 CST 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_clk_gen.sh
This command will launch the 'execute' function for the single-step flow. This
function is called from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
./ad9361_clk_gen.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_clk_gen.sh -noclean_files
For more information on the script, please type './ad9361_clk_gen.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/ies/ad9361_clk_gen.sh
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_clk_gen.sh
# Simulator : Cadence Incisive Enterprise Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun Mar 26 00:46:36 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_clk_gen.sh [-help]
# usage: ad9361_clk_gen.sh [-lib_map_path]
# usage: ad9361_clk_gen.sh [-noclean_files]
# usage: ad9361_clk_gen.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Directory path for design sources and include directories (if any) wrt this path
ref_dir="."
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
ref_dir="$export_sim_ref_dir"
fi
# Set the compiled library directory
ref_lib_dir="."
# Command line options
irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
# Design libraries
design_libs=(xil_defaultlib xpm)
# Simulation root library directory
sim_lib_dir="ies_lib"
# Script info
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
execute
}
# RUN_STEP: <execute>
execute()
{
irun $irun_opts \
-reflib "$ref_lib_dir/unisim:unisim" \
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
-reflib "$ref_lib_dir/secureip:secureip" \
-reflib "$ref_lib_dir/unimacro:unimacro" \
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-top xil_defaultlib.ad9361_clk_gen \
-f run.f \
-top glbl \
glbl.v \
+incdir+"$ref_dir/../../../ipstatic" \
+incdir+"../../../ipstatic"
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
else
ref_lib_dir=$2
fi
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Create design library directory paths
create_lib_dir()
{
if [[ -e $sim_lib_dir ]]; then
rm -rf $sim_lib_dir
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
lib_dir="$sim_lib_dir/$lib"
if [[ ! -e $lib_dir ]]; then
mkdir -p $lib_dir
fi
done
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_clk_gen.sh [-help]\n\
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
Usage: ad9361_clk_gen.sh [-reset_run]\n\
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/ies/file_info.txt
+6
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@@ -0,0 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/ies/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/ies/run.f
+15
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@@ -0,0 +1,15 @@
-makelib ies_lib/xil_defaultlib -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib ies_lib/xpm \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib ies_lib/xil_defaultlib \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
-endlib
-makelib ies_lib/xil_defaultlib \
glbl.v
-endlib
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/README.txt
+49
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@@ -0,0 +1,49 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun Mar 26 00:46:36 CST 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_clk_gen.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
./ad9361_clk_gen.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_clk_gen.sh -noclean_files
For more information on the script, please type './ad9361_clk_gen.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/ad9361_clk_gen.sh
+167
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_clk_gen.sh
# Simulator : Mentor Graphics ModelSim Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun Mar 26 00:46:36 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_clk_gen.sh [-help]
# usage: ad9361_clk_gen.sh [-lib_map_path]
# usage: ad9361_clk_gen.sh [-noclean_files]
# usage: ad9361_clk_gen.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -64 -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
copy_setup_file $2
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="/home/josh/Mentor/CompLib/2019.1.3"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
cp $src_file .
fi
}
# Create design library directory
create_lib_dir()
{
lib_dir="modelsim_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_clk_gen.sh [-help]\n\
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
Usage: ad9361_clk_gen.sh [-reset_run]\n\
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/ad9361_clk_gen.udo
View File
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/compile.do
+23
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@@ -0,0 +1,23 @@
vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/xpm
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap xpm modelsim_lib/msim/xpm
vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ipstatic" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
vlog -work xil_defaultlib \
"glbl.v"
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/file_info.txt
+6
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@@ -0,0 +1,6 @@
xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/glbl.v
+71
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@@ -0,0 +1,71 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/simulate.do
+16
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@@ -0,0 +1,16 @@
onbreak {quit -f}
onerror {quit -f}
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ad9361_clk_gen xil_defaultlib.glbl
do {wave.do}
view wave
view structure
view signals
do {ad9361_clk_gen.udo}
run -all
quit -force
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/modelsim/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/README.txt
+49
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@@ -0,0 +1,49 @@
################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun Mar 26 00:46:36 CST 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_clk_gen.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
./ad9361_clk_gen.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_clk_gen.sh -noclean_files
For more information on the script, please type './ad9361_clk_gen.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/ad9361_clk_gen.sh
+174
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_clk_gen.sh
# Simulator : Mentor Graphics Questa Advanced Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun Mar 26 00:46:36 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_clk_gen.sh [-help]
# usage: ad9361_clk_gen.sh [-lib_map_path]
# usage: ad9361_clk_gen.sh [-noclean_files]
# usage: ad9361_clk_gen.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
elaborate
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
source elaborate.do 2>&1 | tee -a elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -64 -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
copy_setup_file $2
esac
create_lib_dir
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
cp $src_file .
fi
}
# Create design library directory
create_lib_dir()
{
lib_dir="questa_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
create_lib_dir
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_clk_gen.sh [-help]\n\
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
Usage: ad9361_clk_gen.sh [-reset_run]\n\
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/ad9361_clk_gen.udo
View File
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/compile.do
+23
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@@ -0,0 +1,23 @@
vlib questa_lib/work
vlib questa_lib/msim
vlib questa_lib/msim/xil_defaultlib
vlib questa_lib/msim/xpm
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
vmap xpm questa_lib/msim/xpm
vlog -work xil_defaultlib -64 -sv "+incdir+../../../ipstatic" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v" \
"../../../ip/ad9361_clk_gen/ad9361_clk_gen.v" \
vlog -work xil_defaultlib \
"glbl.v"
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/elaborate.do
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vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ad9361_clk_gen xil_defaultlib.glbl -o ad9361_clk_gen_opt
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/file_info.txt
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xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
ad9361_clk_gen.v,verilog,xil_defaultlib,../../../ip/ad9361_clk_gen/ad9361_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/glbl.v
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/simulate.do
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onbreak {quit -f}
onerror {quit -f}
vsim -t 1ps -lib xil_defaultlib ad9361_clk_gen_opt
do {wave.do}
view wave
view structure
view signals
do {ad9361_clk_gen.udo}
run -all
quit -force
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/questa/wave.do
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add wave *
add wave /glbl/GSR
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/riviera/README.txt
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################################################################################
# Vivado (TM) v2019.1.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun Mar 26 00:46:36 CST 2023
#
################################################################################
1. How to run the generated simulation script:-
From the shell prompt in the current directory, issue the following command:-
./ad9361_clk_gen.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first executes the 'setup' function, the purpose of which is to
create simulator specific setup files, create design library mappings and library
directories and copy 'glbl.v' from the Vivado software install location into the
current directory.
The 'setup' function is also used for removing the simulator generated data in
order to reset the current directory to the original state when export_simulation
was launched from Vivado. This generated data can be removed by specifying the
'-reset_run' switch to the './ad9361_clk_gen.sh' script.
./ad9361_clk_gen.sh -reset_run
To keep the generated data from the previous run but regenerate the setup files and
library directories, use the '-noclean_files' switch.
./ad9361_clk_gen.sh -noclean_files
For more information on the script, please type './ad9361_clk_gen.sh -help'.
2. Additional design information files:-
export_simulation generates following additional file that can be used for fetching
the design files information or for integrating with external custom scripts.
Name : file_info.txt
Purpose: This file contains detail design file information based on the compile order
when export_simulation was executed from Vivado. The file contains information
about the file type, name, whether it is part of the IP, associated library
and the file path information.
projects/datalink_814/dl814_k7_basic/ip/ip_user_files/sim_scripts/ad9361_clk_gen/riviera/ad9361_clk_gen.sh
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#!/bin/bash -f
#*********************************************************************************************************
# Vivado (TM) v2019.1.3 (64-bit)
#
# Filename : ad9361_clk_gen.sh
# Simulator : Aldec Riviera-PRO Simulator
# Description : Simulation script for compiling, elaborating and verifying the project source files.
# The script will automatically create the design libraries sub-directories in the run
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun Mar 26 00:46:36 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
# usage: ad9361_clk_gen.sh [-help]
# usage: ad9361_clk_gen.sh [-lib_map_path]
# usage: ad9361_clk_gen.sh [-noclean_files]
# usage: ad9361_clk_gen.sh [-reset_run]
#
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
# that points to these libraries and rerun export_simulation. For more information about this switch please
# type 'export_simulation -help' in the Tcl shell.
#
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
# executing this script. Please type 'ad9361_clk_gen.sh -help' for more information.
#
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#*********************************************************************************************************
# Script info
echo -e "ad9361_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
# Main steps
run()
{
check_args $# $1
setup $1 $2
compile
simulate
}
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
map_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
map_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
# Map library.cfg file
map_setup_file()
{
file="library.cfg"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="/home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# Delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# Check command line arguments
check_args()
{
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
echo -e "ERROR: Unknown option specified '$2' (type \"./ad9361_clk_gen.sh -help\" for more information)\n"
exit 1
fi
if [[ ($2 == "-help" || $2 == "-h") ]]; then
usage
fi
}
# Script usage
usage()
{
msg="Usage: ad9361_clk_gen.sh [-help]\n\
Usage: ad9361_clk_gen.sh [-lib_map_path]\n\
Usage: ad9361_clk_gen.sh [-reset_run]\n\
Usage: ad9361_clk_gen.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
-noclean_files switch.\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
echo -e $msg
exit 1
}
# Launch script
run $1 $2

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