analog.com user axi_clkgen 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW clk CLK clk clk2 CLK clk2 clk_0 CLK clk_0 clk_1 CLK clk_1 s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_clkgen xilinx_anylanguagesynthesis_view_fileset viewChecksum dd68556b xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_clkgen xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum dd68556b xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 6f7527fe xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation clk2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false clk_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation clk_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 FPGA_VOLTAGE Fpga Voltage 0 CLKSEL_EN Clksel En 0 CLKIN_PERIOD Clkin Period 5 CLKIN2_PERIOD Clkin2 Period 5 false VCO_DIV Vco Div 11 VCO_MUL Vco Mul 49 CLK0_DIV Clk0 Div 6 CLK0_PHASE Clk0 Phase 0 CLK1_DIV Clk1 Div 6 false CLK1_PHASE Clk1 Phase 0 false choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_38e7dd38 0 1 2 3 4 choice_pairs_68effc1b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 choice_pairs_a535243b 0 10 11 12 13 14 20 21 22 30 choice_pairs_aee923ef 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/ad_mmcm_drp.v verilogSource ../common/ad_rst.v verilogSource ../common/up_axi.v verilogSource ../common/up_clkgen.v verilogSource ../scripts/adi_xilinx_device_info_enc.tcl tclSource bd/bd.tcl tclSource axi_clkgen.v verilogSource CHECKSUM_386d12b2 xilinx_anylanguagebehavioralsimulation_view_fileset ../xilinx/common/ad_mmcm_drp.v verilogSource ../common/ad_rst.v verilogSource ../common/up_axi.v verilogSource ../common/up_clkgen.v verilogSource ../scripts/adi_xilinx_device_info_enc.tcl tclSource bd/bd.tcl tclSource axi_clkgen.v verilogSource xilinx_xpgui_view_fileset xgui/axi_clkgen_v1_0.tcl tclSource CHECKSUM_4919e9d5 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_utilityxitfiles_view_fileset gui/axi_clkgen_v1_0.gtcl GTCL axi_clkgen_v1_0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 FPGA_VOLTAGE Fpga Voltage 0 CLKSEL_EN Clksel En 0 CLKIN_PERIOD Clkin Period 5 CLKIN2_PERIOD Clkin2 Period 5 false VCO_DIV Vco Div 11 VCO_MUL Vco Mul 49 CLK0_DIV Clk0 Div 6 CLK0_PHASE Clk0 Phase 0 CLK1_DIV Clk1 Div 6 false CLK1_PHASE Clk1 Phase 0 false Component_Name axi_clkgen_v1_0 ENABLE_CLKIN2 Enable secondary clock input false ENABLE_CLKOUT1 Enable secondary clock output false virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices axi_clkgen_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:22:17Z 2019.1.3