analog.com user axi_mc_controller 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW ref_clk CLK ref_clk ctrl_data_clk CLK ctrl_data_clk s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_mc_controller xilinx_anylanguagesynthesis_view_fileset viewChecksum a3054a15 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_mc_controller xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 826c8096 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 ref_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_data_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 fmc_en_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_ah_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_al_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_bh_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_bl_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_ch_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_cl_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation gpo_o out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_a_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_b_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm_c_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sensors_o out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation position_i in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_mc_controller_constr.xdc xdc control_registers.v verilogSource delay.v verilogSource motor_driver.v verilogSource ../common/up_axi.v verilogSource axi_mc_controller.v verilogSource CHECKSUM_2d356c0a xilinx_anylanguagebehavioralsimulation_view_fileset control_registers.v verilogSource delay.v verilogSource motor_driver.v verilogSource ../common/up_axi.v verilogSource axi_mc_controller.v verilogSource xilinx_xpgui_view_fileset xgui/axi_mc_controller_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 axi_mc_controller_v1_0 Component_Name axi_mc_controller_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_mc_controller_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:15:52Z 2019.1.3