analog.com user axi_dacfifo 1.0 axi AWID axi_awid AWADDR axi_awaddr AWLEN axi_awlen AWSIZE axi_awsize AWBURST axi_awburst AWLOCK axi_awlock AWCACHE axi_awcache AWPROT axi_awprot AWQOS axi_awqos AWVALID axi_awvalid AWREADY axi_awready WDATA axi_wdata WSTRB axi_wstrb WLAST axi_wlast WVALID axi_wvalid WREADY axi_wready BID axi_bid BRESP axi_bresp BVALID axi_bvalid BREADY axi_bready ARID axi_arid ARADDR axi_araddr ARLEN axi_arlen ARSIZE axi_arsize ARBURST axi_arburst ARLOCK axi_arlock ARCACHE axi_arcache ARPROT axi_arprot ARQOS axi_arqos ARVALID axi_arvalid ARREADY axi_arready RID axi_rid RDATA axi_rdata RRESP axi_rresp RLAST axi_rlast RVALID axi_rvalid RREADY axi_rready axi_clk CLK axi_clk ASSOCIATED_BUSIF axi ASSOCIATED_RESET axi_resetn axi_resetn RST axi_resetn POLARITY ACTIVE_LOW dma_clk CLK dma_clk ASSOCIATED_RESET dma_rst dma_rst RST dma_rst dac_clk CLK dac_clk ASSOCIATED_RESET dac_rst dac_rst RST dac_rst axi 4294967296 512 xilinx_anylanguagesynthesis Synthesis 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xilinx_anylanguagebehavioralsimulation dac_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data out 63 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_dunf out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_xfer_out out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bypass in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation axi_awid out 3 0 std_logic_vector xilinx_anylanguagesynthesis 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xilinx_anylanguagebehavioralsimulation 0 axi_rid in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rdata in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 axi_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DAC_DATA_WIDTH Dac Data Width 64 DMA_DATA_WIDTH Dma Data Width 64 AXI_DATA_WIDTH Axi Data Width 512 AXI_SIZE Axi Size 2 AXI_LENGTH Axi Length 15 AXI_ADDRESS Axi Address 0x00000000 AXI_ADDRESS_LIMIT Axi Address Limit 0xFFFFFFFF choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_dacfifo_constr.xdc xdc ../../common/ad_axis_inf_rx.v verilogSource ../../common/ad_b2g.v verilogSource ../../common/ad_g2b.v verilogSource ../../common/ad_mem.v verilogSource ../../common/ad_mem_asym.v verilogSource axi_dacfifo_address_buffer.v verilogSource axi_dacfifo_rd.v verilogSource axi_dacfifo_wr.v verilogSource ../../util_dacfifo/util_dacfifo_bypass.v verilogSource axi_dacfifo.v verilogSource CHECKSUM_ea154f34 xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_axis_inf_rx.v verilogSource ../../common/ad_b2g.v verilogSource ../../common/ad_g2b.v verilogSource ../../common/ad_mem.v verilogSource ../../common/ad_mem_asym.v verilogSource axi_dacfifo_address_buffer.v verilogSource axi_dacfifo_rd.v verilogSource axi_dacfifo_wr.v verilogSource ../../util_dacfifo/util_dacfifo_bypass.v verilogSource axi_dacfifo.v verilogSource xilinx_xpgui_view_fileset xgui/axi_dacfifo_v1_0.tcl tclSource CHECKSUM_bde7c6b3 XGUI_VERSION_2 axi_dacfifo_v1_0 DAC_DATA_WIDTH Dac Data Width 64 DMA_DATA_WIDTH Dma Data Width 64 AXI_DATA_WIDTH Axi Data Width 512 AXI_SIZE Axi Size 2 AXI_LENGTH Axi Length 15 AXI_ADDRESS Axi Address 0x00000000 AXI_ADDRESS_LIMIT Axi Address Limit 0xFFFFFFFF Component_Name axi_dacfifo_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_dacfifo_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:20:20Z 2019.1.3