analog.com user jesd204_tx 1.0 tx_data TVALID tx_valid TREADY tx_ready TDATA tx_data tx_phy0 txdata phy_data 31 0 txcharisk phy_charisk 3 0 txheader phy_header 1 0 true tx_phy1 txdata phy_data 63 32 txcharisk phy_charisk 7 4 txheader phy_header 3 2 false tx_phy2 txdata phy_data 95 64 txcharisk phy_charisk 11 8 txheader phy_header 5 4 false tx_phy3 txdata phy_data 127 96 txcharisk phy_charisk 15 12 txheader phy_header 7 6 false tx_phy4 txdata phy_data 159 128 txcharisk phy_charisk 19 16 txheader phy_header 9 8 false tx_phy5 txdata phy_data 191 160 txcharisk phy_charisk 23 20 txheader phy_header 11 10 false tx_phy6 txdata phy_data 223 192 txcharisk phy_charisk 27 24 txheader phy_header 13 12 false tx_phy7 txdata phy_data 255 224 txcharisk phy_charisk 31 28 txheader phy_header 15 14 false tx_phy8 txdata phy_data 287 256 txcharisk phy_charisk 35 32 txheader phy_header 17 16 false tx_phy9 txdata phy_data 319 288 txcharisk phy_charisk 39 36 txheader phy_header 19 18 false tx_phy10 txdata phy_data 351 320 txcharisk phy_charisk 43 40 txheader phy_header 21 20 false tx_phy11 txdata phy_data 383 352 txcharisk phy_charisk 47 44 txheader phy_header 23 22 false tx_phy12 txdata phy_data 415 384 txcharisk phy_charisk 51 48 txheader phy_header 25 24 false tx_phy13 txdata phy_data 447 416 txcharisk phy_charisk 55 52 txheader phy_header 27 26 false tx_phy14 txdata phy_data 479 448 txcharisk phy_charisk 59 56 txheader phy_header 29 28 false tx_phy15 txdata phy_data 511 480 txcharisk phy_charisk 63 60 txheader phy_header 31 30 false tx_cfg lanes_disable cfg_lanes_disable links_disable cfg_links_disable beats_per_multiframe cfg_beats_per_multiframe octets_per_frame cfg_octets_per_frame lmfc_offset cfg_lmfc_offset sysref_oneshot cfg_sysref_oneshot sysref_disable cfg_sysref_disable continuous_cgs cfg_continuous_cgs continuous_ilas cfg_continuous_ilas skip_ilas cfg_skip_ilas mframes_per_ilas cfg_mframes_per_ilas disable_char_replacement cfg_disable_char_replacement disable_scrambler cfg_disable_scrambler tx_ilas_config rd ilas_config_rd addr ilas_config_addr data ilas_config_data true tx_event sysref_alignment_error event_sysref_alignment_error sysref_edge event_sysref_edge tx_status state status_state sync status_sync tx_ctrl manual_sync_request ctrl_manual_sync_request true tx_data_tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_clock tx_data_tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_clock CLK clk ASSOCIATED_BUSIF tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl ASSOCIATED_RESET reset tx_data_tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_reset tx_data_tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_reset RST reset POLARITY ACTIVE_HIGH xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_tx xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 17e094e8 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_tx xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 17e094e8 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 9907ebf1 xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_charisk out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_header out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sysref in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true tx_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tx_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lanes_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_links_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_beats_per_multiframe in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_frame in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lmfc_offset in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_sysref_oneshot in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_sysref_disable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_cgs in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_ilas in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_skip_ilas in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_mframes_per_ilas in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_char_replacement in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_scrambler in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_rd out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_addr out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_manual_sync_request in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 event_sysref_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation event_sysref_alignment_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_sync out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_state out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_OUTPUT_PIPELINE Num Output Pipeline 0 LINK_MODE Link Mode 1 DATA_PATH_WIDTH Data Path Width 4 choice_pairs_1942b210 2 1 xilinx_anylanguagesynthesis_view_fileset jesd204_tx_constr.ttcl ttcl jesd204_tx_ctrl.v verilogSource jesd204_tx_header.v verilogSource jesd204_tx_lane.v verilogSource jesd204_tx_lane_64b.v verilogSource jesd204_tx.v verilogSource CHECKSUM_064467a3 xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_tx_ctrl.v verilogSource jesd204_tx_header.v verilogSource jesd204_tx_lane.v verilogSource jesd204_tx_lane_64b.v verilogSource jesd204_tx.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/jesd204_tx_v1_0.tcl tclSource CHECKSUM_4b2560df XGUI_VERSION_2 xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/jesd204_tx_v1_0.gtcl GTCL ADI JESD204 Transmit NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_OUTPUT_PIPELINE Num Output Pipeline 0 LINK_MODE Link Layer mode 1 DATA_PATH_WIDTH Data Path Width 4 false Component_Name jesd204_tx_v1_0 SYSREF_IOB Place SYSREF in IOB true virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices ADI JESD204 Transmit package_project Analog Devices http://www.analog.com 1 2021-12-09T07:17:38Z 2019.1.3