analog.com user spi_engine_execution 1.0 ctrl CMD_READY cmd_ready CMD_VALID cmd_valid CMD_DATA cmd SDO_READY sdo_data_ready SDO_VALID sdo_data_valid SDO_DATA sdo_data SDI_READY sdi_data_ready SDI_VALID sdi_data_valid SDI_DATA sdi_data SYNC_READY sync_ready SYNC_VALID sync_valid SYNC_DATA sync ctrl_signal_clock ctrl_signal_clock CLK clk ASSOCIATED_BUSIF ctrl ASSOCIATED_RESET resetn ctrl_signal_reset ctrl_signal_reset RST resetn POLARITY ACTIVE_LOW spi SCLK sclk SDI sdi SDO sdo SDO_T sdo_t THREE_WIRE three_wire CS cs spi_signal_clock spi_signal_clock CLK clk ASSOCIATED_BUSIF spi ASSOCIATED_RESET resetn spi_signal_reset spi_signal_reset RST resetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog spi_engine_execution xilinx_anylanguagesynthesis_view_fileset viewChecksum 537cc789 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog spi_engine_execution xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 537cc789 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 49a5a305 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation active out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdo_data_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdi_data_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdi_data_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_valid out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sclk out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_t out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 cs out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation three_wire out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_CS Num Of Cs 1 DEFAULT_SPI_CFG Default Spi Cfg 0 DEFAULT_CLK_DIV Default Clk Div 0 DATA_WIDTH Data Width 8 NUM_OF_SDI Num Of Sdi 1 SDO_DEFAULT Sdo Default "0" SDI_DELAY Sdi Delay false choice_list_b71134be "0" "1" choice_list_dd9ee503 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset spi_engine_execution.v verilogSource CHECKSUM_537cc789 xilinx_anylanguagebehavioralsimulation_view_fileset spi_engine_execution.v verilogSource xilinx_xpgui_view_fileset xgui/spi_engine_execution_v1_0.tcl tclSource CHECKSUM_4d31af11 XGUI_VERSION_2 spi_engine_execution_v1_0 NUM_OF_CS Number of CSN lines 1 DEFAULT_SPI_CFG Default SPI mode 0 DEFAULT_CLK_DIV Default SCLK divider 0 DATA_WIDTH Parallel data width 8 NUM_OF_SDI Number of MISO 1 SDO_DEFAULT MOSI default level "0" SDI_DELAY Delay MISO latching false Component_Name spi_engine_execution_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices spi_engine_execution_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:07:50Z 2019.1.3