analog.com user axi_jesd204_common 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_up_common xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 20a384cb xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_up_common xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 46282bf1 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum fb8a8194 up_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ext_resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_reset_synchronizer out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_reset_ext in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_raddr in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_rdata out 31 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_wreq in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_waddr in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_extra_cfg in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_irq_trigger in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cfg_is_writeable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_lanes_disable out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_links_disable out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_beats_per_multiframe out 7 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_octets_per_frame out 7 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_disable_scrambler out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_disable_char_replacement out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_extra_cfg out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation PCORE_VERSION Pcore Version 0 PCORE_MAGIC Pcore Magic 0 ID Id 0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 DATA_PATH_WIDTH Data Path Width 2 MAX_OCTETS_PER_FRAME Max Octets Per Frame 256 NUM_IRQS Num Irqs 1 EXTRA_CFG_WIDTH Extra Cfg Width 1 LINK_MODE Link Mode 1 ENABLE_LINK_STATS Enable Link Stats 0 xilinx_anylanguagesynthesis_view_fileset jesd204_up_common.v verilogSource jesd204_up_sysref.v verilogSource ../../xilinx/common/up_clock_mon_constr.xdc xdc ../../common/up_clock_mon.v verilogSource CHECKSUM_ec760b7c xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_up_common.v verilogSource jesd204_up_sysref.v verilogSource ../../common/up_clock_mon.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/jesd204_up_common_v1_0.tcl tclSource CHECKSUM_fb8a8194 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset ADI AXI JESD204B Common Library PCORE_VERSION Pcore Version 0 PCORE_MAGIC Pcore Magic 0 ID Id 0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 DATA_PATH_WIDTH Data Path Width 2 MAX_OCTETS_PER_FRAME Max Octets Per Frame 256 NUM_IRQS Num Irqs 1 EXTRA_CFG_WIDTH Extra Cfg Width 1 LINK_MODE Link Mode 1 ENABLE_LINK_STATS Enable Link Stats 0 Component_Name jesd204_up_common_v1_0 virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices ADI AXI JESD204B Common Library true package_project Analog Devices http://www.analog.com 1 2021-12-08T12:24:39Z 2019.1.3