analog.com user axi_spdif_tx 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axis TDATA s_axis_tdata TLAST s_axis_tlast TVALID s_axis_tvalid TREADY s_axis_tready true dma_req_aclk CLK dma_req_aclk ASSOCIATED_RESET dma_req_rstn s_axis_aclk CLK s_axis_aclk ASSOCIATED_BUSIF s_axis ASSOCIATED_RESET s_axis_aresetn spdif_data_clk CLK spdif_data_clk dma_req_rstn RST dma_req_rstn POLARITY ACTIVE_LOW s_axis_aresetn RST s_axis_aresetn POLARITY ACTIVE_LOW dma_ack TVALID dma_req_davalid TREADY dma_req_daready TUSER dma_req_datype false dma_req TVALID dma_req_drvalid TREADY dma_req_drready TUSER dma_req_drtype TLAST dma_req_drlast false dma_req_dma_ack_signal_clock dma_req_dma_ack_signal_clock CLK dma_req_aclk ASSOCIATED_BUSIF dma_req:dma_ack ASSOCIATED_RESET dma_req_rstn dma_req_dma_ack_signal_reset dma_req_dma_ack_signal_reset RST dma_req_rstn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axi_spdif_tx xilinx_anylanguagesynthesis_view_fileset viewChecksum 583a014a xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axi_spdif_tx xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 673f3e79 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum ff8f284a spdif_data_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 spdif_tx_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awaddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dma_req_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dma_req_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dma_req_davalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_datype in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_daready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drtype out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false S_AXI_DATA_WIDTH S Axi Data Width 32 S_AXI_ADDRESS_WIDTH S Axi Address Width 32 DEVICE_FAMILY Device Family virtex6 DMA_TYPE Dma Type 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_spdif_tx_constr.xdc xdc ../common/axi_ctrlif.vhd vhdlSource tx_package.vhd vhdlSource ../common/dma_fifo.vhd vhdlSource ../common/axi_streaming_dma_tx_fifo.vhd vhdlSource ../common/pl330_dma_fifo.vhd vhdlSource tx_encoder.vhd vhdlSource axi_spdif_tx.vhd vhdlSource CHECKSUM_34e69c4c xilinx_anylanguagebehavioralsimulation_view_fileset ../common/axi_ctrlif.vhd vhdlSource tx_package.vhd vhdlSource ../common/dma_fifo.vhd vhdlSource ../common/axi_streaming_dma_tx_fifo.vhd vhdlSource ../common/pl330_dma_fifo.vhd vhdlSource tx_encoder.vhd vhdlSource axi_spdif_tx.vhd vhdlSource xilinx_xpgui_view_fileset xgui/axi_spdif_tx_v1_0.tcl tclSource CHECKSUM_ff8f284a XGUI_VERSION_2 axi_spdif_tx_v1_0 S_AXI_DATA_WIDTH S Axi Data Width 32 S_AXI_ADDRESS_WIDTH S Axi Address Width 32 DEVICE_FAMILY Device Family virtex6 DMA_TYPE Dma Type 0 Component_Name axi_spdif_tx_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_spdif_tx_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:23:28Z 2019.1.3