`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/07/11 15:13:23
// Design Name:
// Module Name: GMSK_send
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module GMSK_send(
	input			clk_48M					,
	input			rst						,
	output  [11:0]	gmsk_12M_i,
	output  [11:0]	gmsk_12M_q,
	output  [11:0]	gmsk_1p5m_i,
	output  [11:0]	gmsk_1p5m_q
    );

	wire	[17:0]		gmsk_send1p5M_I		;
	wire	[17:0]		gmsk_send1p5M_Q		;
	wire	[17:0]		gmsk_send12M_I		;
	wire	[17:0]		gmsk_send12M_Q		;
	//ROM核输出数据 1.5M基带数据
	reg [4:0] cnt_32_data = 5'd0			;
	reg [10:0] addra_1p5m = 11'd0			;
	wire data_bio_1p5M;
	reg Rc_nd;
	data_1p5m data_1p5m (
	.clka(clk_48M),    			// input wire clka
	.ena(1'b1),      			// input wire ena
	.addra(addra_1p5m),  		// input wire [10 : 0] addra
	.douta(data_bio_1p5M) 		// output wire [0 : 0] douta
	);

	always @(posedge clk_48M)begin
		if(cnt_32_data == 5'd31)begin
			cnt_32_data <= 5'd0;
			addra_1p5m <= addra_1p5m + 11'd1;
			Rc_nd <= 1'b1;
		end
		else begin
			addra_1p5m <= addra_1p5m;
			cnt_32_data <= cnt_32_data + 5'd1;
			Rc_nd <= 1'b0;
		end
	end


	//
	reg Rc_data_buff = 0;
	reg Minus_1_Npower = 0;
	always @(posedge clk_48M)begin
			if(Rc_nd)
			Rc_data_buff <= data_bio_1p5M;
			Minus_1_Npower <= !Minus_1_Npower;
	end

	//预编码
	reg				precode_nd = 1'b0	;
	reg	[1:0]		precode_data = 2'd0 ;
	always @(posedge clk_48M)begin
		if(Rc_nd)begin
			precode_nd   <= 1'b1;
			precode_data <= {data_bio_1p5M ^ Rc_data_buff ^ Minus_1_Npower,1'b1} ;
		end
		else begin
			precode_nd <= 1'b0;
			precode_data <= precode_data;
		end
	end

	//高斯滤波器基带数据成型
	wire precode_tready_1mp5;
	wire GaussFir_dout_valid_1mp5;
	wire [15:0] GaussFir_dout_1mp5;
	GaussFir_1mp5 GaussFir_1mp5 (
	.aclk(clk_48M),                              // input wire aclk
	.s_axis_data_tvalid(precode_nd),  // input wire s_axis_data_tvalid
	.s_axis_data_tready(precode_tready_1mp5),  // output wire s_axis_data_tready
	.s_axis_data_tdata({{6{precode_data[1]}},precode_data}),    // input wire [7 : 0] s_axis_data_tdata
	.m_axis_data_tvalid(GaussFir_dout_valid_1mp5),  // output wire m_axis_data_tvalid
	.m_axis_data_tdata(GaussFir_dout_1mp5[15:0])    // output wire [15 : 0] m_axis_data_tdata
	);

	//存储相位地址
	reg signed [15:0] DDS_addra=16'd0;
	always @ (posedge clk_48M) begin
		if(rst)
			DDS_addra[15:0] <= 15'd0;
		else
			DDS_addra[15:0] <=  GaussFir_dout_1mp5[15:0];
	end

	reg [17:0] phase_addr = 18'd0;
	always @ (posedge clk_48M)begin
			phase_addr[17:0] <= phase_addr[17:0] + {{2{DDS_addra[15]}},DDS_addra[15:0]};
	end

	//相位累积进行基带调制1pm5
	AddrtoWaveform AddrtoWaveform(
		.clk		(	clk_48M)		,
		.rst		(	rst	   )		,

		.Phase_addr	(phase_addr[17:2])	,
		.Cos_Wave	( gmsk_send1p5M_I[17:0] ),
		.Sin_Wave	( gmsk_send1p5M_Q[17:0] )
		);

	//ROM核输出数据 12M
	reg [2:0] cnt_4_data = 3'd0;
	reg [10:0] addra_12m = 11'd0;
	wire data_bio_12M;
	reg Rc_nd_12m = 1'b0;
	data_1p5m data_12m (
	.clka(clk_48M),    // input wire clka
	.ena(1'b1),      // input wire ena
	.addra(addra_12m),  // input wire [10 : 0] addra
	.douta(data_bio_12M)  // output wire [0 : 0] douta
	);
	always @(posedge clk_48M)begin
		if(cnt_4_data == 3'd3)begin
			cnt_4_data <= 3'd0;
			addra_12m <= addra_12m + 11'd1;
			Rc_nd_12m <= 1'b1;
		end
		else begin
			addra_12m <= addra_12m;
			cnt_4_data <= cnt_4_data + 3'd1;
			Rc_nd_12m <= 1'b0;
		end
	end


	reg Rc_data_buff_12m = 0;
	reg Minus_1_Npower_12m = 0;
	always @(posedge clk_48M)begin
		if(Rc_nd_12m)
			Rc_data_buff_12m <= data_bio_12M;
			Minus_1_Npower_12m <= !Minus_1_Npower_12m;
	end
	//预编码
	reg				precode_nd_12m = 1'b0	;
	reg	[1:0]		precode_data_12m = 2'd0 ;

	always @(posedge clk_48M)begin
		if(Rc_nd_12m)begin
			precode_nd_12m   <= 1'b1;
			precode_data_12m <= {data_bio_12M ^ Rc_data_buff_12m ^ Minus_1_Npower_12m,1'b1};
			end
			else begin
				precode_nd_12m <= 1'b0;
				precode_data_12m <= precode_data_12m;
			end
	end

	//经过高斯低通滤波器
	wire precode_tready_12m;
	wire GaussFir_dout_valid_12m;
	wire [15:0] GaussFir_dout_12m;
	GaussFir_12m GaussFir_12m(
	.aclk(clk_48M),                              // input wire aclk
	.s_axis_data_tvalid(precode_nd_12m),  // input wire s_axis_data_tvalid
	.s_axis_data_tready(precode_tready_12m),  // output wire s_axis_data_tready
	.s_axis_data_tdata({{6{precode_data_12m[1]}},precode_data_12m}),    // input wire [7 : 0] s_axis_data_tdata
	.m_axis_data_tvalid(GaussFir_dout_valid_12m),  // output wire m_axis_data_tvalid
	.m_axis_data_tdata(GaussFir_dout_12m[15:0])    // output wire [15 : 0] m_axis_data_tdata
	);

	//相位累积进行基带调制1pm5
	reg signed [15:0] DDS_addra_12M=16'd0;
	always @ (posedge clk_48M) begin
		if(rst)
			DDS_addra_12M[15:0] <= 15'd0;
		else
			DDS_addra_12M[15:0] <=  {GaussFir_dout_12m[15:0]};
	end

	reg [17:0] phase_addr_12M = 18'd0;
	always @ (posedge clk_48M)begin
			phase_addr_12M[17:0] <= phase_addr_12M[17:0] + {{2{DDS_addra_12M[15]}},DDS_addra_12M[15:0]};
	end

	AddrtoWaveform AddrtoWaveform_12M(
		.clk		(	clk_48M)		,
		.rst		(	rst	   )		,

		.Phase_addr	( phase_addr_12M[17:3])	,
		.Cos_Wave	( gmsk_send12M_I[17:0] ),
		.Sin_Wave	( gmsk_send12M_Q[17:0] )
		);

	//截位输出数据
    assign gmsk_12M_i [11:0] = gmsk_send12M_I [17:6];
    assign gmsk_12M_q [11:0] = gmsk_send12M_Q [17:6];
    assign gmsk_1p5m_i [11:0] = gmsk_send1p5M_I [17:6];
    assign gmsk_1p5m_q [11:0] = gmsk_send1p5M_Q [17:6];



endmodule