`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:03:33 09/24/2021 
// Design Name: 
// Module Name:    fre_caliatt 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module 		fre_caliatt(
input				i_clk			,
input				i_rstn			,
output				ENABLE   	    ,
output				SC       	    ,
output				SD       	    ,
output				END_SYN  	    ,
input				SDOUT    	    ,
input				CAL_F    	    ,
input signed[7:0]	i_temp			,
input[15:0]			i_fre_mode		,
input[15:0]			i_cal_fre_code		,
input  [3:0]		cal1_mgc       ,
input  [3:0]		cal2_mgc       ,
input  [3:0]		cal3_mgc       ,
input  [3:0]		cal4_mgc       ,
input  [3:0]		i_ceshi_module       ,
input [40:0] 		SYNC_OUT		,
input 				SW				,
output [3:0]		R_CAL1			,
output [3:0]		R_CAL2			,
output [3:0]		R_CAL3			,	
output [3:0]		R_CAL4			,	
input [4:0]			tx_mgc			,	
input [4:0]			tx_cal_mgc			,	
output [4:0]		T_CAL			
 );
 
 
wire[15:0]	fre_mode		;
wire[31:0]	hop_fre_mode		;
assign		fre_mode		=	i_cal_fre_code/40		;//20.375Ghz~23.875Ghz
assign		hop_fre_mode	=	i_cal_fre_code+20375	;//20.375Ghz~23.875Ghz


wire [3:0]	R_CAL4_r    	    ;
wire [3:0]	R_CAL3_r    	    ;
wire [3:0]	R_CAL2_r    	    ;
wire [3:0]	R_CAL1_r    	    ;
wire [4:0]	T_CAL_r    	   	    ;
wire [31:0]	data_in	   		    ;
reg	 [31:0]	data_in_r	        ;
reg			R_CAL_F	   		    ;
wire[15:0]	cal_mgc_r	   		    ;
reg	[15:0]	cal_mgc_rr	   		    ;
reg			tx_en	   		    ;
reg 		vio_en		        ;




always@(posedge i_clk)
begin
	cal_mgc_rr	<=	cal_mgc_r;
end
//------------------vio_debug------------------------//
/* always@(posedge i_clk)
begin
	vio_R_CAL_4	<=	SYNC_OUT[4:0];
	vio_R_CAL_3	<=	SYNC_OUT[9:5];
	vio_R_CAL_2	<=	SYNC_OUT[14:10];
	vio_R_CAL_1	<=	SYNC_OUT[19:15];
	vio_T_CAL  	<=	SYNC_OUT[24:20];
	vio_en		<=	SYNC_OUT[25]; 	
end */

//------------------vio_debug------------------------//
assign R_CAL1	= R_CAL1_r + cal1_mgc ;//通道1 
assign R_CAL2	= R_CAL2_r + cal2_mgc ;//通道2 
assign R_CAL3	= R_CAL3_r + cal3_mgc ;//通道3 
assign R_CAL4	= R_CAL4_r + cal4_mgc ;//通道4 
assign T_CAL	= ( i_ceshi_module==4'ha || i_ceshi_module==4'hb) ? (tx_mgc[4:0] + tx_cal_mgc) :  (T_CAL_r + tx_cal_mgc) ;//发射通道，低衰减

assign		cal_mgc_r	=	{cal1_mgc,cal2_mgc,cal3_mgc,cal4_mgc};
assign		data_in = {	4'h0,3'b0,
						T_CAL	,  //发射通道
                        R_CAL1[0], //接收通道1_1dB
						R_CAL1[1], //接收通道1_2dB
						R_CAL1[2], //接收通道1_4dB
						R_CAL1[3], //接收通道1_8dB
					    R_CAL2[0], //接收通道2_1dB
						R_CAL2[1], //接收通道2_2dB
						R_CAL2[2], //接收通道2_4dB
						R_CAL2[3], //接收通道2_8dB
						R_CAL3[0], //接收通道3_1dB
						R_CAL3[1], //接收通道3_2dB
						R_CAL3[2], //接收通道3_4dB
						R_CAL3[3], //接收通道3_8dB
						R_CAL4   , //
						4'b0   	};
reg [31:0] cnt5us=0;

always@(posedge i_clk)begin
	if(cnt5us==2000)
		cnt5us<=2000;
	else
		cnt5us<=cnt5us+1'b1;
end	

always@(posedge i_clk or negedge i_rstn)begin
if(!i_rstn)
    R_CAL_F 	<= 1'b0;
else 
	R_CAL_F 	<= CAL_F;
end

always@(posedge i_clk or negedge i_rstn)begin
	if(!i_rstn)
		tx_en<=1'b0;
	else if(cnt5us==1999)
		tx_en<=1'b1;
	else if({R_CAL_F,CAL_F}==2'b01 ||  cal_mgc_rr!=cal_mgc_r)
		tx_en<=1'b1;
	else
		tx_en<=1'b0;
end


	
R_CAL_1 R_CAL_1 (
    .i_clk(i_clk), 
    .i_rstn(i_rstn), 
    .i_temp(i_temp), 
    .fre_mode(fre_mode), 
    .R_CAL(R_CAL1_r)
    );

R_CAL_2 R_CAL_2 (
    .i_clk(i_clk), 
    .i_rstn(i_rstn), 
    .i_temp(i_temp), 
    .fre_mode(fre_mode), 
    .R_CAL(R_CAL2_r)
    );

R_CAL_3 R_CAL_3 (
    .i_clk(i_clk), 
    .i_rstn(i_rstn), 
    .i_temp(i_temp), 
    .fre_mode(fre_mode), 
    .R_CAL(R_CAL3_r)
    );

R_CAL_4 R_CAL_4 (
    .i_clk(i_clk), 
    .i_rstn(i_rstn), 
    .i_temp(i_temp), 
    .fre_mode(fre_mode), 
    .R_CAL(R_CAL4_r)
    );


T_CAL T_CAL__ (
    .i_clk(i_clk), 
    .i_rstn(i_rstn), 
    .SW(SW), 
    .i_temp(i_temp), 
    .hop_fre_mode(hop_fre_mode), 
    .T_CAL_(T_CAL_r)
    );


spi_tx SPI_TX (
    .clk		(i_clk			)	, 
    .rstn		(i_rstn			)	, 
    .tx_en		(tx_en			)	, 
    .data_in	(data_in		)	, 
    .spi_cs		(ENABLE			)	, 
    .spi_sclk	(SC				)	, 
    .spi_sdo	(SD				)	,
    .DARY		(END_SYN		)		
    );

















endmodule