****** Vivado v2019.1.3 (64-bit)
  **** SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
  **** IP Build 2633630 on Wed Sep  4 12:30:14 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source axi_dmac_ip.tcl
# source ../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
##   set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
###           DEV_PACKAGE \
###           SPEED_GRADE \
###           FPGA_FAMILY \
###           FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
###           FPGA_VOLTAGE \
###           XCVR_TYPE }
### set fpga_technology_list { \
###         { Unknown     0 } \
###         { 7series     1 } \
###         { ultrascale  2 } \
###         { ultrascale+ 3 }}
### set fpga_family_list { \
###         { Unknown 0 } \
###         { artix   1 } \
###         { kintex  2 } \
###         { virtex  3 } \
###         { zynq    4 }}
### set speed_grade_list { \
###         { Unknown 0  } \
###         { -1      10 } \
###         { -1L     11 } \
###         { -1H     12 } \
###         { -1HV    13 } \
###         { -1LV    14 } \
###         { -2      20 } \
###         { -2L     21 } \
###         { -2LV    22 } \
###         { -3      30 }}
### set dev_package_list { \
###         { Unknown 0  } \
###         { rf      1  } \
###         { fl      2  } \
###         { ff      3  } \
###         { fb      4  } \
###         { hc      5  } \
###         { fh      6  } \
###         { cs      7  } \
###         { cp      8  } \
###         { ft      9  } \
###         { fg      10 } \
###         { sb      11 } \
###         { rb      12 } \
###         { rs      13 } \
###         { cl      14 } \
###         { sf      15 } \
###         { ba      16 } \
###         { fa      17 } \
###         { fs      18 } \
###         { fi      19 }}
### set xcvr_type_list { \
###         { Unknown             0 } \
###         { GTPE2_NOT_SUPPORTED 1 } \
###         { GTXE2               2 } \
###         { GTHE2_NOT_SUPPORTED 3 } \
###         { GTZE2_NOT_SUPPORTED 4 } \
###         { GTHE3               5 } \
###         { GTYE3_NOT_SUPPORTED 6 } \
###         { GTRE4_NOT_SUPPORTED 7 } \
###         { GTHE4               8 } \
###         { GTYE4               9 } \
###         { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
### 
###   set list_pointer [string tolower $param]
###   set list_pointer [append list_pointer "_list"]
### 
###   upvar 1 $list_pointer $list_pointer
### 
###   set ip [get_bd_cells $cellpath]
###   set part [get_property PART [current_project]]
### 
###   switch -regexp -- $param {
###       FPGA_TECHNOLOGY {
###           switch  -regexp -- $part {
###              ^xc7    {set series_name 7series}
###              ^xczu   {set series_name ultrascale+}
###              ^xc.u.p {set series_name ultrascale+}
###              ^xc.u   {set series_name ultrascale }
###              default {
###                  puts "Undefined fpga technology for \"$part\"!"
###                  exit -1
###              }
###           }
###           return "$series_name"
###       }
###       FPGA_FAMILY {
###           set fpga_family [get_property FAMILY $part]
###           foreach i $fpga_family_list {
###               regexp ^[lindex $i 0] $fpga_family matched
###           }
###           return "$matched"
###       }
###       SPEED_GRADE {
###           set speed_grade [get_property SPEED $part]
###           return "$speed_grade"
###       }
###       DEV_PACKAGE {
###           set dev_package [get_property PACKAGE $part]
###           foreach i $dev_package_list {
###               regexp ^[lindex $i 0] $dev_package matched
###           }
###           return "$matched"
###       }
###       XCVR_TYPE {
###           set matched ""
###           set dev_transcivers "none"
###           foreach x [list_property $part] {
###               regexp ^GT..._TRANSCEIVERS $x dev_transcivers
###           }
###           foreach i $xcvr_type_list {
###               regexp ^[lindex $i 0] $dev_transcivers matched
###           }
###           if { $matched eq "" } {
###                puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
###           }
###           return "$matched"
###       }
###       FPGA_VOLTAGE {
###           set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### 	  set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
### 
###           return "$fpga_voltage"
###       }
###       default {
###           puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
###       }
###   }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
##   set REQUIRED_VIVADO_VERSION "2019.1"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
##   set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
##   set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
## 
##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
##   set f [ipx::add_file $ip_constr_files $proj_filegroup]
##   set_property -dict [list \
##     type ttcl \
##   ] $f
##   ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
## 
##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
##   set f [ipx::add_file $ip_files $proj_filegroup]
##   set_property -dict [list \
##     type ttcl \
##   ] $f
##   ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
##   set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
##   if {$proj_filegroup == {}} {
##     set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
##   }
## 
##   foreach file $ip_bd_files {
##     set f [ipx::add_file $file $proj_filegroup]
##     set_property -dict [list \
##       type tclSource \
##     ] $f
##   }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
## 
##   ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
## 
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
## 
##   ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
## 
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
##   foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
##     set_property ENABLEMENT_DEPENDENCY $dependency $port
##     if {$driver_value != {}} {
##       set_property DRIVER_VALUE $driver_value $port
##     }
##   }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
##   set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
##   adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
##   set map [ipx::add_port_map $phys $bus]
##   set_property "PHYSICAL_NAME" $phys $map
##   set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
##   set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
## 
##   set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
##   set_property "BUS_TYPE_VLNV" $bus_type $bus
##   set_property "INTERFACE_MODE" $mode $bus
## 
##   foreach port_map $port_maps {
##     adi_add_port_map $bus {*}$port_map
##   }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
##   for {set i 0} {$i < $num} {incr i} {
##     set bus_name [format "%s%d" $bus_name_prefix $i]
##     set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
## 
##     set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
##     set_property "BUS_TYPE_VLNV" $bus_type $bus
##     set_property "INTERFACE_MODE" $mode $bus
## 
##     if {$dependency ne ""} {
##       set bus_dependency [string map [list "{i}" $i] $dependency]
##       set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
##     }
## 
##     foreach port_map $port_maps {
##       lassign $port_map phys logic width width_dep
##       set map [ipx::add_port_map $phys $bus]
##       set_property "PHYSICAL_NAME" $phys $map
##       set_property "LOGICAL_NAME" $logic $map
##       set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
##       set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
##       if {$width_dep ne ""} {
##         set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
##         set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
##         set width_dep_r "(($width_dep) * $i)"
##         set width_dep_l "(($width_dep) * ($i + 1)-1)"
##         set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
##         set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
##       }
##     }
##   }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
##   set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
##   set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
##   set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
##   set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
##   set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
##   set_property display_name $clock_inf_name $clock_inf
##   set clock_map [ipx::add_port_map "CLK" $clock_inf]
##   set_property physical_name $clock_signal_name $clock_map
## 
##   set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
##   set_property value $bus_inf_name $assoc_busif
## 
##   if { $reset_signal_name != "" } {
##     set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
##     set_property value $reset_signal_name $assoc_reset
## 
##     set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
##     set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
##     set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
##     set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
##     set_property display_name $reset_inf_name $reset_inf
##     set_property interface_mode $reset_signal_mode $reset_inf
##     set reset_map [ipx::add_port_map "RST" $reset_inf]
##     set_property physical_name $reset_signal_name $reset_map
## 
##     set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
##     if {[string match {*[Nn]} $reset_signal_name] == 1} {
##       set_property value "ACTIVE_LOW" $reset_polarity
##     } else {
##       set_property value "ACTIVE_HIGH" $reset_polarity
##     }
##   }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
##   foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
##     foreach vlnv $vlnvs {
##       ipx::add_subcore $vlnv $file_group
##     }
##   }
## }
## proc adi_ip_create {ip_name} {
## 
##   global ad_hdl_dir
##   global ad_ghdl_dir
##   global REQUIRED_VIVADO_VERSION
##   global IGNORE_VERSION_CHECK
## 
##   set VIVADO_VERSION [version -short]
##   if {$IGNORE_VERSION_CHECK} {
##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
##       puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
##       puts -nonewline "got $VIVADO_VERSION.\n"
##     }
##   } else {
##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
##       puts -nonewline "ERROR: vivado version mismatch; "
##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
##       puts -nonewline "got $VIVADO_VERSION.\n"
##       puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
##       exit 2
##     }
##   }
## 
##   create_project $ip_name . -force
## 
##   ## Load custom message severity definitions
##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
## 
##   set lib_dirs $ad_hdl_dir/library
##   if {$ad_hdl_dir ne $ad_ghdl_dir} {
##     lappend lib_dirs $ad_ghdl_dir/library
##   }
## 
##   set_property ip_repo_paths $lib_dirs [current_fileset]
##   update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
##   set proj_fileset [get_filesets sources_1]
##   foreach m_file $ip_files {
##     if {[file extension $m_file] eq ".xdc"} {
##       add_files -norecurse -fileset constrs_1 $m_file
##     } else {
##       add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
##     }
##   }
##   set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
## 
##   global ad_hdl_dir
## 
##   ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
## 
##   set_property name $ip_name [ipx::current_core]
## 
##   set_property vendor_display_name {Analog Devices} [ipx::current_core]
##   set_property company_url {http://www.analog.com} [ipx::current_core]
## 
##   set i_families ""
##   foreach i_part [get_parts] {
##     lappend i_families [get_property FAMILY $i_part]
##   }
##   set i_families [lsort -unique $i_families]
##   set s_families [get_property supported_families [ipx::current_core]]
##   foreach i_family $i_families {
##     set s_families "$s_families $i_family Production"
##     set s_families "$s_families $i_family Beta"
##   }
##   set_property supported_families $s_families [ipx::current_core]
## 
##   ipx::save_core [ipx::current_core]
## 
##   ipx::remove_all_bus_interface [ipx::current_core]
##   set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
##   foreach map $memory_maps {
##     ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
##   }
## 
##   ipx::update_checksums [ipx::current_core]
##   ipx::save_core [ipx::current_core]
## }
## proc adi_ip_properties {ip_name} {
## 
##   adi_ip_properties_lite $ip_name
## 
##   ipx::infer_bus_interface {\
##     s_axi_awvalid \
##     s_axi_awaddr \
##     s_axi_awprot \
##     s_axi_awready \
##     s_axi_wvalid \
##     s_axi_wdata \
##     s_axi_wstrb \
##     s_axi_wready \
##     s_axi_bvalid \
##     s_axi_bresp \
## 
##     s_axi_bready \
##     s_axi_arvalid \
##     s_axi_araddr \
##     s_axi_arprot \
##     s_axi_arready \
##     s_axi_rvalid \
##     s_axi_rdata \
##     s_axi_rresp \
##     s_axi_rready} \
##   xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
## 
##   ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
##   ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
## 
##   set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
##   set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
## 
##   if {$raddr_width != $waddr_width} {
##     puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
##     set range 65536
##   } else {
##     if {$raddr_width >= 16} {
##       set range 65536
##     } else {
##       set range [expr 1 << $raddr_width]
##     }
##   }
## 
##   ipx::add_memory_map {s_axi} [ipx::current_core]
##   set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
##   ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
##   set_property range $range [ipx::get_address_blocks axi_lite \
##     -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
##   ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
##   ipx::save_core
## }
## proc adi_init_bd_tcl {} {
## 
##   global auto_set_param_list
##   global auto_set_param_list_overwritable
##   set cc [ipx::current_core]
## 
##   if { [file exists bd] } {
##     file delete -force bd
##   }
##   file mkdir bd
## 
##   set bd_tcl [open "bd/bd.tcl" w]
## 
##   puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
##   puts $bd_tcl "proc init {cellpath otherInfo} {"
##   puts $bd_tcl "  set ip \[get_bd_cells \$cellpath\]"
##   puts $bd_tcl ""
##   set auto_set_param ""
##   foreach i $auto_set_param_list {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
##       append auto_set_param "    $i \\\n"
##     }
##   }
##   if { $auto_set_param ne "" } {
##     puts $bd_tcl "  bd::mark_propagate_only \$ip \" \\"
##     regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
##     puts $bd_tcl $auto_set_param
##   }
## 
##   set auto_set_overwritable_param ""
##   foreach i $auto_set_param_list_overwritable {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
##       append auto_set_overwritable_param "    $i \\\n"
##     }
##   }
##   if { $auto_set_overwritable_param ne "" } {
##     puts $bd_tcl "  bd::mark_propagate_override \$ip \" \\"
##     regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
##     puts $bd_tcl $auto_set_overwritable_param
##   }
##   puts $bd_tcl "  adi_auto_assign_device_spec \$cellpath"
##   puts $bd_tcl "}"
##   puts $bd_tcl ""
##   puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
##   puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
##   puts $bd_tcl ""
##   puts $bd_tcl "  set ip \[get_bd_cells \$cellpath\]"
##   puts $bd_tcl "  set ip_param_list \[list_property \$ip\]"
##   puts $bd_tcl "  set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
##   puts $bd_tcl ""
##   puts $bd_tcl "  set parent_dir \"../\""
##   puts $bd_tcl "  for {set x 1} {\$x<=4} {incr x} {"
##   puts $bd_tcl "    set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
##   puts $bd_tcl "    if { \[file exists \$linkname\] } {"
##   puts $bd_tcl "      source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
##   puts $bd_tcl "      break"
##   puts $bd_tcl "    }"
##   puts $bd_tcl "    append parent_dir \"../\""
##   puts $bd_tcl "  }"
##   puts $bd_tcl ""
##   puts $bd_tcl "  # Find predefindes auto assignable parameters"
##   puts $bd_tcl "  foreach i \$auto_set_param_list {"
##   puts $bd_tcl "    if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
##   puts $bd_tcl "      set val \[adi_device_spec \$cellpath \$i\]"
##   puts $bd_tcl "      set_property CONFIG.\$i \$val \$ip"
##   puts $bd_tcl "    }"
##   puts $bd_tcl "  }"
##   puts $bd_tcl ""
##   puts $bd_tcl "  # Find predefindes auto assignable/overwritable parameters"
##   puts $bd_tcl "  foreach i \$auto_set_param_list_overwritable {"
##   puts $bd_tcl "    if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
##   puts $bd_tcl "      set val \[adi_device_spec \$cellpath \$i\]"
##   puts $bd_tcl "      set_property CONFIG.\$i \$val \$ip"
##   puts $bd_tcl "    }"
##   puts $bd_tcl "  }"
##   puts $bd_tcl "}"
##   puts $bd_tcl ""
##   close $bd_tcl
## 
##   set proj_fileset [get_filesets sources_1]
##   add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
## 
##   set local_mk [open "temporary_case_dependencies.mk" w]
##   seek $local_mk 0 start
##   puts $local_mk "CLEAN_TARGET += bd"
##   puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
##   close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
## 
##   global auto_set_param_list
##   global auto_set_param_list_overwritable
##   set cc [ipx::current_core]
## 
##   foreach i $auto_set_param_list {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
##       adi_add_device_spec_param $i
##     }
##   }
##   foreach i $auto_set_param_list_overwritable {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
##       adi_add_device_spec_param $i
##     }
##   }
## }
## proc adi_add_device_spec_param {ip_param} {
## 
##   set cc [ipx::current_core]
## 
##   set list_pointer [string tolower $ip_param]
##   set list_pointer [append list_pointer "_list"]
## 
##   global $list_pointer
## 
##   # set j 1D list from the original list
##   foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
## 
##   # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
##   if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
##     set_property -dict [list \
##       "value_validation_type" "range_long" \
##       "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
##       "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
##     [ipx::get_user_parameters $ip_param -of_objects $cc]
##   } else {
##     set_property -dict [list \
##       "value_validation_type" "pairs" \
##       "value_validation_pairs" $j ] \
##     [ipx::get_user_parameters $ip_param -of_objects $cc]
##   }
## 
##   # FPGA info grup
##   set info_group_name "FPGA info"
##   set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
##   if { [string trim $info_group] eq "" } {
##     set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
##     set info_group [ipgui::add_group -name $info_group_name -component $cc \
##         -parent $page0 -display_name $info_group_name]
##   }
## 
##   set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
##   set_property -dict [list "widget" "comboBox" ] $p
##   ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
## 
##   ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
##   ipx::create_bus_definition analog.com interface $name 1.0
## 
##   set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
##   set_property xml_file_name ${name}.xml [ipx::current_busdef]
##   set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
## 
##   ipx::save_abstraction_definition [ipx::current_busabs]
##   ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
## 
##   ipx::add_bus_abstraction_port $name [ipx::current_busabs]
##   set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
##   set_property master_presence required $m_intf
##   set_property slave_presence  required $m_intf
##   set_property master_width $width $m_intf
##   set_property slave_width  $width $m_intf
## 
##   set m_dir "in"
##   set s_dir "out"
##   if {$dir eq "output"} {
##     set m_dir "out"
##     set s_dir "in"
##   }
## 
##   set_property master_direction $m_dir $m_intf
##   set_property slave_direction  $s_dir $m_intf
## 
##   if {$type ne "none"} {
##     set_property is_${type} true $m_intf
##   }
## 
##   ipx::save_bus_definition [ipx::current_busdef]
##   ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
## 
##   ipx::add_bus_interface $name [ipx::current_core]
##   set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
##   set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
##   set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
##   set_property interface_mode $mode $m_bus_if
## 
##   foreach map $maps  {
##     set m_maps [regexp -all -inline {\S+} $map]
##     lassign $m_maps p_name p_map
##     ipx::add_port_map $p_name $m_bus_if
##     set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
##   }
## }
# adi_ip_create axi_dmac
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'.)
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
# adi_ip_files axi_dmac [list \
#   "$ad_hdl_dir/library/common/ad_mem_asym.v" \
#   "$ad_hdl_dir/library/common/up_axi.v" \
#   "inc_id.vh" \
#   "resp.vh" \
#   "axi_dmac_burst_memory.v" \
#   "axi_dmac_regmap.v" \
#   "axi_dmac_regmap_request.v" \
#   "axi_dmac_reset_manager.v" \
#   "axi_dmac_resize_dest.v" \
#   "axi_dmac_resize_src.v" \
#   "axi_dmac_response_manager.v" \
#   "axi_dmac_transfer.v" \
#   "address_generator.v" \
#   "data_mover.v" \
#   "request_arb.v" \
#   "request_generator.v" \
#   "response_handler.v" \
#   "axi_register_slice.v" \
#   "2d_transfer.v" \
#   "dest_axi_mm.v" \
#   "dest_axi_stream.v" \
#   "dest_fifo_inf.v" \
#   "src_axi_mm.v" \
#   "src_axi_stream.v" \
#   "src_fifo_inf.v" \
#   "splitter.v" \
#   "response_generator.v" \
#   "axi_dmac.v" \
#   "axi_dmac_constr.ttcl" \
#   "axi_dmac_pkg_sv.ttcl" \
#   "bd/bd.tcl" ]
# adi_ip_properties axi_dmac
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/axi_dmac_constr.ttcl' ignored by IP packager.
WARNING: [IP_Flow 19-5226] Project source file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac/axi_dmac_pkg_sv.ttcl' ignored by IP packager.
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/ad_mem_asym.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_dmac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_request_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_data_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_address_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'dest_response_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_request_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_data_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_address_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'src_response_id' has a dependency on the module local parameter or undefined parameter 'ID_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_req_measured_burst_length' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BURST_WIDTH'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_dma_req_dest_address' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BEAT_WIDTH_DEST'.
WARNING: [IP_Flow 19-587] [HDL Parser] HDL port or parameter 'up_dma_req_src_address' has a dependency on the module local parameter or undefined parameter 'BYTES_PER_BEAT_WIDTH_SRC'.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "inc_id.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "resp.vh" from the top-level HDL file.
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_wr_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'analog.com:interface:fifo_wr:1.0' (from User Repositories).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_dest_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_src_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_dest_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_src_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_rd': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'fifo_wr': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axis_data' and definition port 'DATA'.
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 's_axis': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_wr_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'fifo_rd_clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'fifo_wr_clk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'm_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 's_axis_aclk': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'bd/bd.tcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qkintexu.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qkintexu.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qkintexuplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qkintexuplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qrkintexu.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qrkintexu.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qvirtexuplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qvirtexuplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  qzynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  zynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  zynquplusRFSOC.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
# adi_ip_infer_mm_interfaces axi_dmac
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi' of definition 'xilinx.com:interface:aximm:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_rd_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'fifo_wr_clk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_dest_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_src_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_dest_axi': References existing address space 'm_dest_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_src_axi': References existing address space 'm_src_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_dest_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_src_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_dest_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_src_axi_aresetn'.
# adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
# adi_ip_sim_ttcl axi_dmac "axi_dmac_pkg_sv.ttcl"
# adi_ip_bd axi_dmac "bd/bd.tcl"
# adi_ip_add_core_dependencies { \
# 	analog.com:user:util_axis_fifo:1.0 \
# 	analog.com:user:util_cdc:1.0 \
# }
# set_property display_name "ADI AXI DMA Controller" [ipx::current_core]
# set_property description "ADI AXI DMA Controller" [ipx::current_core]
# adi_add_bus "s_axis" "slave" \
# 	"xilinx.com:interface:axis_rtl:1.0" \
# 	"xilinx.com:interface:axis:1.0" \
# 	[list {"s_axis_ready" "TREADY"} \
# 	  {"s_axis_valid" "TVALID"} \
# 	  {"s_axis_data" "TDATA"} \
# 	  {"s_axis_strb" "TSTRB"} \
# 	  {"s_axis_keep" "TKEEP"} \
# 	  {"s_axis_user" "TUSER"} \
# 	  {"s_axis_id" "TID"} \
# 	  {"s_axis_dest" "TDEST"} \
# 	  {"s_axis_last" "TLAST"}]
# adi_add_bus_clock "s_axis_aclk" "s_axis"
# adi_add_bus "m_axis" "master" \
# 	"xilinx.com:interface:axis_rtl:1.0" \
# 	"xilinx.com:interface:axis:1.0" \
# 	[list {"m_axis_ready" "TREADY"} \
# 	  {"m_axis_valid" "TVALID"} \
# 	  {"m_axis_data" "TDATA"} \
# 	  {"m_axis_strb" "TSTRB"} \
# 	  {"m_axis_keep" "TKEEP"} \
# 	  {"m_axis_user" "TUSER"} \
# 	  {"m_axis_id" "TID"} \
# 	  {"m_axis_dest" "TDEST"} \
# 	  {"m_axis_last" "TLAST"}]
# adi_add_bus_clock "m_axis_aclk" "m_axis"
# adi_set_bus_dependency "m_src_axi" "m_src_axi" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 0)"
# adi_set_bus_dependency "m_dest_axi" "m_dest_axi" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 0)"
# adi_set_bus_dependency "s_axis" "s_axis" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 1)"
# adi_set_bus_dependency "m_axis" "m_axis" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 1)"
# adi_set_ports_dependency "fifo_rd" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
# adi_set_ports_dependency "dest_diag_level_bursts" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF')) = 1)"
# set dummy_axi_ports [list \
# 	"m_dest_axi_arvalid" \
# 	"m_dest_axi_arready" \
# 	"m_dest_axi_araddr" \
# 	"m_dest_axi_arlen" \
# 	"m_dest_axi_arsize" \
# 	"m_dest_axi_arburst" \
# 	"m_dest_axi_arcache" \
# 	"m_dest_axi_arprot" \
# 	"m_dest_axi_rready" \
# 	"m_dest_axi_rvalid" \
# 	"m_dest_axi_rresp" \
# 	"m_dest_axi_rdata" \
# 	"m_src_axi_awvalid" \
# 	"m_src_axi_awready" \
# 	"m_src_axi_awvalid" \
# 	"m_src_axi_awaddr" \
# 	"m_src_axi_awlen" \
# 	"m_src_axi_awsize" \
# 	"m_src_axi_awburst" \
# 	"m_src_axi_awcache" \
# 	"m_src_axi_awprot" \
# 	"m_src_axi_wvalid" \
# 	"m_src_axi_wready" \
# 	"m_src_axi_wvalid" \
# 	"m_src_axi_wdata" \
# 	"m_src_axi_wstrb" \
# 	"m_src_axi_wlast" \
# 	"m_src_axi_bready" \
# 	"m_src_axi_bvalid" \
# 	"m_src_axi_bresp" \
# ]
# lappend dummy_axi_ports \
# 	"m_dest_axi_awid" \
# 	"m_dest_axi_awlock" \
# 	"m_dest_axi_wid" \
# 	"m_dest_axi_bid" \
# 	"m_dest_axi_arid" \
# 	"m_dest_axi_arlock" \
# 	"m_dest_axi_rid" \
# 	"m_dest_axi_rlast" \
# 	"m_src_axi_arid" \
# 	"m_src_axi_arlock" \
# 	"m_src_axi_rid" \
# 	"m_src_axi_awid" \
# 	"m_src_axi_awlock" \
# 	"m_src_axi_wid" \
# 	"m_src_axi_bid"
# foreach p $dummy_axi_ports {
# 	adi_set_ports_dependency $p "false"
# }
# set_property master_address_space_ref m_dest_axi \
#     [ipx::get_bus_interfaces m_dest_axi \
#     -of_objects [ipx::current_core]]
# set_property master_address_space_ref m_src_axi \
#     [ipx::get_bus_interfaces m_src_axi \
#     -of_objects [ipx::current_core]]
# adi_add_bus "fifo_wr" "slave" \
# 	"analog.com:interface:fifo_wr_rtl:1.0" \
# 	"analog.com:interface:fifo_wr:1.0" \
# 	{ \
# 		{"fifo_wr_en" "EN"} \
# 		{"fifo_wr_din" "DATA"} \
# 		{"fifo_wr_overflow" "OVERFLOW"} \
# 		{"fifo_wr_sync" "SYNC"} \
# 		{"fifo_wr_xfer_req" "XFER_REQ"} \
# 	}
# adi_add_bus_clock "fifo_wr_clk" "fifo_wr"
# adi_set_bus_dependency "fifo_wr" "fifo_wr" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 2)"
# adi_add_bus "fifo_rd" "slave" \
# 	"analog.com:interface:fifo_rd_rtl:1.0" \
# 	"analog.com:interface:fifo_rd:1.0" \
# 	{
# 		{"fifo_rd_en" "EN"} \
# 		{"fifo_rd_dout" "DATA"} \
# 		{"fifo_rd_valid" "VALID"} \
# 		{"fifo_rd_underflow" "UNDERFLOW"} \
# 	}
# adi_add_bus_clock "fifo_rd_clk" "fifo_rd"
# adi_set_bus_dependency "fifo_rd" "fifo_rd" \
# 	"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
# foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" \
#   "s_axis_valid" "s_axis_data" "s_axis_last" "m_axis_ready" \
#   "fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} {
# 	set_property DRIVER_VALUE "0" [ipx::get_ports $port]
# }
# foreach port {"s_axis_user" "fifo_wr_sync"} {
# 	set_property DRIVER_VALUE "1" [ipx::get_ports $port]
# }
# ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
INFO: [IP_Flow 19-5107] Inferred bus interface 'irq' of definition 'xilinx.com:signal:interrupt:1.0' (from TCL Argument).
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
# set cc [ipx::current_core]
# foreach intf [ipx::get_bus_interfaces m_*_axi -of_objects $cc] {
# 	set para [ipx::add_bus_parameter SUPPORTS_NARROW_BURST $intf]
# 	set_property "VALUE" "0" $para
# }
# set_property -dict [list \
# 	"value_validation_type" "list" \
# 	"value_validation_list" "2 4 8 16 32" \
#  ] \
#  [ipx::get_user_parameters FIFO_SIZE -of_objects $cc]
# set_property -dict [list \
# 	"value_validation_type" "range_long" \
# 	"value_validation_range_minimum" "8" \
# 	"value_validation_range_maximum" "32" \
# 	] \
# 	[ipx::get_user_parameters DMA_LENGTH_WIDTH -of_objects $cc]
# foreach {k v} { \
# 		"ASYNC_CLK_REQ_SRC" "true" \
# 		"ASYNC_CLK_SRC_DEST" "true" \
# 		"ASYNC_CLK_DEST_REQ" "true" \
# 		"CYCLIC" "false" \
# 		"DMA_2D_TRANSFER" "false" \
# 		"SYNC_TRANSFER_START" "false" \
# 		"AXI_SLICE_SRC" "false" \
# 		"AXI_SLICE_DEST" "false" \
# 		"DISABLE_DEBUG_REGISTERS" "false" \
#     "ENABLE_DIAGNOSTICS_IF" "false" \
# 	} { \
# 	set_property -dict [list \
# 			"value_format" "bool" \
# 			"value" $v \
# 		] \
# 		[ipx::get_user_parameters $k -of_objects $cc]
# 	set_property -dict [list \
# 			"value_format" "bool" \
# 			"value" $v \
# 		] \
# 		[ipx::get_hdl_parameters $k -of_objects $cc]
# }
# set_property -dict [list \
# 	"enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \
# ] \
# [ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc]
# foreach dir {"SRC" "DEST"} {
# 	set_property -dict [list \
# 		"value_validation_type" "list" \
# 		"value_validation_list" "16 32 64 128 256 512 1024" \
# 	] \
# 	[ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc]
# 
# 	set_property -dict [list \
# 		"value_validation_type" "pairs" \
# 		"value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \
# 		"enablement_tcl_expr" "\$DMA_TYPE_${dir} == 0" \
# 	] \
# 	[ipx::get_user_parameters DMA_AXI_PROTOCOL_${dir} -of_objects $cc]
# 
# 	set_property -dict [list \
# 		"value_validation_type" "pairs" \
# 		"value_validation_pairs" { \
# 			"Memory-Mapped AXI" "0" \
# 			"Streaming AXI" "1" \
# 			"FIFO Interface" "2" \
# 		} \
# 	] \
# 	[ipx::get_user_parameters DMA_TYPE_${dir} -of_objects $cc]
# }
# set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# set g [ipgui::add_group -name {DMA Endpoint Configuration} -component $cc \
# 		-parent $page0 -display_name {DMA Endpoint Configuration} \
# 		-layout "horizontal"]
# set src_group [ipgui::add_group -name {Source} -component $cc -parent $g \
# 		-display_name {Source}]
# set dest_group [ipgui::add_group -name {Destination} -component $cc -parent $g \
# 		-display_name {Destination}]
# foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] {
# 	set p [ipgui::get_guiparamspec -name "DMA_TYPE_${dir}" -component $cc]
# 	ipgui::move_param -component $cc -order 0 $p -parent $group
# 	set_property -dict [list \
# 			"widget" "comboBox" \
# 			"display_name" "Type" \
# 		] $p
# 
# 	set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_${dir}" -component $cc]
# 	ipgui::move_param -component $cc -order 1 $p -parent $group
# 	set_property -dict [list \
# 		"widget" "comboBox" \
# 		"display_name" "AXI Protocol" \
# 	] $p
# 
# 	set p [ipgui::get_guiparamspec -name "DMA_DATA_WIDTH_${dir}" -component $cc]
# 	ipgui::move_param -component $cc -order 2 $p -parent $group
# 	set_property -dict [list \
# 		"display_name" "Bus Width" \
# 	] $p
# 
# 	set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc]
# 	ipgui::move_param -component $cc -order 3 $p -parent $group
# 	set_property -dict [list \
# 		"display_name" "Insert Register Slice" \
# 	] $p
# }
# set p [ipgui::get_guiparamspec -name "SYNC_TRANSFER_START" -component $cc]
# ipgui::move_param -component $cc -order 4 $p -parent $src_group
# set_property -dict [list \
# 	"display_name" "Transfer Start Synchronization Support" \
# ] $p
# set general_group [ipgui::add_group -name "General Configuration" -component $cc \
# 		-parent $page0 -display_name "General Configuration"]
# set p [ipgui::get_guiparamspec -name "ID" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $general_group
# set_property -dict [list \
# 	"display_name" "Core ID" \
# ] $p
# set p [ipgui::get_guiparamspec -name "DMA_LENGTH_WIDTH" -component $cc]
# ipgui::move_param -component $cc -order 1 $p -parent $general_group
# set_property -dict [list \
# 	"display_name" "DMA Transfer Length Register Width" \
# ] $p
# set p [ipgui::get_guiparamspec -name "FIFO_SIZE" -component $cc]
# ipgui::move_param -component $cc -order 2 $p -parent $general_group
# set_property -dict [list \
# 	"widget" "comboBox" \
# 	"display_name" "Store-and-Forward Memory Size (In Bursts)" \
# ] $p
# set p [ipgui::get_guiparamspec -name "MAX_BYTES_PER_BURST" -component $cc]
# ipgui::move_param -component $cc -order 3 $p -parent $general_group
# set_property -dict [list \
# 	"display_name" "Maximum Bytes per Burst" \
# ] $p
# set feature_group [ipgui::add_group -name "Features" -component $cc \
# 		-parent $page0 -display_name "Features"]
# set p [ipgui::get_guiparamspec -name "CYCLIC" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $feature_group
# set_property -dict [list \
# 	"display_name" "Cyclic Transfer Support" \
# ] $p
# set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
# ipgui::move_param -component $cc -order 1 $p -parent $feature_group
# set_property -dict [list \
# 	"display_name" "2D Transfer Support" \
# ] $p
# set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \
# 		-parent $page0 -display_name {Clock Domain Configuration}]
# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_REQ_SRC" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $clk_group
# set_property -dict [list \
# 	"display_name" "Request and Source Clock Asynchronous" \
# ] $p
# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_SRC_DEST" -component $cc]
# ipgui::move_param -component $cc -order 1 $p -parent $clk_group
# set_property -dict [list \
# 	"display_name" "Source and Destination Clock Asynchronous" \
# ] $p
# set p [ipgui::get_guiparamspec -name "ASYNC_CLK_DEST_REQ" -component $cc]
# ipgui::move_param -component $cc -order 2 $p -parent $clk_group
# set_property -dict [list \
# 	"display_name" "Destination and Request Clock Asynchronous" \
# ] $p
# set dbg_group [ipgui::add_group -name {Debug} -component $cc \
# 		-parent $page0 -display_name {Debug}]
# set p [ipgui::get_guiparamspec -name "DISABLE_DEBUG_REGISTERS" -component $cc]
# ipgui::move_param -component $cc -order 0 $p -parent $dbg_group
# set_property -dict [list \
# 	"display_name" "Disable Debug Registers" \
# ] $p
# set p [ipgui::get_guiparamspec -name "ENABLE_DIAGNOSTICS_IF" -component $cc]
# ipgui::move_param -component $cc -order 1 $p -parent $dbg_group
# set_property -dict [list \
# 	"display_name" "Enable Diagnostics Interface" \
# ] $p
# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc]
# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc]
# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc]
# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc]
# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_ID_W" -component $cc]
# ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_DEST_W" -component $cc]
# ipx::create_xgui_files [ipx::current_core]
# ipx::save_core $cc
INFO: [Common 17-206] Exiting Vivado at Wed Dec  8 10:23:00 2021...