analog.com user ad_ip_jesd204_tpl_dac 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW link TREADY link_ready TVALID link_valid TDATA link_data link_signal_clock link_signal_clock CLK link_clk ASSOCIATED_BUSIF link s_axi axi_lite 0 8192 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog ad_ip_jesd204_tpl_dac xilinx_anylanguagesynthesis_view_fileset viewChecksum adc151cc xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog ad_ip_jesd204_tpl_dac xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 2093b0ca xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c6e9fb8a xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset link_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation link_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation link_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation link_data out 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_ddata in 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_dunf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_sync_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awaddr in 12 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_araddr in 12 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 NUM_LANES Num Lanes 4 NUM_CHANNELS Num Channels 2 SAMPLES_PER_FRAME Samples Per Frame 1 CONVERTER_RESOLUTION Converter Resolution 16 BITS_PER_SAMPLE Bits Per Sample 16 OCTETS_PER_BEAT Octets Per Beat 4 DDS_TYPE Dds Type 1 DDS_CORDIC_DW Dds Cordic Dw 16 DDS_CORDIC_PHASE_DW Dds Cordic Phase Dw 16 DATAPATH_DISABLE Datapath Disable 0 IQCORRECTION_DISABLE Iqcorrection Disable 1 EXT_SYNC Ext Sync 0 choice_list_6e06e1af 4 8 choice_list_6e77d344 1 2 4 6 8 16 32 64 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_7540484d 8 12 16 choice_list_96dbe929 1 2 3 4 8 16 choice_list_e05731dc 8 11 12 16 choice_list_eace76f4 1 2 3 4 6 8 12 16 choice_pairs_38e7dd38 0 1 2 3 4 choice_pairs_68effc1b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 choice_pairs_978e9846 0 1 choice_pairs_a535243b 0 10 11 12 13 14 20 21 22 30 choice_pairs_aee923ef 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset ../../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../../xilinx/common/ad_rst_constr.xdc xdc ../../xilinx/common/up_xfer_status_constr.xdc xdc ../../xilinx/common/up_clock_mon_constr.xdc xdc ../../common/ad_dds.v verilogSource ../../common/ad_dds_1.v verilogSource ../../common/ad_dds_2.v verilogSource ../../common/ad_dds_cordic_pipe.v verilogSource ../../common/ad_dds_sine.v verilogSource ../../common/ad_dds_sine_cordic.v verilogSource ad_ip_jesd204_tpl_dac_channel.v verilogSource ad_ip_jesd204_tpl_dac_core.v verilogSource ad_ip_jesd204_tpl_dac_framer.v verilogSource ad_ip_jesd204_tpl_dac_pn.v verilogSource ad_ip_jesd204_tpl_dac_regmap.v verilogSource ../../common/ad_iqcor.v verilogSource ../../xilinx/common/ad_mul.v verilogSource ../../common/ad_perfect_shuffle.v verilogSource ../../common/ad_rst.v verilogSource ../../common/up_axi.v verilogSource ../../common/up_clock_mon.v verilogSource ../../common/up_dac_channel.v verilogSource ../../common/up_dac_common.v verilogSource ../ad_ip_jesd204_tpl_common/up_tpl_common.v verilogSource ../../common/up_xfer_cntrl.v verilogSource ../../common/up_xfer_status.v verilogSource ad_ip_jesd204_tpl_dac.v verilogSource CHECKSUM_281a17bc xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_dds.v verilogSource ../../common/ad_dds_1.v verilogSource ../../common/ad_dds_2.v verilogSource ../../common/ad_dds_cordic_pipe.v verilogSource ../../common/ad_dds_sine.v verilogSource ../../common/ad_dds_sine_cordic.v verilogSource ad_ip_jesd204_tpl_dac_channel.v verilogSource ad_ip_jesd204_tpl_dac_core.v verilogSource ad_ip_jesd204_tpl_dac_framer.v verilogSource ad_ip_jesd204_tpl_dac_pn.v verilogSource ad_ip_jesd204_tpl_dac_regmap.v verilogSource ../../common/ad_iqcor.v verilogSource ../../xilinx/common/ad_mul.v verilogSource ../../common/ad_perfect_shuffle.v verilogSource ../../common/ad_rst.v verilogSource ../../common/up_axi.v verilogSource ../../common/up_clock_mon.v verilogSource ../../common/up_dac_channel.v verilogSource ../../common/up_dac_common.v verilogSource ../ad_ip_jesd204_tpl_common/up_tpl_common.v verilogSource ../../common/up_xfer_cntrl.v verilogSource ../../common/up_xfer_status.v verilogSource ad_ip_jesd204_tpl_dac.v verilogSource xilinx_xpgui_view_fileset xgui/ad_ip_jesd204_tpl_dac_v1_0.tcl tclSource CHECKSUM_b05da9e6 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_utilityxitfiles_view_fileset gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl GTCL JESD204 Transport Layer for DACs ID Core ID 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 NUM_LANES Number of Lanes (L) 4 NUM_CHANNELS Number of Conveters (M) 2 SAMPLES_PER_FRAME Samples per Frame (S) 1 CONVERTER_RESOLUTION Converter Resolution (N) 16 BITS_PER_SAMPLE Bits per Sample (N') 16 OCTETS_PER_BEAT Octets per Beat 4 DDS_TYPE DDS Type 1 true DDS_CORDIC_DW CORDIC DDS Data Width 16 true DDS_CORDIC_PHASE_DW CORDIC DDS Phase Width 16 true DATAPATH_DISABLE Disable Datapath 0 IQCORRECTION_DISABLE Disable IQ Correction 1 EXT_SYNC Enable external SYNC 0 Component_Name ad_ip_jesd204_tpl_dac_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices JESD204 Transport Layer for DACs package_project Analog Devices http://www.analog.com 1 2021-12-09T07:08:56Z 2019.1.3