`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/02/23 11:13:17
// Design Name: 
// Module Name: sim_c2c_dma
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sim_c2c_dma(

    );

//*************************Parameter Declarations******************************

parameter   CLK_PERIOD   =   10.41666667;

reg clk;

initial begin
    clk = 1'b1;
end

always  
    #(CLK_PERIOD/2) clk = !clk;

reg rst;
initial begin
     rst = 1'b1;
#(CLK_PERIOD*10)
     rst = 1'b0;		
end  


reg [31:0] c2c_tx_fifo_tdata = 32'd0;
always  
    #(CLK_PERIOD) c2c_tx_fifo_tdata = c2c_tx_fifo_tdata + 32'd1;
    
reg [191:0]c2c_din = 192'hFFFFFFFF_7E7E7E7E_10000207_12345678_9ABCDEFF_FFFFFFFF;
always  
    #(CLK_PERIOD) c2c_din[191:0] = {c2c_din[190:0],1'b0};

c2c_bridge_dma u_c2c_bridge_dma(
    .clk                    (clk                    ), // input clk, 96Mhz
    .rst                    (rst                    ), // input rst, active high
    //interface data                              
    .c2c_clkin              (clk                    ),
    .c2c_clkout             (                       ),
    .c2c_din                (c2c_din[191]           ),
    .c2c_dout               (                       ),
    //dma fifo interface   
    .c2c_tx_fifo_tdata      (c2c_tx_fifo_tdata      ),
    .c2c_tx_fifo_tlast      (1'b1                   ),
    .c2c_tx_fifo_tready     (                       ),
    .c2c_tx_fifo_tvalid     (1'b1                   ),
    
    .c2c_rx_fifo_tdata      (                       ),
    .c2c_rx_fifo_tlast      (                       ),
    .c2c_rx_fifo_tready     (1'b1                   ),
    .c2c_rx_fifo_tvalid     (                       )
);

endmodule