analog.com user cn0363_dma_sequencer 1.0 phase TVALID phase_valid TREADY phase_ready TDATA phase data TVALID data_valid TREADY data_ready TDATA data data_filtered TVALID data_filtered_valid TREADY data_filtered_ready TDATA data_filtered i_q TVALID i_q_valid TREADY i_q_ready TDATA i_q i_q_filtered TVALID i_q_filtered_valid TREADY i_q_filtered_ready TDATA i_q_filtered dma_wr EN dma_wr_en SYNC dma_wr_sync DATA dma_wr_data OVERFLOW dma_wr_overflow XFER_REQ dma_wr_xfer_req phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_clock phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_clock CLK clk ASSOCIATED_BUSIF phase:data:data_filtered:i_q:i_q_filtered:dma_wr ASSOCIATED_RESET processing_resetn phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_reset phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_reset RST processing_resetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog cn0363_dma_sequencer xilinx_anylanguagesynthesis_view_fileset viewChecksum cc522df0 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog cn0363_dma_sequencer xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum cc522df0 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phase in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phase_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phase_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data in 23 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_filtered in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_filtered_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_filtered_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_q in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_q_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_q_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_q_filtered in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_q_filtered_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_q_filtered_ready out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation overflow out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wr_data out 31 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wr_en out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wr_sync out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wr_overflow in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dma_wr_xfer_req in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation channel_enable in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation processing_resetn out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset cn0363_dma_sequencer.v verilogSource CHECKSUM_cc522df0 xilinx_anylanguagebehavioralsimulation_view_fileset cn0363_dma_sequencer.v verilogSource xilinx_xpgui_view_fileset xgui/cn0363_dma_sequencer_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 cn0363_dma_sequencer_v1_0 Component_Name cn0363_dma_sequencer_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices cn0363_dma_sequencer_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:16:56Z 2019.1.3