analog.com user ad_ip_jesd204_tpl_adc 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW link TREADY link_ready TVALID link_valid TDATA link_data link_signal_clock link_signal_clock CLK link_clk ASSOCIATED_BUSIF link s_axi axi_lite 0 8192 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog ad_ip_jesd204_tpl_adc xilinx_anylanguagesynthesis_view_fileset viewChecksum 72f5745e xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog ad_ip_jesd204_tpl_adc xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 403c22a1 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 6db799a7 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset link_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation link_sof in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation link_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation link_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 link_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_dovf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_sync_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_rst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awaddr in 12 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_araddr in 12 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 NUM_LANES Num Lanes 1 NUM_CHANNELS Num Channels 4 SAMPLES_PER_FRAME Samples Per Frame 1 CONVERTER_RESOLUTION Converter Resolution 14 BITS_PER_SAMPLE Bits Per Sample 16 OCTETS_PER_BEAT Octets Per Beat 4 TWOS_COMPLEMENT Twos Complement 1 choice_list_6e06e1af 4 8 choice_list_6e77d344 1 2 4 6 8 16 32 64 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_7540484d 8 12 16 choice_list_96dbe929 1 2 3 4 8 16 choice_list_e05731dc 8 11 12 16 choice_list_eace76f4 1 2 3 4 6 8 12 16 choice_pairs_38e7dd38 0 1 2 3 4 choice_pairs_68effc1b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 choice_pairs_a535243b 0 10 11 12 13 14 20 21 22 30 choice_pairs_aee923ef 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset ../../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../../xilinx/common/ad_rst_constr.xdc xdc ../../xilinx/common/up_xfer_status_constr.xdc xdc ../../xilinx/common/up_clock_mon_constr.xdc xdc ../../common/ad_datafmt.v verilogSource ad_ip_jesd204_tpl_adc_channel.v verilogSource ad_ip_jesd204_tpl_adc_core.v verilogSource ad_ip_jesd204_tpl_adc_deframer.v verilogSource ad_ip_jesd204_tpl_adc_pnmon.v verilogSource ad_ip_jesd204_tpl_adc_regmap.v verilogSource ../../common/ad_perfect_shuffle.v verilogSource ../../common/ad_pnmon.v verilogSource ../../common/ad_rst.v verilogSource ../../common/ad_xcvr_rx_if.v verilogSource ../../common/up_adc_channel.v verilogSource ../../common/up_adc_common.v verilogSource ../../common/up_axi.v verilogSource ../../common/up_clock_mon.v verilogSource ../ad_ip_jesd204_tpl_common/up_tpl_common.v verilogSource ../../common/up_xfer_cntrl.v verilogSource ../../common/up_xfer_status.v verilogSource ad_ip_jesd204_tpl_adc.v verilogSource CHECKSUM_689d6433 xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_datafmt.v verilogSource ad_ip_jesd204_tpl_adc_channel.v verilogSource ad_ip_jesd204_tpl_adc_core.v verilogSource ad_ip_jesd204_tpl_adc_deframer.v verilogSource ad_ip_jesd204_tpl_adc_pnmon.v verilogSource ad_ip_jesd204_tpl_adc_regmap.v verilogSource ../../common/ad_perfect_shuffle.v verilogSource ../../common/ad_pnmon.v verilogSource ../../common/ad_rst.v verilogSource ../../common/ad_xcvr_rx_if.v verilogSource ../../common/up_adc_channel.v verilogSource ../../common/up_adc_common.v verilogSource ../../common/up_axi.v verilogSource ../../common/up_clock_mon.v verilogSource ../ad_ip_jesd204_tpl_common/up_tpl_common.v verilogSource ../../common/up_xfer_cntrl.v verilogSource ../../common/up_xfer_status.v verilogSource ad_ip_jesd204_tpl_adc.v verilogSource xilinx_xpgui_view_fileset xgui/ad_ip_jesd204_tpl_adc_v1_0.tcl tclSource CHECKSUM_811d7f09 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource JESD204 Transport Layer for ADCs ID Core ID 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 NUM_LANES Number of Lanes (L) 1 NUM_CHANNELS Number of Conveters (M) 4 SAMPLES_PER_FRAME Samples per Frame (S) 1 CONVERTER_RESOLUTION Converter Resolution (N) 14 BITS_PER_SAMPLE Bits per Sample (N') 16 OCTETS_PER_BEAT Octets per Beat 4 TWOS_COMPLEMENT Use twos complement 1 Component_Name ad_ip_jesd204_tpl_adc_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices JESD204 Transport Layer for ADCs package_project Analog Devices http://www.analog.com 1 2021-12-08T12:24:32Z 2019.1.3