####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := ad_ip_jesd204_tpl_dac

GENERIC_DEPS += ../../common/ad_dds.v
GENERIC_DEPS += ../../common/ad_dds_1.v
GENERIC_DEPS += ../../common/ad_dds_2.v
GENERIC_DEPS += ../../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../../common/ad_dds_sine.v
GENERIC_DEPS += ../../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../../common/ad_iqcor.v
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += ../../common/up_dac_channel.v
GENERIC_DEPS += ../../common/up_dac_common.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_core.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_framer.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_pn.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_regmap.v

XILINX_DEPS += ../../xilinx/common/ad_mul.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += ad_ip_jesd204_tpl_dac_ip.tcl

INTEL_DEPS += ../../intel/common/ad_mul.v
INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += ad_ip_jesd204_tpl_dac_hw.tcl

include ../../scripts/library.mk