analog.com user util_rfifo 1.0 din_clk CLK din_clk ASSOCIATED_RESET din_rstn dout_clk CLK dout_clk ASSOCIATED_RESET dout_rst din_rstn RST din_rstn POLARITY ACTIVE_LOW dout_rst RST dout_rst xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_rfifo xilinx_anylanguagesynthesis_view_fileset viewChecksum 9092e1b3 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_rfifo xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum adc311cd xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 70b62934 din_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_enable_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_valid_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din_valid_in_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 din_data_0 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 din_enable_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true din_valid_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true din_valid_in_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_1 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_enable_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true din_valid_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true din_valid_in_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_2 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_enable_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true din_valid_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true din_valid_in_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_data_3 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true din_enable_4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_in_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_4 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_enable_5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_in_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_5 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_enable_6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_in_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_6 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_enable_7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false din_valid_in_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_data_7 in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false din_unf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dout_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_enable_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dout_valid_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dout_valid_out_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dout_data_0 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout_enable_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_valid_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_valid_out_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_data_1 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_enable_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_valid_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_valid_out_2 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_data_2 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_enable_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_valid_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_valid_out_3 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dout_data_3 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true dout_enable_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_out_4 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_data_4 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_enable_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_out_5 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_data_5 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_enable_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_out_6 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_data_6 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_enable_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_valid_out_7 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dout_data_7 out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dout_unf out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_CHANNELS Num Of Channels 4 DIN_DATA_WIDTH Din Data Width 32 DOUT_DATA_WIDTH Dout Data Width 64 DIN_ADDRESS_WIDTH Din Address Width 8 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset util_rfifo_constr.xdc xdc ../common/ad_mem.v verilogSource util_rfifo.v verilogSource CHECKSUM_3e63fdd4 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_mem.v verilogSource util_rfifo.v verilogSource xilinx_xpgui_view_fileset xgui/util_rfifo_v1_0.tcl tclSource CHECKSUM_70b62934 XGUI_VERSION_2 util_rfifo_v1_0 NUM_OF_CHANNELS Num Of Channels 4 DIN_DATA_WIDTH Din Data Width 32 DOUT_DATA_WIDTH Dout Data Width 64 DIN_ADDRESS_WIDTH Din Address Width 8 Component_Name util_rfifo_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_rfifo_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:24:13Z 2019.1.3