`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Chengdu Tiger // Engineer: Tangxy // // Create Date: 14:14:49 09/06/2021 // Design Name: // Module Name: top // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Sisyif( input clk_40m , input clk_20m , input rst_n , //调零至信处接口 input SPI_CLK_F ,//SPI控制，时钟暂定50MHz，用来发送跳频频点、发射MGC值、接收MGC值 input SPI_SYN_F ,//片选 input SPI_MOSI_F , output SPI_MISO_F , input TP_EN_F ,//跳频使能控制(上升沿更新) input TR_MGC_F ,//接收发射MGC使能控制(上升沿更新) input CAL_F ,//校准MGC使能(上升沿更新) input PRF ,//高发低收，默认接收 //信处至射频接口 output standby ,//高开低待机，默认待机 output SW_PLL ,//乒乓频率源选择0：频率源A —— 1：频率源B output T ,//发射电源控制 output R ,//接收电源控制 output SW_BPF ,//开关滤波器选择 output SCLK1 ,//锁相环A控制 output SDIO1 ,// output CS1 ,// input LD1 ,// output SCLK2 ,//锁相环B控制 output SDIO2 ,// output CS2 ,// input LD2 ,// output SCLK3 ,//点频源控制 output SDIO3 ,// output CS3 ,// input LD3 ,// output TMGC_16db ,//发射通道MGC控制,高电平衰减 output TMGC_8db ,// output TMGC_4db ,// output TMGC_2db ,// output TMGC_1db ,// output RMGC_16db ,//四个接收通道MGC控制，同时控制，高电平衰减 output RMGC_8db ,// output RMGC_4db ,// output RMGC_2db ,// output RMGC_1db ,// output ENABLE ,//SPI控制四个接收通道增益校准 output SC ,// output SD ,// output END_SYN ,// input SDOUT ,// inout DQ_WD ,//温度传感器 output SW_RX //接收监测控制 ); wire vio_rstn ; wire [9:0] SYNC_OUT ; wire [35:0] CONTROL0 ; wire [35:0] CONTROL1 ; wire [150:0] TRIG0 ; wire[15:0] temp_data ;//LSB =0.625 C wire[7:0] temp ;//LSB =1°C wire[11:0] hop_fre_code; wire adf4371_hop1 ; wire adf4371_hop2 ; wire [15:0] fre_code ; wire [7:0] tx_mgc ; wire [7:0] rx1_mgc ; wire [7:0] rx2_mgc ; wire [7:0] rx3_mgc ; wire [7:0] rx4_mgc ; wire [3:0] cal1_mgc ; wire [3:0] cal2_mgc ; wire [3:0] cal3_mgc ; wire [3:0] cal4_mgc ; wire [7:0] tx_cal_mgc ; wire [3:0] model ; wire [3:0] rf_en ; wire [31:0] frame_count; wire [3:0] ceshi_model; wire [15:0] current_fre_code ; wire [15:0] cal_fre_code ; wire [7:0] R_MGC_1 ; wire SW_C1; wire SW; wire SW2; wire SW3; wire [3:0] R_CAL1; wire [3:0] R_CAL2; wire [3:0] R_CAL3; wire [3:0] R_CAL4; wire [4:0] T_CAL ; assign temp = temp_data[11:4] ; assign RMGC_16db = R_MGC_1[4] ; assign RMGC_8db = R_MGC_1[3] ; assign RMGC_4db = R_MGC_1[2] ; assign RMGC_2db = R_MGC_1[1] ; assign RMGC_1db = R_MGC_1[0] ; assign standby = rf_en == 4'b0 ; assign T = PRF ; assign R = ~PRF ; assign SW_BPF = SW_C1 ; assign SW_PLL = SW ; assign SW_RX = rx2_mgc == 8'b0 ? 1'b0 :1'b1 ; spi_slave u_spi_slave ( .i_sys_clk(clk_40m), .i_sys_rst_n(rst_n), .i_spi_sck(SPI_CLK_F), .i_spi_cs(SPI_SYN_F), .i_spi_sdi(SPI_MOSI_F), .o_frame_count(frame_count), .o_fre_code(fre_code), .o_tx_mgc(tx_mgc), .o_model(model), .o_rf_en(rf_en), .o_cal1_mgc(cal1_mgc), .o_cal2_mgc(cal2_mgc), .o_cal3_mgc(cal3_mgc), .o_cal4_mgc(cal4_mgc), .o_tx_cal_mgc(tx_cal_mgc), .o_rx1_mgc(rx1_mgc), .o_rx2_mgc(rx2_mgc), .o_rx3_mgc(rx3_mgc), .o_rx4_mgc(rx4_mgc), .o_ceshi_model(ceshi_model) ); spi_master u_spi_master ( .i_sys_rst_n (rst_n) , .i_clk (clk_40m) , //.debug_clk (clk_80m) , .i_spi_sck (SPI_CLK_F) , .i_spi_cs (SPI_SYN_F) , .o_spi_sdo (SPI_MISO_F) , .i_spi_sdi (SPI_MOSI_F) , .i_LD_LO3 (LD3) , .i_LD1 (LD1) , .i_LD2 (LD2) , .i_cal1_mgc (R_CAL4) , .i_cal2_mgc (R_CAL3) , .i_cal3_mgc (R_CAL2) , .i_cal4_mgc (R_CAL1) , .i_temp (temp ) , .i_frame_count (frame_count) ); mgc_ctrl u_mgc_ctrl( .i_sys_clk (clk_40m ), .i_rst_n (rst_n ), .i_TR_SW_F (PRF ), .i_TP_EN_F (TP_EN_F ), .i_T_MGC_EN_F (TR_MGC_F ), .i_R_MGC_EN_F (TR_MGC_F ), .i_CAL_F (CAL_F ), .i_fre_code (fre_code ), .i_tx_mgc (tx_mgc ), .i_rx1_mgc (rx1_mgc ), .i_rx2_mgc (rx2_mgc ), .i_rx3_mgc (rx3_mgc ), .i_rx4_mgc (rx4_mgc ), .i_ceshi_module (ceshi_model ), .o_current_fre_code (current_fre_code ), .o_cal_fre_code (cal_fre_code ), .o_hop_fre_code (hop_fre_code ), //0(20.375GHz)~3500(23.875GHz) .o_adf4371_hop1 (adf4371_hop1 ), //high active .o_adf4371_hop2 (adf4371_hop2 ), .o_SW (SW ), .o_SW2 (SW2 ), .o_SW3 (SW3 ), .o_SW_C1 (SW_C1 ), .o_T_MGC_1dB (TMGC_1db ), .o_T_MGC_2dB (TMGC_2db ), .o_T_MGC_4dB (TMGC_4db ), .o_T_MGC_8dB (TMGC_8db ), .o_T_MGC_16dB (TMGC_16db ), .o_R_MGC_1 (R_MGC_1 ) //.o_R_MGC_2 (R_MGC_2 ), //.o_R_MGC_3 (R_MGC_3 ), //.o_R_MGC_4 (R_MGC_4 ) ); wire cfgover; adf4371_a u_adf4371_a ( .sysclk (clk_40m ), .arstn (rst_n&vio_rstn ), .cs (CS1 ), .mux_out (LD1 ), .sclk (SCLK1 ), .sdio (SDIO1 ), .rf_en (rf_en ), .SW_PLL (SW_PLL ), .CAL_F (CAL_F ), .o_cfgover (cfgover ), .ceshi_model(ceshi_model ), .adf4371_hop(adf4371_hop1), .fre_code (hop_fre_code) ); adf4371_b u_adf4371_b ( .sysclk (clk_40m ), .arstn (rst_n&vio_rstn), .cs (CS2 ), .mux_out (LD2 ), .sclk (SCLK2 ), .sdio (SDIO2 ), .rf_en (rf_en ), .SW_PLL (SW_PLL ), .CAL_F (CAL_F ), .i_cfgover (cfgover ), .ceshi_model(ceshi_model ), .adf4371_hop(adf4371_hop2), .fre_code (hop_fre_code) ); fre_caliatt u_fre_caliatt ( .i_clk (clk_40m ), .i_rstn (rst_n ), .ENABLE (ENABLE ), .SC (SC ), .SD (SD ), .END_SYN (END_SYN ), .SDOUT (SDOUT ), .CAL_F (CAL_F ), .i_temp (temp ), .i_fre_mode (current_fre_code ), .i_cal_fre_code (cal_fre_code ), // .SYNC_OUT (SYNC_OUT ), .SW (SW ), .cal1_mgc (cal1_mgc ), .cal2_mgc (cal2_mgc ), .cal3_mgc (cal3_mgc ), .cal4_mgc (cal4_mgc ), .tx_cal_mgc (tx_cal_mgc ), .tx_mgc (tx_mgc ), .i_ceshi_module (ceshi_model ), .R_CAL1 (R_CAL1 ), .R_CAL2 (R_CAL2 ), .R_CAL3 (R_CAL3 ), .R_CAL4 (R_CAL4 ), .T_CAL (T_CAL ) ); adf4351_2 u_adf4351 ( .i_sysclk(clk_20m), .i_arstn(rst_n), .o_ADF4351_SCK(SCLK3), .o_ADF4351_DATA(SDIO3), .o_ADF4351_LE(CS3), .i_ADF4351_locked(LD3) ); ds18b20_temp u_temp ( .clk(clk_40m), .rstn(rst_n), .dq(DQ_WD), .temp_data(temp_data) ); assign vio_rstn = 1'b1; endmodule