analog.com user axi_spdif_rx 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW m_axis TDATA m_axis_tdata TKEEP m_axis_tkeep TLAST m_axis_tlast TVALID m_axis_tvalid TREADY m_axis_tready true dma_req_aclk CLK dma_req_aclk ASSOCIATED_RESET dma_req_rstn m_axis_aclk CLK m_axis_aclk ASSOCIATED_BUSIF m_axis dma_req_rstn RST dma_req_rstn POLARITY ACTIVE_LOW dma_ack TVALID dma_req_davalid TREADY dma_req_daready TUSER dma_req_datype false dma_req TVALID dma_req_drvalid TREADY dma_req_drready TUSER dma_req_drtype TLAST dma_req_drlast false dma_req_dma_ack_signal_clock dma_req_dma_ack_signal_clock CLK dma_req_aclk ASSOCIATED_BUSIF dma_req:dma_ack ASSOCIATED_RESET dma_req_rstn dma_req_dma_ack_signal_reset dma_req_dma_ack_signal_reset RST dma_req_rstn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axi_spdif_rx xilinx_anylanguagesynthesis_view_fileset viewChecksum 2df62c64 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axi_spdif_rx xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 2df62c64 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 8815501a rx_int_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spdif_rx_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spdif_rx_i_dbg out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awaddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tkeep out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dma_req_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dma_req_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false dma_req_davalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_datype in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_daready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drtype out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_drready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false C_S_AXI_DATA_WIDTH C S Axi Data Width 32 C_S_AXI_ADDR_WIDTH C S Axi Addr Width 32 C_DMA_TYPE C Dma Type 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../common/axi_ctrlif.vhd vhdlSource rx_package.vhd vhdlSource ../common/dma_fifo.vhd vhdlSource ../common/axi_streaming_dma_rx_fifo.vhd vhdlSource ../common/pl330_dma_fifo.vhd vhdlSource rx_decode.vhd vhdlSource rx_phase_det.vhd vhdlSource rx_status_reg.vhd vhdlSource axi_spdif_rx.vhd vhdlSource CHECKSUM_9b31708f xilinx_anylanguagebehavioralsimulation_view_fileset ../common/axi_ctrlif.vhd vhdlSource rx_package.vhd vhdlSource ../common/dma_fifo.vhd vhdlSource ../common/axi_streaming_dma_rx_fifo.vhd vhdlSource ../common/pl330_dma_fifo.vhd vhdlSource rx_decode.vhd vhdlSource rx_phase_det.vhd vhdlSource rx_status_reg.vhd vhdlSource axi_spdif_rx.vhd vhdlSource xilinx_xpgui_view_fileset xgui/axi_spdif_rx_v1_0.tcl tclSource CHECKSUM_8815501a XGUI_VERSION_2 axi_spdif_rx_v1_0 C_S_AXI_DATA_WIDTH C S Axi Data Width 32 C_S_AXI_ADDR_WIDTH C S Axi Addr Width 32 C_DMA_TYPE C Dma Type 0 Component_Name axi_spdif_rx_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_spdif_rx_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:16:38Z 2019.1.3