analog.com user util_adcfifo 1.0 adc_clk CLK adc_clk ASSOCIATED_RESET adc_rst adc_rst RST adc_rst dma_clk CLK dma_clk xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_adcfifo xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum a42a85a4 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_adcfifo xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 81b0fb44 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 26128cef adc_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wr in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wdata in 255 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wovf out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wr out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_xfer_req in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_xfer_status out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation FPGA_TECHNOLOGY Fpga Technology 0 ADC_DATA_WIDTH Adc Data Width 256 DMA_DATA_WIDTH Dma Data Width 64 DMA_READY_ENABLE Dma Ready Enable 1 DMA_ADDRESS_WIDTH Dma Address Width 10 xilinx_anylanguagesynthesis_view_fileset util_adcfifo_constr.xdc xdc ../common/ad_axis_inf_rx.v verilogSource ../common/ad_mem_asym.v verilogSource ../common/ad_rst.v verilogSource util_adcfifo.v verilogSource CHECKSUM_59dcc5ef xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_axis_inf_rx.v verilogSource ../common/ad_mem_asym.v verilogSource ../common/ad_rst.v verilogSource util_adcfifo.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/util_adcfifo_v1_0.tcl tclSource CHECKSUM_26128cef XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset util_adcfifo_v1_0 FPGA_TECHNOLOGY Fpga Technology 0 ADC_DATA_WIDTH Adc Data Width 256 DMA_DATA_WIDTH Dma Data Width 64 DMA_READY_ENABLE Dma Ready Enable 1 DMA_ADDRESS_WIDTH Dma Address Width 10 Component_Name util_adcfifo_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_adcfifo_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:17:55Z 2019.1.3