analog.com user axi_jesd204_tx 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW tx_cfg lanes_disable core_cfg_lanes_disable links_disable core_cfg_links_disable beats_per_multiframe core_cfg_beats_per_multiframe octets_per_frame core_cfg_octets_per_frame lmfc_offset core_cfg_lmfc_offset sysref_oneshot core_cfg_sysref_oneshot sysref_disable core_cfg_sysref_disable continuous_cgs core_cfg_continuous_cgs continuous_ilas core_cfg_continuous_ilas skip_ilas core_cfg_skip_ilas mframes_per_ilas core_cfg_mframes_per_ilas disable_char_replacement core_cfg_disable_char_replacement disable_scrambler core_cfg_disable_scrambler tx_ilas_config rd core_ilas_config_rd addr core_ilas_config_addr data core_ilas_config_data true tx_event sysref_alignment_error core_event_sysref_alignment_error sysref_edge core_event_sysref_edge tx_status state core_status_state sync core_status_sync tx_ctrl manual_sync_request core_ctrl_manual_sync_request true irq INTERRUPT irq SENSITIVITY LEVEL_HIGH tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_clock tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_clock CLK core_clk ASSOCIATED_BUSIF tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl ASSOCIATED_RESET core_reset tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_reset tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_reset RST core_reset POLARITY ACTIVE_HIGH s_axi axi_lite 0 16384 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_jesd204_tx xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 3308ac30 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_jesd204_tx xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum c3f4e40f xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 89faa098 s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_reset_ext in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 core_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_lanes_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_links_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_beats_per_multiframe out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_lmfc_offset out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_sysref_oneshot out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_sysref_disable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_continuous_cgs out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_continuous_ilas out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_skip_ilas out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_mframes_per_ilas out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_disable_char_replacement out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_cfg_disable_scrambler out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ilas_config_rd in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ilas_config_addr in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ilas_config_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_event_sysref_alignment_error in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_event_sysref_edge in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_ctrl_manual_sync_request out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_state in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation core_status_sync in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 LINK_MODE Link Mode 1 ENABLE_LINK_STATS Enable Link Stats 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_9ca20931 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_pairs_1942b210 2 1 xilinx_anylanguagesynthesis_view_fileset axi_jesd204_tx_ooc.ttcl ttcl axi_jesd204_tx_constr.xdc xdc processing_order late jesd204_up_tx.v verilogSource ../../common/up_axi.v verilogSource axi_jesd204_tx.v verilogSource CHECKSUM_2b7f24ef xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_up_tx.v verilogSource ../../common/up_axi.v verilogSource axi_jesd204_tx.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_jesd204_tx_v1_0.tcl tclSource CHECKSUM_8192bd24 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset ADI JESD204B Transmit AXI Interface ID Id 0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 LINK_MODE Link Layer mode 1 ENABLE_LINK_STATS Enable Link Stats 0 Component_Name axi_jesd204_tx_v1_0 virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices ADI JESD204C Transmit AXI Interface package_project Analog Devices http://www.analog.com 1 2021-12-09T07:17:20Z 2019.1.3