analog.com user jesd204_rx 1.0 rx_phy0 rxdata phy_data 31 0 rxcharisk phy_charisk 3 0 rxdisperr phy_disperr 3 0 rxnotintable phy_notintable 3 0 rxheader phy_header 1 0 rxblock_sync phy_block_sync 0 0 true rx_phy1 rxdata phy_data 63 32 rxcharisk phy_charisk 7 4 rxdisperr phy_disperr 7 4 rxnotintable phy_notintable 7 4 rxheader phy_header 3 2 rxblock_sync phy_block_sync 1 1 false rx_phy2 rxdata phy_data 95 64 rxcharisk phy_charisk 11 8 rxdisperr phy_disperr 11 8 rxnotintable phy_notintable 11 8 rxheader phy_header 5 4 rxblock_sync phy_block_sync 2 2 false rx_phy3 rxdata phy_data 127 96 rxcharisk phy_charisk 15 12 rxdisperr phy_disperr 15 12 rxnotintable phy_notintable 15 12 rxheader phy_header 7 6 rxblock_sync phy_block_sync 3 3 false rx_phy4 rxdata phy_data 159 128 rxcharisk phy_charisk 19 16 rxdisperr phy_disperr 19 16 rxnotintable phy_notintable 19 16 rxheader phy_header 9 8 rxblock_sync phy_block_sync 4 4 false rx_phy5 rxdata phy_data 191 160 rxcharisk phy_charisk 23 20 rxdisperr phy_disperr 23 20 rxnotintable phy_notintable 23 20 rxheader phy_header 11 10 rxblock_sync phy_block_sync 5 5 false rx_phy6 rxdata phy_data 223 192 rxcharisk phy_charisk 27 24 rxdisperr phy_disperr 27 24 rxnotintable phy_notintable 27 24 rxheader phy_header 13 12 rxblock_sync phy_block_sync 6 6 false rx_phy7 rxdata phy_data 255 224 rxcharisk phy_charisk 31 28 rxdisperr phy_disperr 31 28 rxnotintable phy_notintable 31 28 rxheader phy_header 15 14 rxblock_sync phy_block_sync 7 7 false rx_phy8 rxdata phy_data 287 256 rxcharisk phy_charisk 35 32 rxdisperr phy_disperr 35 32 rxnotintable phy_notintable 35 32 rxheader phy_header 17 16 rxblock_sync phy_block_sync 8 8 false rx_phy9 rxdata phy_data 319 288 rxcharisk phy_charisk 39 36 rxdisperr phy_disperr 39 36 rxnotintable phy_notintable 39 36 rxheader phy_header 19 18 rxblock_sync phy_block_sync 9 9 false rx_phy10 rxdata phy_data 351 320 rxcharisk phy_charisk 43 40 rxdisperr phy_disperr 43 40 rxnotintable phy_notintable 43 40 rxheader phy_header 21 20 rxblock_sync phy_block_sync 10 10 false rx_phy11 rxdata phy_data 383 352 rxcharisk phy_charisk 47 44 rxdisperr phy_disperr 47 44 rxnotintable phy_notintable 47 44 rxheader phy_header 23 22 rxblock_sync phy_block_sync 11 11 false rx_phy12 rxdata phy_data 415 384 rxcharisk phy_charisk 51 48 rxdisperr phy_disperr 51 48 rxnotintable phy_notintable 51 48 rxheader phy_header 25 24 rxblock_sync phy_block_sync 12 12 false rx_phy13 rxdata phy_data 447 416 rxcharisk phy_charisk 55 52 rxdisperr phy_disperr 55 52 rxnotintable phy_notintable 55 52 rxheader phy_header 27 26 rxblock_sync phy_block_sync 13 13 false rx_phy14 rxdata phy_data 479 448 rxcharisk phy_charisk 59 56 rxdisperr phy_disperr 59 56 rxnotintable phy_notintable 59 56 rxheader phy_header 29 28 rxblock_sync phy_block_sync 14 14 false rx_phy15 rxdata phy_data 511 480 rxcharisk phy_charisk 63 60 rxdisperr phy_disperr 63 60 rxnotintable phy_notintable 63 60 rxheader phy_header 31 30 rxblock_sync phy_block_sync 15 15 false rx_cfg lanes_disable cfg_lanes_disable links_disable cfg_links_disable beats_per_multiframe cfg_beats_per_multiframe octets_per_frame cfg_octets_per_frame lmfc_offset cfg_lmfc_offset sysref_oneshot cfg_sysref_oneshot sysref_disable cfg_sysref_disable buffer_delay cfg_buffer_delay buffer_early_release cfg_buffer_early_release disable_char_replacement cfg_disable_char_replacement err_statistics_reset ctrl_err_statistics_reset err_statistics_mask ctrl_err_statistics_mask disable_scrambler cfg_disable_scrambler frame_align_err_threshold cfg_frame_align_err_threshold rx_status ctrl_state status_ctrl_state lane_cgs_state status_lane_cgs_state lane_emb_state status_lane_emb_state err_statistics_cnt status_err_statistics_cnt lane_ifs_ready status_lane_ifs_ready lane_latency status_lane_latency lane_frame_align_err_cnt status_lane_frame_align_err_cnt rx_ilas_config valid ilas_config_valid addr ilas_config_addr data ilas_config_data true rx_event sysref_alignment_error event_sysref_alignment_error sysref_edge event_sysref_edge frame_alignment_error event_frame_alignment_error unexpected_lane_state_error event_unexpected_lane_state_error rx_cfg_rx_ilas_config_rx_event_rx_status_rx_data_signal_clock rx_cfg_rx_ilas_config_rx_event_rx_status_rx_data_signal_clock CLK clk ASSOCIATED_BUSIF rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data ASSOCIATED_RESET reset rx_cfg_rx_ilas_config_rx_event_rx_status_rx_data_signal_reset rx_cfg_rx_ilas_config_rx_event_rx_status_rx_data_signal_reset RST reset POLARITY ACTIVE_HIGH xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_rx xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 77806980 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_rx xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 77806980 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum bb2715c0 xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 phy_header in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 phy_charisk in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_notintable in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_disperr in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation phy_block_sync in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sysref in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lmfc_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation event_sysref_alignment_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation event_sysref_edge out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation event_frame_alignment_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation event_unexpected_lane_state_error out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true phy_en_char_align out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true rx_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_eof out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sof out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lanes_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_links_disable in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_beats_per_multiframe in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_frame in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lmfc_offset in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_sysref_disable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_sysref_oneshot in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_buffer_early_release in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_buffer_delay in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_char_replacement in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_scrambler in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_err_statistics_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_err_statistics_mask in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_frame_align_err_threshold in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_err_statistics_cnt out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_valid out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_addr out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_ctrl_state out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_cgs_state out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_ifs_ready out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_latency out 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_emb_state out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_lane_frame_align_err_cnt out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_INPUT_PIPELINE Num Input Pipeline 1 LINK_MODE Link Mode 1 DATA_PATH_WIDTH Data Path Width 4 ENABLE_FRAME_ALIGN_CHECK Enable Frame Align Check 1 ENABLE_FRAME_ALIGN_ERR_RESET Enable Frame Align Err Reset 0 choice_pairs_1942b210 2 1 xilinx_anylanguagesynthesis_view_fileset jesd204_rx_constr.ttcl ttcl align_mux.v verilogSource elastic_buffer.v verilogSource error_monitor.v verilogSource jesd204_ilas_monitor.v verilogSource jesd204_lane_latency_monitor.v verilogSource jesd204_rx_cgs.v verilogSource jesd204_rx_ctrl.v verilogSource jesd204_rx_ctrl_64b.v verilogSource jesd204_rx_frame_align_monitor.v verilogSource jesd204_rx_frame_mark.v verilogSource jesd204_rx_header.v verilogSource jesd204_rx_lane.v verilogSource jesd204_rx_lane_64b.v verilogSource jesd204_rx.v verilogSource CHECKSUM_d09f39f3 xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset align_mux.v verilogSource elastic_buffer.v verilogSource error_monitor.v verilogSource jesd204_ilas_monitor.v verilogSource jesd204_lane_latency_monitor.v verilogSource jesd204_rx_cgs.v verilogSource jesd204_rx_ctrl.v verilogSource jesd204_rx_ctrl_64b.v verilogSource jesd204_rx_frame_align_monitor.v verilogSource jesd204_rx_frame_mark.v verilogSource jesd204_rx_header.v verilogSource jesd204_rx_lane.v verilogSource jesd204_rx_lane_64b.v verilogSource jesd204_rx.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/jesd204_rx_v1_0.tcl tclSource CHECKSUM_a23568ae XGUI_VERSION_2 xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/jesd204_rx_v1_0.gtcl GTCL ADI JESD204 Receive NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 NUM_INPUT_PIPELINE Num Input Pipeline 1 LINK_MODE Link Layer mode 1 DATA_PATH_WIDTH Data Path Width 4 false ENABLE_FRAME_ALIGN_CHECK Enable Frame Align Check 1 ENABLE_FRAME_ALIGN_ERR_RESET Enable Frame Align Err Reset 0 Component_Name jesd204_rx_v1_0 SYSREF_IOB Place SYSREF in IOB true virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices ADI JESD204 Receive package_project Analog Devices http://www.analog.com 1 2021-12-08T12:25:18Z 2019.1.3