analog.com user util_fir_dec 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_fir_dec xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 4ad39f21 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_fir_dec xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 4ad39f21 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_data_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation channel_0 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation channel_1 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation decimate in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data_tdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset coefile_dec.coe coe util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci xci util_fir_dec.v verilogSource CHECKSUM_ea102078 xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset coefile_dec.coe coe util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci xci util_fir_dec.v verilogSource xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset xilinx_xpgui_view_fileset xgui/util_fir_dec_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 util_fir_dec_v1_0 Component_Name util_fir_dec_v1_0 virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices util_fir_dec_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:19:00Z 2019.1.3