analog.com user axi_hdmi_tx 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axis TREADY vdma_ready TVALID vdma_valid TDATA vdma_data TLAST vdma_end_of_frame hdmi_clk CLK hdmi_clk hdmi_out_clk CLK hdmi_out_clk vdma_clk CLK vdma_clk ASSOCIATED_BUSIF s_axis s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_hdmi_tx xilinx_anylanguagesynthesis_view_fileset viewChecksum 8317b780 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_hdmi_tx xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 57c5e82b xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 70073919 xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset hdmi_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation hdmi_out_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation hdmi_16_hsync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true hdmi_16_vsync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true hdmi_16_data_e out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true hdmi_16_data out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true hdmi_16_es_data out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_24_hsync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_24_vsync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_24_data_e out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_24_data out 23 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_36_hsync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_36_vsync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_36_data_e out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false hdmi_36_data out 35 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false vdma_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation vdma_end_of_frame in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 vdma_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 vdma_data in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 vdma_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 CR_CB_N Cr Cb N 0 FPGA_TECHNOLOGY Fpga Technology 0 INTERFACE Interface 16_BIT OUT_CLK_POLARITY Out Clk Polarity 0 choice_list_684d9491 16_BIT 24_BIT 36_BIT 16_BIT_EMBEDDED_SYNC choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_aee923ef 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc axi_hdmi_tx_constr.xdc xdc ../common/ad_csc.v verilogSource ../common/ad_csc_RGB2CrYCb.v verilogSource ../common/ad_mem.v verilogSource ../common/ad_rst.v verilogSource ../common/ad_ss_444to422.v verilogSource axi_hdmi_tx_core.v verilogSource axi_hdmi_tx_es.v verilogSource axi_hdmi_tx_vdma.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_hdmi_tx.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_hdmi_tx.v verilogSource CHECKSUM_d8dabf5a xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_csc.v verilogSource ../common/ad_csc_RGB2CrYCb.v verilogSource ../common/ad_mem.v verilogSource ../common/ad_rst.v verilogSource ../common/ad_ss_444to422.v verilogSource axi_hdmi_tx_core.v verilogSource axi_hdmi_tx_es.v verilogSource axi_hdmi_tx_vdma.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_hdmi_tx.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_hdmi_tx.v verilogSource xilinx_xpgui_view_fileset xgui/axi_hdmi_tx_v1_0.tcl tclSource CHECKSUM_a6d814f3 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_hdmi_tx_v1_0 ID Id 0 CR_CB_N Cr Cb N 0 FPGA_TECHNOLOGY Fpga Technology 0 INTERFACE Interface 16_BIT OUT_CLK_POLARITY Out Clk Polarity 0 Component_Name axi_hdmi_tx_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_hdmi_tx_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:23:17Z 2019.1.3