`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/07/11 15:53:41
// Design Name:
// Module Name: AddrtoWaveform
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module AddrtoWaveform(
    input clk,
    input rst,
    input [14:0] Phase_addr,
    output reg [17:0] Cos_Wave = 18'd0,
    output reg [17:0] Sin_Wave = 18'd0
    );

reg [14:0] Phase_addr_D1 = 13'd0;
always @(posedge clk)
    if(rst)
        begin
        Phase_addr_D1 <= 13'd0;
        end
    else
        begin
        Phase_addr_D1[14:0] <= Phase_addr[14:0];
        end

    reg [1:0] PhaseChange = 2'd0;
    always @(posedge clk)
    if(rst)
        begin
        PhaseChange[1:0]<= 2'd0;
        end
    else
        begin
        PhaseChange[1:0]<= Phase_addr_D1[14:13];
        end

    reg [1:0] PhaseChange_D1 = 2'd0;  reg [1:0] PhaseChange_D2 = 2'd0;
    reg [1:0] PhaseChange_D3 = 2'd0;  reg [1:0] PhaseChange_D4 = 2'd0;
    always @(posedge clk)
    if(rst)
        begin
        PhaseChange_D1[1:0] <= 2'd0;
        PhaseChange_D2[1:0] <= 2'd0;
        PhaseChange_D3[1:0] <= 2'd0;
        PhaseChange_D4[1:0] <= 2'd0;
        end
    else
        begin
        PhaseChange_D1[1:0] <= PhaseChange[1:0];
        PhaseChange_D2[1:0] <= PhaseChange_D1[1:0];
        PhaseChange_D3[1:0] <= PhaseChange_D2[1:0];
        PhaseChange_D4[1:0] <= PhaseChange_D3[1:0];
        end

    reg [12:0] Phase_addr_D2 = 13'd0;
    always @(posedge clk)
    if(rst)
        begin
        Phase_addr_D2[12:0]<= 13'd0;
        end
    else
        begin
        Phase_addr_D2[12:0]<= Phase_addr_D1[12:0];
        end


    reg [12:0]Cos_addr = 13'd0;
    reg [12:0]Sin_addr = 13'd0;
    always @(posedge clk)
    if(rst)
        begin
            Cos_addr[12:0] <= 13'd0;
            Sin_addr[12:0] <= 13'd0;
        end
    else
        begin
            case(PhaseChange[1:0])
            2'd0:
                begin
                    Cos_addr[12:0] <= Phase_addr_D2[12:0];
                    Sin_addr[12:0] <= 13'd8191 - Phase_addr_D2[12:0];
                end
            2'd1:
                begin
                    Cos_addr[12:0] <= 13'd8191 - Phase_addr_D2[12:0];
                    Sin_addr[12:0] <= Phase_addr_D2[12:0];
                end
            2'd2:
                begin
                    Cos_addr[12:0] <= Phase_addr_D2[12:0];
                    Sin_addr[12:0] <=  13'd8191 - Phase_addr_D2[12:0];
                end
            2'd3:
                begin
                    Cos_addr[12:0] <= 13'd8191 - Phase_addr_D2[12:0];
                    Sin_addr[12:0] <= Phase_addr_D2[12:0];
                end
            default:
                begin
                    Cos_addr[12:0] <= 13'd0;
                    Sin_addr[12:0] <= 13'd0;
                end
            endcase
        end


    wire [17:0] Cos_dout;
    wire [17:0] Sin_dout;
    COSLUT_10_16bit COSLUT_10_16bit (
      .clka(clk),    // input wire clka
      .addra(Cos_addr[12:0]),  // input wire [9 : 0] addra
      .douta(Cos_dout[17:0]),  // output wire [15 : 0] douta
      .clkb(clk),    // input wire clkb
      .addrb(Sin_addr[12:0]),  // input wire [9 : 0] addrb
      .doutb(Sin_dout[17:0])  // output wire [15 : 0] doutb
    );


    always @(posedge clk)
    if(rst)
        begin
            Cos_Wave[17:0] <= 16'd0;
            Sin_Wave[17:0] <= 16'd0;
        end
    else
        begin
            case(PhaseChange_D4[1:0])
            2'd0:
                begin
                    Cos_Wave[17:0] <= Cos_dout[17:0];
                    Sin_Wave[17:0] <= Sin_dout[17:0];
                end
            2'd1:
                begin
                    Cos_Wave[17:0] <= ~Cos_dout[17:0] + 18'd1;
                    Sin_Wave[17:0] <= Sin_dout[17:0];
                end
            2'd2:
                begin
                    Cos_Wave[17:0] <= ~Cos_dout[17:0] + 18'd1;
                    Sin_Wave[17:0] <= ~Sin_dout[17:0] + 18'd1;
                end
            2'd3:
                begin
                    Cos_Wave[17:0] <= Cos_dout[17:0];
                    Sin_Wave[17:0] <= ~Sin_dout[17:0] + 18'd1;
                end
            default:
                begin
                    Cos_Wave[17:0] <= 18'd0;
                    Sin_Wave[17:0] <= 18'd0;
                end
            endcase
        end


endmodule