analog.com user axi_logic_analyzer 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW clk CLK clk clk_out CLK clk_out s_axi axi_lite 0 128 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_logic_analyzer xilinx_anylanguagesynthesis_view_fileset viewChecksum b63889b2 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_logic_analyzer xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum e338d3aa xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation clk_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_i in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_o out 15 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_t out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_i in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data out 15 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_read out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation external_rate in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation external_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation external_decimation_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 trigger_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_out_adc out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_depth out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc axi_logic_analyzer_constr.xdc xdc ../common/ad_rst.v verilogSource axi_logic_analyzer_reg.v verilogSource axi_logic_analyzer_trigger.v verilogSource ../common/up_axi.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_logic_analyzer.v verilogSource CHECKSUM_c7746b84 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_rst.v verilogSource axi_logic_analyzer_reg.v verilogSource axi_logic_analyzer_trigger.v verilogSource ../common/up_axi.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_logic_analyzer.v verilogSource xilinx_xpgui_view_fileset xgui/axi_logic_analyzer_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 axi_logic_analyzer_v1_0 Component_Name axi_logic_analyzer_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_logic_analyzer_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:15:42Z 2019.1.3