analog.com user util_tdd_sync 1.0 clk CLK clk ASSOCIATED_RESET rstn rstn RST rstn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_tdd_sync xilinx_anylanguagesynthesis_view_fileset viewChecksum d4aa66cf xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_tdd_sync xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 12c1bffc xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum fdcef067 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_mode in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_out out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation TDD_SYNC_PERIOD Tdd Sync Period 100000000 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset util_tdd_sync_constr.xdc xdc ../common/util_pulse_gen.v verilogSource util_tdd_sync.v verilogSource CHECKSUM_08a38e14 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/util_pulse_gen.v verilogSource util_tdd_sync.v verilogSource xilinx_xpgui_view_fileset xgui/util_tdd_sync_v1_0.tcl tclSource CHECKSUM_fdcef067 XGUI_VERSION_2 util_tdd_sync_v1_0 TDD_SYNC_PERIOD Tdd Sync Period 100000000 Component_Name util_tdd_sync_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_tdd_sync_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:24:21Z 2019.1.3