analog.com user axi_usb_fx3 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi:m_axis:s_axis ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW m_axis TDATA m_axis_tdata TKEEP m_axis_tkeep TLAST m_axis_tlast TVALID m_axis_tvalid TREADY m_axis_tready s_axis TDATA s_axis_tdata TKEEP s_axis_tkeep TLAST s_axis_tlast TVALID s_axis_tvalid TREADY s_axis_tready s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_usb_fx3 xilinx_anylanguagesynthesis_view_fileset viewChecksum a0e8fe23 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_usb_fx3 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum a0e8fe23 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 dma_rdy in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wmk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_rdy in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pclk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data inout 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation addr out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation slcs_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation slrd_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sloe_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation slwr_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pktend_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation epswitch_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation debug_fx32dma out 74 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation debug_dma2fx3 out 73 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation debug_status out 14 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tkeep in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axis_tlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 m_axis_tdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tkeep out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_usb_fx3_core.v verilogSource axi_usb_fx3_if.v verilogSource axi_usb_fx3_reg.v verilogSource ../common/up_axi.v verilogSource axi_usb_fx3.v verilogSource CHECKSUM_b6dfdecc xilinx_anylanguagebehavioralsimulation_view_fileset axi_usb_fx3_core.v verilogSource axi_usb_fx3_if.v verilogSource axi_usb_fx3_reg.v verilogSource ../common/up_axi.v verilogSource axi_usb_fx3.v verilogSource xilinx_xpgui_view_fileset xgui/axi_usb_fx3_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 axi_usb_fx3_v1_0 Component_Name axi_usb_fx3_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_usb_fx3_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:16:48Z 2019.1.3