`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/8/13 00:24:20
// Design Name: 
// Module Name: LMX2595
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 

// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
// fPFD	 = fPFD = REFIN × ((1 + D)/(R × (1 + T))) 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//////////////////////////////////////////////////////////////////////////////////


module adf4371_b(//20.375Ghz ~ 23.875Ghz
input               sysclk    ,//40MHZ
input               arstn     ,
output              cs        ,
input               mux_out   ,
output              sclk      ,
output              sdio      ,     
input [3:0]			rf_en	  , 			    
input 				CAL_F	  , 			    
input 				SW_PLL	  , 			    
input 				i_cfgover	  , 			    
input [3:0]			ceshi_model	  , 			    
input               adf4371_hop      ,    			    
input[11:0]         fre_code          			    
    );

localparam      DATA_WIDTH = 24			;
localparam      DATA_LENTH = 72		;
localparam      WAIT_ld   = 40000		;					
//***********************************************************************************************************//												
reg[7:0]                cnt_word    = 8'd0					;
reg	    				csb_reg	    = 1'b1					;
reg[5:0]                cnt_bits    = 6'd0					;  
reg[DATA_WIDTH-1:0]     cfgdata     = 0,        regdata = 0	;
reg[3:0]                state	    = 4'b000				;
reg                     spi_sdo     = 1'b0,     spi_csb = 1'b1;
wire                    pll_locked  						;
reg[31:0]               cnt_lock    = 32'd0					;
reg[31:0]               cnt_locked  = 32'd0					;
wire[15:0]              band  							;

//-----------------------------------
assign      pll_locked		 = mux_out							;
assign      sclk  	  		 = spi_csb ? 1'b0 : ~sysclk		;
assign      cs     	  		 = spi_csb & csb_reg			;
assign      sdio      		 = spi_sdo						;
//-----------------------------------

wire [7:0]	SI_BAND_SEL    ;		//VCO频段
wire [7:0]	SI_VCO_SEL_BIAS_CODE    ; //[7:4]=VCO内核, [3:0]=VCO偏置
reg[13:0]	MOD2		;
reg[13:0]	FRAC2		;
reg[24:0]	FRAC1		;
reg[15:0]	INT			;

assign		SI_BAND_SEL            =  band[15:8]   ;
assign		SI_VCO_SEL_BIAS_CODE   =  band[7:0]  ;

reg[2:0]	hop_en;	
reg[15:0]	code;	
reg[11:0]	pre_fre_code;
reg[3:0]	cp_r;	
reg[3:0]	rf_en_r;	
reg[2:0]	CAL_F_R;	

reg	[3:0]	R_DIV ;
reg	[3:0]	D	 ;
wire[13:0]	douta3		;
wire[13:0]	douta4		;
wire[24:0]	douta2		;
wire[15:0]	douta1			;

//----------------------------------- 
INT_ROMb int_rom (
    .sysclk(sysclk), 
    .addra(code), 
    .douta(douta1)
    );

FRAC1 frac1_rom (
    .clka(sysclk), 
    .addra(code), 
    .douta(douta2)
    );
	
// FRAC1_ROM FRAC1_ROM (
//  .clka(sysclk), // input clka
//  .addra(code), // input [11 : 0] addra
//  .douta(douta2) // output [24 : 0] douta
//); 
	
frac2_rom frac2_rom (
    .sysclk(sysclk), 
    .addra(code), 
    .douta(douta4)
    );

mod2_rom mod2_rom (
    .sysclk(sysclk), 
    .addra(code), 
    .douta(douta3)
    );


band_rom_b band_rom_b (
    .sysclk(sysclk), 
    .addra(code),
	.douta(band) // output [15 : 0] douta
    );	

//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------

always@(posedge sysclk,negedge arstn)
begin
	if(!arstn)
		INT<=douta1;
	else if(code==24 || code==26 )  
		INT<=76;
	else if(code==424 )  
		INT<=77;
	else if(code==426 )  
		INT<=78;
	else if(code==824 || code==826 )  
		INT<=79;
	else if(code==1224) 
		INT<=80;
	else if(code==1226 )  
		INT<=81;
	else if(code==1624 || code==1626 )  
		INT<=82;
	else if(code==2024 )  
		INT<=83;
	else if(code==2026 )  
		INT<=84;	
	else if(code==2424 || code==2426 )  
		INT<=85;
	else if(code==2824 )  
		INT<=86;
	else if( code==2826 )  
		INT<=87;
	else
		INT<=douta1;	
end

always@(posedge sysclk,negedge arstn)
begin
	if(!arstn)
		FRAC1<=douta2;
	else if(code==24 )  
		FRAC1<=16651386;
	else if(code==26 )  
		FRAC1<=16903045;
	else if(code==424 )  
		FRAC1<=33428602;
	else if(code==426 )  
		FRAC1<=125829;
	else if(code==824 )  
		FRAC1<=16651386;
	else if(code==826 )  
		FRAC1<=16903045;
	else if(code==1224) 
		FRAC1<=33428602;
	else if(code==1226 )  
		FRAC1<=125829;
	else if(code==1624)  
		FRAC1<=16651386;
	else if(code==1626 )  
		FRAC1<=16903045;
	else if(code==2024 )  
		FRAC1<=33428602;
	else if(code==2026 )  
		FRAC1<=125829;	
	else if(code==2424 )  
		FRAC1<=16651386;
	else if(code==2426 )  
		FRAC1<=16903045;
	else if(code==2824 )  
		FRAC1<=33428602;
	else if( code==2826 )  
		FRAC1<=125829;
	else
		FRAC1<=douta2;	
end

always@(posedge sysclk,negedge arstn)
begin
	if(!arstn)
		MOD2<=douta3;
	else if(code==24 )  
		MOD2<=25;
	else if(code==26 )  
		MOD2<=25;
	else if(code==424 )  
		MOD2<=25;
	else if(code==426 )  
		MOD2<=25;
	else if(code==824 )  
		MOD2<=25;
	else if(code==826 )  
		MOD2<=25;
	else if(code==1224) 
		MOD2<=25;
	else if(code==1226 )  
		MOD2<=25;
	else if(code==1624)  
		MOD2<=25;
	else if(code==1626 )  
		MOD2<=25;
	else if(code==2024 )  
		MOD2<=25;
	else if(code==2026 )  
		MOD2<=25;	
	else if(code==2424 )  
		MOD2<=25;
	else if(code==2426 )  
		MOD2<=25;
	else if(code==2824 )  
		MOD2<=25;
	else if( code==2826 )  
		MOD2<=25;
	else
		MOD2<=douta3;	
end

always@(posedge sysclk,negedge arstn)
begin
	if(!arstn)
		FRAC2<=douta4;
	else if(code==24 )  
		FRAC2<=22;
	else if(code==26 )  
		FRAC2<=3;
	else if(code==424 )  
		FRAC2<=22;
	else if(code==426 )  
		FRAC2<=3;
	else if(code==824 )  
		FRAC2<=22;
	else if(code==826 )  
		FRAC2<=3;
	else if(code==1224) 
		FRAC2<=22;
	else if(code==1226 )  
		FRAC2<=3;
	else if(code==1624)  
		FRAC2<=22;
	else if(code==1626 )  
		FRAC2<=3;
	else if(code==2024 )  
		FRAC2<=22;
	else if(code==2026 )  
		FRAC2<=3;	
	else if(code==2424 )  
		FRAC2<=22;
	else if(code==2426 )  
		FRAC2<=3;
	else if(code==2824 )  
		FRAC2<=22;
	else if( code==2826 )  
		FRAC2<=3;
	else
		FRAC2<=douta4;	
end

always@(posedge sysclk,negedge arstn)
begin
	if(!arstn)begin
		R_DIV<=4'b1;
		D<=4'b0;
	end
	else if(code==24 || code==26 ||   code==424 ||  code==426 || code==824 ||  code==826|| code==1224 ||  code==1226 || code==1624 ||  code==1626 ||code==2024 ||  code==2026 ||code==2424 ||  code==2426 ||code==2824 ||  code==2826 )
	begin
		R_DIV<=	4'd3;
		D<=4'd2;
	end
	else
	begin
		R_DIV<=4'b1;
		D<=4'b0;
	end	
end


always@(posedge sysclk,negedge arstn)begin
if(~arstn)
	pre_fre_code<=11'h6d6;
else if(CAL_F_R==3'b011)
	pre_fre_code<=fre_code;
else
	pre_fre_code<=pre_fre_code;
end

always@(posedge sysclk,negedge arstn)begin
if(~arstn)
	code<=16'h6d6;
else if(hop_en==2'b01)
	code<=fre_code;
else
	code<=code;
end

always@(posedge sysclk,negedge arstn)begin
if(~arstn)begin
    hop_en 	<= 3'b0;
    CAL_F_R 	<= 3'b0;
    rf_en_r <= 4'b0;
end
else  begin
	hop_en	<= {hop_en[1:0],adf4371_hop};
	CAL_F_R	<= {CAL_F_R[1:0],CAL_F};
	rf_en_r	<= rf_en	;
end
end


always@(posedge sysclk,negedge arstn)begin
if(~arstn)
    csb_reg 	<= 1'b1;
else  
	csb_reg		<= spi_csb;
end


always@(posedge sysclk,negedge arstn)begin
if(~arstn)	
	cnt_locked<=32'b0;
else if(cnt_locked==WAIT_ld)
	cnt_locked<=32'b0;
else if(!pll_locked)
	cnt_locked<=cnt_locked+1'b1;
else
	cnt_locked<=32'b0;
end

always@(posedge sysclk,negedge arstn)begin
if(~arstn)begin
    cfgdata  <= 0;
    cnt_word <= 7'd0;
    cnt_bits <= 6'd0;
    state	 <= 4'b0;
    cnt_lock <= 32'd0;
    spi_csb  <= 1'b1;
    spi_sdo  <= 1'b0;
end
else begin
    case(state)
    4'd0:begin
			cnt_word <= 7'd0;		
		if(rf_en==1'b1)
            state <= 4'd0;
		else if(cnt_lock >= 32'd6000) 
			state <= 4'd1;
		else
			state <= state;
			
		if(rf_en==1'b0)
			cnt_lock <= cnt_lock + 1'b1;
		else
			cnt_lock<=32'd0;
		
    end
    4'd1:begin
        spi_csb <= 1'b1;
        spi_sdo <= 1'b0;      
        state 	<= 4'd2;
    end
    4'd2:begin
        cfgdata  <= regdata;
        cnt_bits <= 6'd0;
        state    <= 4'd3;
    end
    4'd3:begin
        spi_csb <= 1'b0;
        spi_sdo <= cfgdata[DATA_WIDTH-1];
        cfgdata <= cfgdata << 1'b1;
        cnt_bits <= cnt_bits + 1'b1;
        if(cnt_bits == DATA_WIDTH-1)begin
            state 	 <= 4'd4;
            cnt_word <= cnt_word + 1'b1;
        end
			cnt_lock <= 32'd0;
    end
    4'd4:begin
        spi_csb  <= 1'b1;
        spi_sdo  <= 1'b0;
        cnt_lock <= 32'd0;
        cnt_bits <= 32'd0;
        if(cnt_word == DATA_LENTH)begin
            state <= 4'd5;
        end
        else
            state <= 4'd1;
    end
	4'd5:begin
			if(cnt_lock>=40000 || pll_locked)begin
				cnt_lock <=	32'd0	;
				state	 <= 4'd6 ;
			end
			else begin
				cnt_lock <=cnt_lock+1'b1;
				state 	 <= state ;
			end
		end
	4'd6:begin
			    cnt_word <= 7'd0;
			if(pll_locked)
				state 	 <= 4'd7 ;
			else
				state 	 <= 4'b1 ;
		end
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
    4'd7:begin//IDLE
		 cnt_word	<= DATA_LENTH;
		 spi_csb 	<= 1'b1;
         spi_sdo 	<= 1'b0;
		 cnt_bits 	<= 6'd0;
		if(rf_en==4'b1)
			state 	<= state;
		else if(rf_en==4'b0 && rf_en_r==4'b1 )
			state   <= 4'd0;
		else if(hop_en==2'b10 || cnt_locked==WAIT_ld  )
			state 	<= 4'd8;
		//else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
		else if(i_cfgover)
			state 	<= 4'd12;
		else
			state 	<= state;
    end
    4'd8:begin
        spi_csb <= 1'b1;
        spi_sdo <= 1'b0;    
		state 	<= 4'd9;
    end
    4'd9:begin
        cfgdata  <= regdata;
        cnt_bits <= 6'd0;
        state 	 <= 4'd10;
    end
    4'd10:begin
        spi_csb <= 1'b0;
        spi_sdo <= cfgdata[DATA_WIDTH-1];
        cfgdata <= cfgdata << 1'b1;
        cnt_bits <= cnt_bits + 1'b1;
        if(cnt_bits == DATA_WIDTH-1)begin
            state 	 <= 4'd11;
            cnt_word <= cnt_word + 1'b1;
        end
    end
	4'd11:begin
        spi_csb  <= 1'b1;
        spi_sdo  <= 1'b0;
        cnt_lock <= 32'd0;
        cnt_bits <= 32'd0;
        if(cnt_word == 8'd85)begin
            state <= 4'd7;
        end
        else
            state <= 4'd8;
    end
	4'd12:begin
        spi_csb <= 1'b1;
        spi_sdo <= 1'b0;    
		state 	<= 4'd13;
    end
    4'd13:begin
        cnt_bits <= 6'd0;
        state 	 <= 4'd14;
		if(ceshi_model==4'hb)
			cfgdata  <= {16'h0025,8'h13};
		else if(ceshi_model==4'ha)
			cfgdata  <= {16'h0025,8'h00};
		else if	(SW_PLL)
			cfgdata  <= {16'h0025,8'h00};
		else	
			cfgdata  <= {16'h0025,8'h13};
    end
    4'd14:begin
        spi_csb <= 1'b0;
        spi_sdo <= cfgdata[DATA_WIDTH-1];
        cfgdata <= cfgdata << 1'b1;
        cnt_bits <= cnt_bits + 1'b1;
        if(cnt_bits == DATA_WIDTH-1)begin
            state 	 <= 4'd7;
            cnt_word <= cnt_word ;
        end
    end
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
    default: begin  
        spi_csb  <= 1'b1; 
        state	 <= 4'd0;
        cnt_lock <= 32'd0;
        cnt_word <= 8'd0;
    end
    endcase
end
end

always@(posedge sysclk,negedge arstn)
begin
	if(!arstn)
		 regdata <=  {16'h0000,8'h18  };
	else case(cnt_word)
		8'd0  : regdata <=  {16'h0000,8'h18  };
		8'd1  : regdata <=  {16'h0001,8'h00  };
		8'd2  : regdata <=  {16'h0003,8'h00  };
		8'd3  : regdata <=  {16'h0004,8'h00  };
		8'd4  : regdata <=  {16'h0005,8'h00  };
		8'd5  : regdata <=  {16'h0006,8'hFF  };
		8'd6  : regdata <=  {16'h000C,8'h00  };
		8'd7  : regdata <=  {16'h000D,8'h00  };
		8'd8  : regdata <=  {16'h0010 ,INT[7:0]  	 			}  ;
		8'd9  : regdata <=  {16'h0011 ,INT[15:8] 	 			}  ;
		8'd10 : regdata <=  {16'h0012,8'h00  };//[6]Autocalibration 
		//8'd10 : regdata <=  {16'h0012,8'h40  };//[6]Autocalibration 
		8'd11 : regdata <=  {16'h0014 ,FRAC1[7:0]}  ;
		8'd12 : regdata <=  {16'h0015 ,FRAC1[15:8]}  ;
		8'd13 : regdata <=  {16'h0016 ,FRAC1[23:16]}  ;
		8'd14 : regdata <=  {16'h0017 ,FRAC2[6:0],FRAC1[24]}  ;
		8'd15 : regdata <=  {16'h0018 ,1'b0,FRAC2[13:7]	}  ;
		8'd16 : regdata <=  {16'h0019 ,MOD2[7:0]}  ;
		8'd17 : regdata <=  {16'h001A ,2'b0,MOD2[13:8]}	;
		8'd18 : regdata <=  {16'h001B,8'h00  };
		8'd19 : regdata <=  {16'h001C,8'h00  };
		8'd20 : regdata <=  {16'h001D,8'h00  };
		8'd21 : regdata <=  {16'h001E,8'h18  };//CP_CURRENT 电荷泵
		//8'd21 : regdata <=  {16'h001E,cp,4'h8  };//CP_CURRENT 电荷泵
		8'd22 : regdata <= { 16'h001F,4'h0,R_DIV  };//R DIV  R分频器
		8'd23 : regdata <=  {16'h0020,8'h1c  };//digital lock detect  数字锁定ld
		8'd24 : regdata <=  {16'h0021,8'h00  };
		8'd25 : regdata <= { 16'h0022,D,4'd0  };//double    D倍频器
		8'd26 : regdata <=  {16'h0023,8'h00  };
		8'd27 : regdata <=  {16'h0024,8'h80  };//DIV_SEL
		8'd28 : regdata <=  {16'h0025,8'h13  };//X4_EN 
		8'd29 : regdata <=  {16'h0026,8'h1F  };
		8'd30 : regdata <=  {16'h0027,8'hCD  };
		//8'd30 : regdata <=  {16'h0027,8'hCD  };
		8'd31 : regdata <=  {16'h0028,8'h83  };
		8'd32 : regdata <=  {16'h002A,8'h00  };
		8'd33 : regdata <=  {16'h002B,8'h00  };
		8'd34 : regdata <=  {16'h002C,8'h44  };
		8'd35 : regdata <=  {16'h002D,8'h11  };
		8'd36 : regdata <=  {16'h002E,8'h12  };
		8'd37 : regdata <=  {16'h002F,8'h94  };
		8'd38 : regdata <=  {16'h0030,8'h2A  };
		8'd39 : regdata <=  {16'h0031,8'h02  };
		8'd40 : regdata <=  {16'h0032,8'h04  };
		8'd41 : regdata <=  {16'h0033,8'h22  };
		8'd42 : regdata <=  {16'h0034,8'h25  };
		8'd43 : regdata <=  {16'h0035,8'hFA  };
		8'd44 : regdata <=  {16'h0036,8'h30  };
		8'd45 : regdata <=  {16'h0037,SI_BAND_SEL}  ;//VCO频段
		8'd46 : regdata <=  {16'h0038,SI_VCO_SEL_BIAS_CODE 	};//[7:4]=VCO内核,[3:0]VCO偏置
		8'd47 : regdata <=  {16'h0039,8'h07  };
		8'd48 : regdata <=  {16'h003A,8'h55  };
		8'd49 : regdata <=  {16'h003D,8'h00  };
		8'd50 : regdata <=  {16'h003E,8'h0C  };
		8'd51 : regdata <=  {16'h003F,8'h80  };
		8'd52 : regdata <=  {16'h0040,8'h50  };
		8'd53 : regdata <=  {16'h0041,8'h28  };
		8'd54 : regdata <=  {16'h0042,8'h00  };
		8'd55 : regdata <=  {16'h0043,8'h00  };
		8'd56 : regdata <=  {16'h0044,8'h00  };
		8'd57 : regdata <=  {16'h0045,8'h00  };
		8'd58 : regdata <=  {16'h0046,8'h00  };
		8'd59 : regdata <=  {16'h0047,8'hC0  };
		8'd60 : regdata <=  {16'h0052,8'hF4  };
		8'd61 : regdata <=  {16'h006C,8'h00  };
		8'd62 : regdata <=  {16'h006E,8'h00  };
		8'd63 : regdata <=  {16'h006F,8'h00  };
		8'd64 : regdata <=  {16'h0070,8'hE3  };
		8'd65 : regdata <=  {16'h0071,8'h60  };
		8'd66 : regdata <=  {16'h0072,8'h32  };
		8'd67 : regdata <=  {16'h0073,8'h00  };
		8'd68 : regdata <=  {16'h0079,8'h00  };
		8'd69 : regdata <=  {16'h007A,8'h00  };
		8'd70 : regdata <=  {16'h007B,8'h00  };
		8'd71 : regdata <=  {16'h007C,8'h00  };

		//跳频
		8'd72:regdata <= { 16'h0022,D,4'd0  };//double    D倍频器
		8'd73:regdata <= { 16'h001F,4'h0,R_DIV  };//R DIV  R分频器
		8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8]		}  ;
		8'd75:regdata <= { 16'h0019 ,MOD2[7:0] 		 		}  ;
		8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7]	 	}  ;
		8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24]	}  ;
		8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] 			}  ;
		8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] 			}  ;
		8'd80:regdata <= { 16'h0014 ,FRAC1[7:0]	 			}  ;
		8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL 		 	}  ;
		8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE 	}  ;
		8'd83:regdata <= { 16'h0011 ,INT[15:8] 	 			}  ;
		8'd84:regdata <= { 16'h0010 ,INT[7:0]  	 			}  ;
		
	default:   regdata <= regdata;
endcase
end











endmodule