`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:35:03 01/27/2022 
// Design Name: 
// Module Name:    mod2_rom 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module frac2_rom(
input   		sysclk,
input [11 : 0]   addra,
output reg[13:0] douta
);


reg[11:0]	addr=0;

always@(posedge sysclk)begin
	addr<=addra%25;	
end

always@(posedge sysclk)begin
	case(addr)
0	:	douta	<=	0;
1	:	douta	<=	2;
2	:	douta	<=	4;
3	:	douta	<=	6;
4	:	douta	<=	8;
5	:	douta	<=	2;
6	:	douta	<=	12;
7	:	douta	<=	14;
8	:	douta	<=	16;
9	:	douta	<=	18;
10	:	douta	<=	4;
11	:	douta	<=	22;
12	:	douta	<=	24;
13	:	douta	<=	1;
14	:	douta	<=	3;
15	:	douta	<=	1;
16	:	douta	<=	7;
17	:	douta	<=	9;
18	:	douta	<=	11;
19	:	douta	<=	13;
20	:	douta	<=	3;
21	:	douta	<=	17;
22	:	douta	<=	19;
23	:	douta	<=	21;
24	:	douta	<=	23;
default:douta	<=	douta	;
endcase

end







endmodule