analog.com user axi_fan_control 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_fan_control xilinx_anylanguagesynthesis_view_fileset viewChecksum 65afd8f8 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_fan_control xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 65afd8f8 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c9d9f988 temp_in in 9 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tacho in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwm out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 PWM_FREQUENCY_HZ Pwm Frequency Hz 5000 INTERNAL_SYSMONE Internal Sysmone 0 AVG_POW Avg Pow 7 TACHO_TOL_PERCENT Tacho Tol Percent 25 TACHO_T25 Tacho T25 1470000 TACHO_T50 Tacho T50 820000 TACHO_T75 Tacho T75 480000 TACHO_T100 Tacho T100 340000 TEMP_00_H Temp 00 H 5 TEMP_25_L Temp 25 L 20 TEMP_25_H Temp 25 H 40 TEMP_50_L Temp 50 L 60 TEMP_50_H Temp 50 H 70 TEMP_75_L Temp 75 L 80 TEMP_75_H Temp 75 H 90 TEMP_00_L Temp 00 L 95 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../common/up_axi.v verilogSource ../common/util_pulse_gen.v verilogSource axi_fan_control.v verilogSource CHECKSUM_6ef3681a xilinx_anylanguagebehavioralsimulation_view_fileset ../common/up_axi.v verilogSource ../common/util_pulse_gen.v verilogSource axi_fan_control.v verilogSource xilinx_xpgui_view_fileset xgui/axi_fan_control_v1_0.tcl tclSource CHECKSUM_c9d9f988 XGUI_VERSION_2 axi_fan_control_v1_0 ID Id 0 PWM_FREQUENCY_HZ Pwm Frequency Hz 5000 INTERNAL_SYSMONE Internal Sysmone 0 AVG_POW Avg Pow 7 TACHO_TOL_PERCENT Tacho Tol Percent 25 TACHO_T25 Tacho T25 1470000 TACHO_T50 Tacho T50 820000 TACHO_T75 Tacho T75 480000 TACHO_T100 Tacho T100 340000 TEMP_00_H Temp 00 H 5 TEMP_25_L Temp 25 L 20 TEMP_25_H Temp 25 H 40 TEMP_50_L Temp 50 L 60 TEMP_50_H Temp 50 H 70 TEMP_75_L Temp 75 L 80 TEMP_75_H Temp 75 H 90 TEMP_00_L Temp 00 L 95 Component_Name axi_fan_control_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_fan_control_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:14:22Z 2019.1.3