analog.com user util_extract 1.0 clk CLK clk xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_extract xilinx_anylanguagesynthesis_view_fileset viewChecksum 92e38904 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_extract xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 92e38904 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum cdd73d0a clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_in_trigger in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation valid_out out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_out out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_CHANNELS Num Of Channels 2 DATA_WIDTH Data Width 32 xilinx_anylanguagesynthesis_view_fileset util_extract.v verilogSource CHECKSUM_92e38904 xilinx_anylanguagebehavioralsimulation_view_fileset util_extract.v verilogSource xilinx_xpgui_view_fileset xgui/util_extract_v1_0.tcl tclSource CHECKSUM_cdd73d0a XGUI_VERSION_2 util_extract_v1_0 NUM_OF_CHANNELS Num Of Channels 2 DATA_WIDTH Data Width 32 Component_Name util_extract_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_extract_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:18:52Z 2019.1.3