analog.com user util_adxcvr 1.0 up_clk CLK up_clk ASSOCIATED_RESET up_rstn cpll_ref_clk_0 CLK cpll_ref_clk_0 ASSOCIATED_RESET up_rx_rst_0:up_tx_rst_0 cpll_ref_clk_1 CLK cpll_ref_clk_1 ASSOCIATED_RESET up_rx_rst_1:up_tx_rst_1 cpll_ref_clk_2 CLK cpll_ref_clk_2 ASSOCIATED_RESET up_rx_rst_2:up_tx_rst_2 cpll_ref_clk_3 CLK cpll_ref_clk_3 ASSOCIATED_RESET up_rx_rst_3:up_tx_rst_3 cpll_ref_clk_4 CLK cpll_ref_clk_4 ASSOCIATED_RESET up_rx_rst_4:up_tx_rst_4 cpll_ref_clk_5 CLK cpll_ref_clk_5 ASSOCIATED_RESET up_rx_rst_5:up_tx_rst_5 cpll_ref_clk_6 CLK cpll_ref_clk_6 ASSOCIATED_RESET up_rx_rst_6:up_tx_rst_6 cpll_ref_clk_7 CLK cpll_ref_clk_7 ASSOCIATED_RESET up_rx_rst_7:up_tx_rst_7 cpll_ref_clk_8 CLK cpll_ref_clk_8 ASSOCIATED_RESET up_rx_rst_8:up_tx_rst_8 cpll_ref_clk_9 CLK cpll_ref_clk_9 ASSOCIATED_RESET up_rx_rst_9:up_tx_rst_9 cpll_ref_clk_10 CLK cpll_ref_clk_10 ASSOCIATED_RESET up_rx_rst_10:up_tx_rst_10 cpll_ref_clk_11 CLK cpll_ref_clk_11 ASSOCIATED_RESET up_rx_rst_11:up_tx_rst_11 cpll_ref_clk_12 CLK cpll_ref_clk_12 ASSOCIATED_RESET up_rx_rst_12:up_tx_rst_12 cpll_ref_clk_13 CLK cpll_ref_clk_13 ASSOCIATED_RESET up_rx_rst_13:up_tx_rst_13 cpll_ref_clk_14 CLK cpll_ref_clk_14 ASSOCIATED_RESET up_rx_rst_14:up_tx_rst_14 cpll_ref_clk_15 CLK cpll_ref_clk_15 ASSOCIATED_RESET up_rx_rst_15:up_tx_rst_15 qpll_ref_clk_0 CLK qpll_ref_clk_0 qpll_ref_clk_4 CLK qpll_ref_clk_4 qpll_ref_clk_8 CLK qpll_ref_clk_8 qpll_ref_clk_12 CLK qpll_ref_clk_12 rx_out_clk_0 CLK rx_out_clk_0 rx_out_clk_1 CLK rx_out_clk_1 rx_out_clk_2 CLK rx_out_clk_2 rx_out_clk_3 CLK rx_out_clk_3 rx_out_clk_4 CLK rx_out_clk_4 rx_out_clk_5 CLK rx_out_clk_5 rx_out_clk_6 CLK rx_out_clk_6 rx_out_clk_7 CLK rx_out_clk_7 rx_out_clk_8 CLK rx_out_clk_8 rx_out_clk_9 CLK rx_out_clk_9 rx_out_clk_10 CLK rx_out_clk_10 rx_out_clk_11 CLK rx_out_clk_11 rx_out_clk_12 CLK rx_out_clk_12 rx_out_clk_13 CLK rx_out_clk_13 rx_out_clk_14 CLK rx_out_clk_14 rx_out_clk_15 CLK rx_out_clk_15 tx_out_clk_0 CLK tx_out_clk_0 tx_out_clk_1 CLK tx_out_clk_1 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tx_charisk_8 txdata tx_data_8 false up_es_9 enb up_es_enb_9 addr up_es_addr_9 wr up_es_wr_9 wdata up_es_wdata_9 rdata up_es_rdata_9 reset up_es_reset_9 ready up_es_ready_9 false up_rx_9 pll_locked up_rx_pll_locked_9 rst up_rx_rst_9 user_ready up_rx_user_ready_9 rst_done up_rx_rst_done_9 lpm_dfe_n up_rx_lpm_dfe_n_9 rate up_rx_rate_9 sys_clk_sel up_rx_sys_clk_sel_9 out_clk_sel up_rx_out_clk_sel_9 enb up_rx_enb_9 addr up_rx_addr_9 wr up_rx_wr_9 wdata up_rx_wdata_9 rdata up_rx_rdata_9 ready up_rx_ready_9 false up_tx_9 pll_locked up_tx_pll_locked_9 rst up_tx_rst_9 user_ready up_tx_user_ready_9 rst_done up_tx_rst_done_9 lpm_dfe_n up_tx_lpm_dfe_n_9 rate up_tx_rate_9 sys_clk_sel up_tx_sys_clk_sel_9 out_clk_sel up_tx_out_clk_sel_9 tx_diffctrl up_tx_diffctrl_9 tx_postcursor up_tx_postcursor_9 tx_precursor up_tx_precursor_9 enb up_tx_enb_9 addr up_tx_addr_9 wr up_tx_wr_9 wdata up_tx_wdata_9 rdata up_tx_rdata_9 ready up_tx_ready_9 false rx_9 rxcharisk rx_charisk_9 rxnotintable rx_notintable_9 rxdisperr rx_disperr_9 rxdata rx_data_9 false tx_9 txcharisk tx_charisk_9 txdata tx_data_9 false up_es_10 enb up_es_enb_10 addr up_es_addr_10 wr up_es_wr_10 wdata up_es_wdata_10 rdata up_es_rdata_10 reset up_es_reset_10 ready up_es_ready_10 false up_rx_10 pll_locked up_rx_pll_locked_10 rst up_rx_rst_10 user_ready up_rx_user_ready_10 rst_done up_rx_rst_done_10 lpm_dfe_n up_rx_lpm_dfe_n_10 rate up_rx_rate_10 sys_clk_sel up_rx_sys_clk_sel_10 out_clk_sel up_rx_out_clk_sel_10 enb up_rx_enb_10 addr up_rx_addr_10 wr up_rx_wr_10 wdata up_rx_wdata_10 rdata up_rx_rdata_10 ready up_rx_ready_10 false up_tx_10 pll_locked up_tx_pll_locked_10 rst up_tx_rst_10 user_ready up_tx_user_ready_10 rst_done up_tx_rst_done_10 lpm_dfe_n up_tx_lpm_dfe_n_10 rate up_tx_rate_10 sys_clk_sel up_tx_sys_clk_sel_10 out_clk_sel up_tx_out_clk_sel_10 tx_diffctrl up_tx_diffctrl_10 tx_postcursor up_tx_postcursor_10 tx_precursor up_tx_precursor_10 enb up_tx_enb_10 addr up_tx_addr_10 wr up_tx_wr_10 wdata up_tx_wdata_10 rdata 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xilinx_anylanguagebehavioralsimulation 0 false up_cpll_rst_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false rx_15_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false rx_15_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false rx_out_clk_15 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false rx_clk_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false rx_charisk_15 out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false rx_disperr_15 out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false rx_notintable_15 out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false rx_data_15 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false 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xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_rx_sys_clk_sel_15 in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_rx_out_clk_sel_15 in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_rx_enb_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_rx_addr_15 in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_rx_wr_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_rx_wdata_15 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_rx_rdata_15 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_rx_ready_15 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_tx_pll_locked_15 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_tx_rst_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_tx_user_ready_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_rst_done_15 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_tx_lpm_dfe_n_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_rate_15 in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_sys_clk_sel_15 in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_out_clk_sel_15 in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_diffctrl_15 in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_postcursor_15 in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_precursor_15 in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_enb_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_addr_15 in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_wr_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_wdata_15 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 up_tx_rdata_15 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_tx_ready_15 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation XCVR_TYPE Xcvr Type 0 QPLL_REFCLK_DIV Qpll Refclk Div 1 QPLL_FBDIV_RATIO Qpll Fbdiv Ratio 1 POR_CFG Por Cfg 0x0006 PPF0_CFG Ppf0 Cfg 0x0600 QPLL_CFG Qpll Cfg "000011010000000000110000001" QPLL_FBDIV Qpll Fbdiv "0000110000" QPLL_CFG0 Qpll Cfg0 0x331C QPLL_CFG1 Qpll Cfg1 0xD038 QPLL_CFG1_G3 Qpll Cfg1 G3 0xD038 QPLL_CFG2 Qpll Cfg2 0x0FC0 QPLL_CFG2_G3 Qpll Cfg2 G3 0x0FC0 QPLL_CFG3 Qpll Cfg3 0x0120 QPLL_CFG4 Qpll Cfg4 0x0003 QPLL_CP_G3 Qpll Cp G3 "0000011111" QPLL_LPF Qpll Lpf "0100110111" QPLL_CP Qpll Cp "0001111111" CPLL_FBDIV Cpll Fbdiv 2 CPLL_FBDIV_4_5 Cpll Fbdiv 4 5 5 CPLL_CFG0 Cpll Cfg0 0x01FA CPLL_CFG1 Cpll Cfg1 0x0023 CPLL_CFG2 Cpll Cfg2 0x0002 CPLL_CFG3 Cpll Cfg3 0x0000 CH_HSPMUX Ch Hspmux 0x2424 PREIQ_FREQ_BST Preiq Freq Bst 0 RXPI_CFG0 Rxpi Cfg0 0x0002 RXPI_CFG1 Rxpi Cfg1 0x0015 RTX_BUF_CML_CTRL Rtx Buf Cml Ctrl "011" TX_NUM_OF_LANES Tx Num Of Lanes 8 TX_OUT_DIV Tx Out Div 1 TX_CLK25_DIV Tx Clk25 Div 20 TX_LANE_INVERT Tx Lane Invert 0 TX_PI_BIASSET Tx Pi Biasset 1 TXPI_CFG Txpi Cfg 0x0054 A_TXDIFFCTRL A Txdiffctrl "10110" RX_NUM_OF_LANES Rx Num Of Lanes 8 RX_OUT_DIV Rx Out Div 1 RX_CLK25_DIV Rx Clk25 Div 20 RX_DFE_LPM_CFG Rx Dfe Lpm Cfg 0x0104 RX_PMA_CFG Rx Pma Cfg 0x001E7080 RX_CDR_CFG Rx Cdr Cfg 0x0B000023FF10400020 RXCDR_CFG0 Rxcdr Cfg0 0x0002 RXCDR_CFG2 Rxcdr Cfg2 0x0269 RXCDR_CFG2_GEN2 Rxcdr Cfg2 Gen2 "1001100101" RXCDR_CFG2_GEN4 Rxcdr Cfg2 Gen4 0x00B4 RXCDR_CFG3 Rxcdr Cfg3 0x0012 RXCDR_CFG3_GEN2 Rxcdr Cfg3 Gen2 "011010" RXCDR_CFG3_GEN3 Rxcdr Cfg3 Gen3 0x0012 RXCDR_CFG3_GEN4 Rxcdr Cfg3 Gen4 0x0024 RX_WIDEMODE_CDR Rx Widemode Cdr "00" RX_XMODE_SEL Rx Xmode Sel "1" TXDRV_FREQBAND Txdrv Freqband 0 TXFE_CFG1 Txfe Cfg1 0x6C00 TXFE_CFG2 Txfe Cfg2 0x6C00 TXFE_CFG3 Txfe Cfg3 0x6C00 TXPI_CFG0 Txpi Cfg0 0x0300 TXPI_CFG1 Txpi Cfg1 0x1000 RX_LANE_INVERT Rx Lane Invert 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_07421b06 0 1 2 3 4 5 6 7 8 9 10 xilinx_anylanguagesynthesis_view_fileset util_adxcvr_constr.xdc xdc util_adxcvr_xch.v verilogSource util_adxcvr_xcm.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource bd/bd.tcl tclSource util_adxcvr.v verilogSource CHECKSUM_92ef6f78 xilinx_anylanguagebehavioralsimulation_view_fileset util_adxcvr_xch.v verilogSource util_adxcvr_xcm.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource bd/bd.tcl tclSource util_adxcvr.v verilogSource xilinx_xpgui_view_fileset xgui/util_adxcvr_v1_0.tcl tclSource CHECKSUM_1fe9667d XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource xilinx_utilityxitfiles_view_fileset gui/util_adxcvr_v1_0.gtcl GTCL util_adxcvr_v1_0 XCVR_TYPE Xcvr Type 0 QPLL_REFCLK_DIV Qpll Refclk Div 1 QPLL_FBDIV_RATIO Qpll Fbdiv Ratio 1 POR_CFG Por Cfg 0x0006 PPF0_CFG Ppf0 Cfg 0x0600 QPLL_CFG Qpll Cfg "000011010000000000110000001" QPLL_FBDIV Qpll Fbdiv "0000110000" QPLL_CFG0 Qpll Cfg0 0x331C QPLL_CFG1 Qpll Cfg1 0xD038 QPLL_CFG1_G3 Qpll Cfg1 G3 0xD038 QPLL_CFG2 Qpll Cfg2 0x0FC0 QPLL_CFG2_G3 Qpll Cfg2 G3 0x0FC0 QPLL_CFG3 Qpll Cfg3 0x0120 QPLL_CFG4 Qpll Cfg4 0x0003 QPLL_CP_G3 Qpll Cp G3 "0000011111" QPLL_LPF Qpll Lpf "0100110111" QPLL_CP Qpll Cp "0001111111" CPLL_FBDIV Cpll Fbdiv 2 CPLL_FBDIV_4_5 Cpll Fbdiv 4 5 5 CPLL_CFG0 Cpll Cfg0 0x01FA CPLL_CFG1 Cpll Cfg1 0x0023 CPLL_CFG2 Cpll Cfg2 0x0002 CPLL_CFG3 Cpll Cfg3 0x0000 CH_HSPMUX Ch Hspmux 0x2424 PREIQ_FREQ_BST Preiq Freq Bst 0 RXPI_CFG0 Rxpi Cfg0 0x0002 RXPI_CFG1 Rxpi Cfg1 0x0015 RTX_BUF_CML_CTRL Rtx Buf Cml Ctrl "011" TX_NUM_OF_LANES Tx Num Of Lanes 8 TX_OUT_DIV Tx Out Div 1 TX_CLK25_DIV Tx Clk25 Div 20 TX_LANE_INVERT Tx Lane Invert 0 TX_PI_BIASSET Tx Pi Biasset 1 TXPI_CFG Txpi Cfg 0x0054 A_TXDIFFCTRL A Txdiffctrl "10110" RX_NUM_OF_LANES Rx Num Of Lanes 8 RX_OUT_DIV Rx Out Div 1 RX_CLK25_DIV Rx Clk25 Div 20 RX_DFE_LPM_CFG Rx Dfe Lpm Cfg 0x0104 RX_PMA_CFG Rx Pma Cfg 0x001E7080 RX_CDR_CFG Rx Cdr Cfg 0x0B000023FF10400020 RXCDR_CFG0 Rxcdr Cfg0 0x0002 RXCDR_CFG2 Rxcdr Cfg2 0x0269 RXCDR_CFG2_GEN2 Rxcdr Cfg2 Gen2 "1001100101" RXCDR_CFG2_GEN4 Rxcdr Cfg2 Gen4 0x00B4 RXCDR_CFG3 Rxcdr Cfg3 0x0012 RXCDR_CFG3_GEN2 Rxcdr Cfg3 Gen2 "011010" RXCDR_CFG3_GEN3 Rxcdr Cfg3 Gen3 0x0012 RXCDR_CFG3_GEN4 Rxcdr Cfg3 Gen4 0x0024 RX_WIDEMODE_CDR Rx Widemode Cdr "00" RX_XMODE_SEL Rx Xmode Sel "1" TXDRV_FREQBAND Txdrv Freqband 0 TXFE_CFG1 Txfe Cfg1 0x6C00 TXFE_CFG2 Txfe Cfg2 0x6C00 TXFE_CFG3 Txfe Cfg3 0x6C00 TXPI_CFG0 Txpi Cfg0 0x0300 TXPI_CFG1 Txpi Cfg1 0x1000 RX_LANE_INVERT Rx Lane Invert 0 Component_Name util_adxcvr_v1_0 virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices util_adxcvr_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T12:25:46Z 2019.1.3