`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/01/13 12:04:17
// Design Name:
// Module Name: rf_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module rf_control(
    input   			clk 				 			   ,	//192Mclk
    input   			rst 				 			   ,

    input 	    [5:0]   tx_gain_manual 		 			   ,  	//发射增益输入
    input 	    [5:0]   rx_gain_manual		 			   ,	//接收增益输入

    input   			gain_on_vio				  		   ,	//vio设置参数or自动切换
    input   	[1:0]	rf_txrx_vio    			   	   	   , 	//发射通道或者接收通道
    input   	[1:0]	rf_txrx_net    			   	   	   , 	//受网络层控制

    input   			rf_vio_set   					   ,  	//vio设置参数or自动切换

    input  		[10:0]	tx_freq_hop_words  	 		   	   , 	//tx跳频频率控制字
    input  				tx_hop_words_valid				   ,	//tx跳频频率控制字有效脉冲
    input   			tx_freq_hop_switch  			   ,	//tx频点切换脉冲

    input  		[10:0]	rx_freq_hop_words  	 		   	   , 	//rx跳频频率控制字
    input  				rx_hop_words_valid				   ,	//rx跳频频率控制字有效脉冲
    input   			rx_freq_hop_switch  			   ,	//rx频点切换脉冲

    input  		[10:0]	freq_hop_words_vio  	 		   , 	//vio设置跳频频率控制字
    input  				hop_words_valid_vio				   ,	//vio设置跳频频率控制字有效脉冲
    input   			freq_hop_switch_vio  			   ,	//vio设置频点切换脉冲



    output reg [11:0] 	tx_gain					= 12'd0	   ,  	//发射通道增益
    output reg  	  	tx_gain_on				= 1'd0	   ,	//发射通道开关
    output reg  [9:0]  	rx_gain					= 10'd0	   ,	//接收通道增益
    output reg  	  	rx_gain_on 				= 1'd0 	   ,	//发射通道开关

    output reg [10:0]	freq_hop_words  	    = 11'd0    , 	//跳频频率控制字
    output reg 			hop_words_valid		    = 1'd0	   ,	//跳频频率控制字有效脉冲
    output reg  		freq_hop_switch  	    = 1'd0	   ,	//频点切换脉冲
    output reg  		freq_hop_switch_out  	= 1'd0

    );

	reg rst_D1_1 = 1'd0;
	reg rst_D1_2 = 1'd0;
	reg rst_D1_3 = 1'd0;
	always @(posedge clk) begin
		rst_D1_1 <= rst ;
		rst_D1_2 <= rst ;
		rst_D1_3 <= rst ;

	end

//--------------------------------------------------------------------------------------------------

//发射通道增益、开关设置
	always @(posedge clk) begin
		if(rst_D1_1)
			tx_gain_on <= 1'b0  ;
		else if(gain_on_vio)
			tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0  ;
		else
			tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0  ;


		if(rst_D1_1)
			tx_gain[11:0] <= 12'b111111111111  ;
		else
			tx_gain[11:0] <= {5'b0,tx_gain_manual[5:0],1'b0};
	end

//--------------------------------------------------------------------------------------------------
//接收通道增益、开关设置
	reg [5:0] rx_gain_div2 = 5'd0;
	always @(posedge clk) begin
		if(rst_D1_2)
			rx_gain_on <= 1'b0  ;
		else if(gain_on_vio)
			rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0  ;
		else
			rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0  ;


		if(rst_D1_2)
			rx_gain[9:0] <= 10'b1111111111  ;
		else
			rx_gain[9:0] <= {4'b0,rx_gain_manual[5:0]} ;
	end
//--------------------------------------------------------------------------------------------------
//跳频设置vio控制or网络层设置
	reg	[10:0]	freq_hop_words_net 	= 11'd0	;
	reg			hop_words_valid_net	= 1'd0	;
	reg			freq_hop_switch_net	= 1'd0	;

	always @(posedge clk) begin
		if(rst_D1_3)begin
				freq_hop_words_net [10:0] <= 11'd0	;
				hop_words_valid_net 	  <= 1'd0 	;
				freq_hop_switch_net 	  <= 1'd0 	;
		end
		else if(rf_txrx_net[1:0] == 2'd1)begin
				freq_hop_words_net [10:0] <= tx_freq_hop_words[10:0]	;
				hop_words_valid_net 	  <= tx_hop_words_valid	 		;
				freq_hop_switch_net 	  <= tx_freq_hop_switch	 		;
		end
		else if(rf_txrx_net[1:0] == 2'd2)begin
				freq_hop_words_net [10:0] <= rx_freq_hop_words[10:0]	;
				hop_words_valid_net 	  <= rx_hop_words_valid	 		;
				freq_hop_switch_net 	  <= rx_freq_hop_switch	 		;
		end
		else begin
				freq_hop_words_net [10:0] <= freq_hop_words_net [10:0]	;
				hop_words_valid_net 	  <= 1'd0 	;
				freq_hop_switch_net 	  <= 1'd0 	;
		end

	end

	always @(posedge clk) begin
		if(rst_D1_3)begin
				freq_hop_words [10:0] <= 11'd0	;
				hop_words_valid 	  <= 1'd0 	;
				freq_hop_switch 	  <= 1'd0 	;
				freq_hop_switch_out   <= 1'd0 	;
		end
		else if(rf_vio_set)begin
				freq_hop_words [10:0] <= freq_hop_words_vio[10:0]	;
				hop_words_valid 	  <= hop_words_valid_vio	 	;
				freq_hop_switch 	  <= freq_hop_switch_vio	 	;
				freq_hop_switch_out   <= freq_hop_switch_vio	 	;
		end
		else begin
				freq_hop_words [10:0] <= freq_hop_words_net[10:0]	;
				hop_words_valid 	  <= hop_words_valid_net	 	;
				freq_hop_switch 	  <= freq_hop_switch_net	 	;
				freq_hop_switch_out   <= freq_hop_switch_net	 	;
		end
	end

	// ila_RF ila_RF (
		// .clk	(clk					), 	// input wire clk

		// .probe0 (tx_gain[11:0]			), 	// input wire [11:0]  probe0
		// .probe1 (tx_gain_on				), 	// input wire [0:0]  probe1
		// .probe2 (rx_gain[9:0]			), 	// input wire [9:0]  probe2
		// .probe3 (rx_gain_on				), 	// input wire [0:0]  probe3

		// .probe4 (freq_hop_words[10:0]	), 	// input wire [10:0]  probe4
		// .probe5 (hop_words_valid		), 	// input wire [0:0]  probe5
		// .probe6 (freq_hop_switch		) 	// input wire [0:0]  probe6
	// );

endmodule