`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 08/06/2022 04:20:01 PM // Design Name: // Module Name: system_top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module system_top( /*************************************************************************** * Interface Content * 01 - Clocks & Reset * 02 - DDR and Fixed-io ***************************************************************************/ // ************************************************************************* // ***************************** PS Fixed IOs ****************************** // ************************************************************************ inout [14:0] DDR_addr , inout [2:0] DDR_ba , inout DDR_cas_n , inout DDR_ck_n , inout DDR_ck_p , inout DDR_cke , inout DDR_cs_n , inout [3:0] DDR_dm , inout [31:0] DDR_dq , inout [3:0] DDR_dqs_n , inout [3:0] DDR_dqs_p , inout DDR_odt , inout DDR_ras_n , inout DDR_reset_n , inout DDR_we_n , inout FIXED_IO_ddr_vrn , inout FIXED_IO_ddr_vrp , inout [53:0] FIXED_IO_mio , inout FIXED_IO_ps_clk , inout FIXED_IO_ps_porb , inout FIXED_IO_ps_srstb , // ************************************************************************* // *************************** Clocks and Resets *************************** // ************************************************************************* input CLK_25M , // pl clock, 25mhz // glink gt reference clock input glink_refclk_p , // generated by oscillator, 125mhz input glink_refclk_n , // ************************************************************************* // ************************************ LVDS ******************************* // ************************************************************************* input Din1 , output Dout1 , input Din2 , output Dout2 , input DCLK_in , output DCLK_out , input TR , input DARY , // ************************************************************************* // *********************************beam ctrl******************************* // ************************************************************************* output [3:0] CLK_TR , output [3:0] TR_TR , output [3:0] DATA_TR , output [3:0] SYN_TR , output [3:0] SEL_TR , output [3:0] SEL4_TR , output [3:0] SEL3_TR , output [3:0] SEL2_TR , output [3:0] SEL1_TR , output T_DLY , output R_DLY , output PW_DOWN , // ************************************************************************* // ************************************ GLINK ******************************* // ************************************************************************* input rx_datain_p_ch_a , input rx_datain_n_ch_a , input rx_datain_p_ch_b , input rx_datain_n_ch_b , output tx_dataout_p_ch_a , output tx_dataout_n_ch_a , output tx_dataout_p_ch_b , output tx_dataout_n_ch_b ); /******************************************************************************* *******************************************************************************/ //supply1 const_high; //assign PW_DOWN = const_high; //****************************************************************************** //******************************* Clock & Reset ********************************* //****************************************************************************** wire CLK_25M_1; wire CLK_25M_2; wire CLK_25M_3; clk_wiz_25m_1to3 u_clk_wiz_25m_1to3 ( // Clock out ports .clk_out1(CLK_25M_1), // output clk_out1 .clk_out2(CLK_25M_2), // output clk_out2 .clk_out3(CLK_25M_3), // output clk_out3 // Clock in ports .clk_in1(CLK_25M)); // input clk_in1 //////clk_lvds wire pl_clk_96m; wire lvds_rst; wire lvds_locked; clk_wiz_lvds u_clk_wiz_lvds ( // Clock out ports .clk_out1(pl_clk_96m), // output clk_out1 // Status and control signals .locked(lvds_locked), // output locked // Clock in ports .clk_in1(CLK_25M_1)); // input clk_in1 assign lvds_rst = ~lvds_locked; //////clk_glink wire glink_logic_clk ; wire glink_ila_clk ; wire glink_rst; wire glink_locked; clk_wiz_glink u_clk_wiz_glink ( // Clock out ports .clk_out1(glink_logic_clk), // output clk_out1 25m .clk_out2(glink_ila_clk), // output clk_out2 125m // Status and control signals .locked(glink_locked), // output locked // Clock in ports .clk_in1(CLK_25M_2)); // input clk_in1 assign glink_rst = ~glink_locked; //////clk_beam wire clk_beam_100m; wire clk_beam_12_5m; wire clk_beam_50m; wire beam_locked; clk_wiz_beam u_clk_wiz_beam ( // Clock out ports .clk_out1(clk_beam_100m), // output clk_out1 .clk_out2(clk_beam_12_5m), // output clk_out2 .clk_out3(clk_beam_50m), // output clk_out3 // Status and control signals .locked(beam_locked), // output locked // Clock in ports .clk_in1(CLK_25M_3)); // input clk_in1 //****************************************************************************** //********************************* selectio ************************************ //****************************************************************************** wire lvds_clkin; wire lvds_rx_clk; clk_wiz_96m_1to1 u_clk_wiz_96m_1to1 ( // Clock out ports .clk_out1(lvds_rx_clk), // output clk_out1 // Clock in ports .clk_in1(lvds_clkin)); // input clk_in1 assign lvds_clkin = DCLK_in; wire [3:0] lvds_din; wire [3:0] lvds_rx_data; selectio_lvds_rx u_selectio_lvds_rx ( .data_in_from_pins(lvds_din), // input [3:0] data_in_from_pins .data_in_to_device(lvds_rx_data), // output [3:0] data_in_to_device .clk_in(lvds_rx_clk), // input clk_in .io_reset(lvds_rst) // input io_reset ); assign lvds_din[0] = Din1; assign lvds_din[1] = Din2; assign lvds_din[2] = TR; assign lvds_din[3] = DARY; wire lvds_dout; wire lvds_tx_data; wire lvds_clkout; wire lvds_tx_clk; selectio_lvds_tx u_selectio_lvds_tx ( .data_out_from_device(lvds_tx_data), // input [0:0] data_out_from_device .data_out_to_pins(lvds_dout), // output [0:0] data_out_to_pins .clk_in(lvds_tx_clk), // input clk_in .clk_out(lvds_clkout), // output clk_out .io_reset(lvds_rst) // input io_reset ); assign Dout1 = lvds_dout; assign DCLK_out = lvds_clkout; //****************************************************************************** //**************************** System Block Design ****************************** //****************************************************************************** wire c2c_rst_n ; wire c2c_rx_clk ; wire c2c_tx_clk ; wire [31:0] c2c_tx_fifo_tdata ; wire c2c_tx_fifo_tlast ; wire c2c_tx_fifo_tready ; wire c2c_tx_fifo_tvalid ; wire [31:0] c2c_rx_fifo_tdata ; wire c2c_rx_fifo_tlast ; wire c2c_rx_fifo_tready ; wire c2c_rx_fifo_tvalid ; wire ps_clk ; wire glink_ip_clk ; wire [31:0] glink_gpio_i_0 ; wire [31:0] glink_gpio_i_1 ; wire [31:0] glink_gpio_o_0 ; wire [31:0] glink_gpio_o_1 ; wire [15:0] glink_tx_fifo_tdata ; wire glink_tx_fifo_tlast ; wire glink_tx_fifo_tready ; wire glink_tx_fifo_tvalid ; wire [15:0] glink_rx_fifo_tdata ; wire glink_rx_fifo_tlast ; wire glink_rx_fifo_tready ; wire glink_rx_fifo_tvalid ; wire pwdown_gpio_o ; system_bd_wrapper u_system_bd_wrapper (.DDR_addr (DDR_addr[14:0] ), .DDR_ba (DDR_ba[2:0] ), .DDR_cas_n (DDR_cas_n ), .DDR_ck_n (DDR_ck_n ), .DDR_ck_p (DDR_ck_p ), .DDR_cke (DDR_cke ), .DDR_cs_n (DDR_cs_n ), .DDR_dm (DDR_dm[3:0] ), .DDR_dq (DDR_dq[31:0] ), .DDR_dqs_n (DDR_dqs_n[3:0] ), .DDR_dqs_p (DDR_dqs_p[3:0] ), .DDR_odt (DDR_odt ), .DDR_ras_n (DDR_ras_n ), .DDR_reset_n (DDR_reset_n ), .DDR_we_n (DDR_we_n ), .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ), .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ), .FIXED_IO_mio (FIXED_IO_mio[53:0] ), .FIXED_IO_ps_clk (FIXED_IO_ps_clk ), .FIXED_IO_ps_porb (FIXED_IO_ps_porb ), .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb ), //C2C .c2c_rst_n (c2c_rst_n ), .c2c_rx_clk (c2c_rx_clk ), .c2c_tx_clk (c2c_tx_clk ), .m_axis_fifo_c2c_out_tdata (c2c_tx_fifo_tdata[31:0] ), .m_axis_fifo_c2c_out_tlast (c2c_tx_fifo_tlast ), .m_axis_fifo_c2c_out_tready (c2c_tx_fifo_tready ), .m_axis_fifo_c2c_out_tvalid (c2c_tx_fifo_tvalid ), .s_axis_fifo_c2c_in_tdata (c2c_rx_fifo_tdata[31:0] ), .s_axis_fifo_c2c_in_tlast (c2c_rx_fifo_tlast ), .s_axis_fifo_c2c_in_tready (c2c_rx_fifo_tready ), .s_axis_fifo_c2c_in_tvalid (c2c_rx_fifo_tvalid ), //PS CLK .ps_clk (ps_clk ), // Glink Ports .glink_ip_clk (glink_ip_clk ), .glink_ip_rst_n (~glink_rst ), .glink_gpio_i_0 (glink_gpio_i_0[31:0] ),// PS <- Glink .glink_gpio_i_1 (glink_gpio_i_1[31:0] ),// PS <- Glink .glink_gpio_o_0 (glink_gpio_o_0[31:0] ),// PS -> Glink .glink_gpio_o_1 (glink_gpio_o_1[31:0] ),// PS -> Glink .m_axis_fifo_glink_out_tdata (glink_tx_fifo_tdata[15:0] ),// PS -> Glink .m_axis_fifo_glink_out_tlast (glink_tx_fifo_tlast ),// PS -> Glink .m_axis_fifo_glink_out_tready (glink_tx_fifo_tready ),// PS -> Glink .m_axis_fifo_glink_out_tvalid (glink_tx_fifo_tvalid ),// PS -> Glink .s_axis_fifo_glink_in_tdata (glink_rx_fifo_tdata[15:0] ),// PS <- Glink .s_axis_fifo_glink_in_tlast (glink_rx_fifo_tlast ),// PS <- Glink .s_axis_fifo_glink_in_tready (glink_rx_fifo_tready ),// PS <- Glink .s_axis_fifo_glink_in_tvalid (glink_rx_fifo_tvalid ),// PS <- Glink .pwdown_gpio_o (pwdown_gpio_o ) ); assign c2c_rst_n = ~lvds_rst; assign c2c_rx_clk = lvds_rx_clk; assign c2c_tx_clk = lvds_tx_clk; reg pwdown_gpio_o_100M_d1; reg pwdown_gpio_o_100M_d2; reg pwdown_gpio_o_100M_d3; always @ ( posedge clk_beam_100m ) begin if ( ~beam_locked ) begin pwdown_gpio_o_100M_d1 <= 1'd0; pwdown_gpio_o_100M_d2 <= 1'd0; pwdown_gpio_o_100M_d3 <= 1'd0; end else begin pwdown_gpio_o_100M_d1 <= pwdown_gpio_o; pwdown_gpio_o_100M_d2 <= pwdown_gpio_o_100M_d1; pwdown_gpio_o_100M_d3 <= pwdown_gpio_o_100M_d2; end end assign PW_DOWN = pwdown_gpio_o_100M_d3; //****************************************************************************** //*********************************** Glink ************************************* //****************************************************************************** glink_top u_glink_top( // glink gt reference clock .glink_refclk_p (glink_refclk_p ), //in,125mhz .glink_refclk_n (glink_refclk_n ), // glink pk clock .glink_logic_clk (glink_logic_clk ), //in,25mhz .pl_rst (glink_rst ), .rx_datain_p_ch_a (rx_datain_p_ch_a ), .rx_datain_n_ch_a (rx_datain_n_ch_a ), .rx_datain_p_ch_b (rx_datain_p_ch_b ), .rx_datain_n_ch_b (rx_datain_n_ch_b ), .tx_dataout_p_ch_a (tx_dataout_p_ch_a ), .tx_dataout_n_ch_a (tx_dataout_n_ch_a ), .tx_dataout_p_ch_b (tx_dataout_p_ch_b ), .tx_dataout_n_ch_b (tx_dataout_n_ch_b ), //glink_ctrl .glink_gpio_i_0 (glink_gpio_i_0 ), .glink_gpio_i_1 (glink_gpio_i_1 ), .glink_gpio_o_0 (glink_gpio_o_0 ), .glink_gpio_o_1 (glink_gpio_o_1 ), //DMA_send_fifo .glink_tx_fifo_tdata (glink_tx_fifo_tdata ), .glink_tx_fifo_tlast (glink_tx_fifo_tlast ), .glink_tx_fifo_tready (glink_tx_fifo_tready ), .glink_tx_fifo_tvalid (glink_tx_fifo_tvalid ), //DMA_recv_fifo .glink_rx_fifo_tdata (glink_rx_fifo_tdata ), .glink_rx_fifo_tlast (glink_rx_fifo_tlast ), .glink_rx_fifo_tready (glink_rx_fifo_tready ), .glink_rx_fifo_tvalid (glink_rx_fifo_tvalid ), .glink_ip_clk (glink_ip_clk )//out,31.25mhz ); //****************************************************************************** //***************************** C2C DMA Control ******************************* //****************************************************************************** c2c_bridge_dma u_c2c_bridge_dma( .clk (pl_clk_96m ), // input clk, 96Mhz .rst (lvds_rst ), // input rst, active high //interface data .c2c_clkin (lvds_rx_clk ), .c2c_clkout (lvds_tx_clk ), .c2c_din (lvds_rx_data[0] ), .c2c_dout (lvds_tx_data ), //dma fifo interface .c2c_tx_fifo_tdata (c2c_tx_fifo_tdata ), .c2c_tx_fifo_tlast (c2c_tx_fifo_tlast ), .c2c_tx_fifo_tready (c2c_tx_fifo_tready ), .c2c_tx_fifo_tvalid (c2c_tx_fifo_tvalid ), .c2c_rx_fifo_tdata (c2c_rx_fifo_tdata ), .c2c_rx_fifo_tlast (c2c_rx_fifo_tlast ), .c2c_rx_fifo_tready (c2c_rx_fifo_tready ), .c2c_rx_fifo_tvalid (c2c_rx_fifo_tvalid ) ); //****************************************************************************** //************************************* beam ctrl********************************* //****************************************************************************** wire beam_clk; wire en_out; wire data_out; wire tr_out; wire dary_out; wire [15:0] debug_freq ; wire debug_freq_change ; wire [63:0] debug_tr_count ; antenna_interface u_antenna_interface ( .clk_in (lvds_rx_clk ), .data_in (lvds_rx_data[1]), .tr_in (lvds_rx_data[2]), .dary_in (lvds_rx_data[3]), .rst (lvds_rst ), .ant_clk (beam_clk ), .en_out (en_out ), .clk_out (clk_beam_100m ), .data_out (data_out ), .tr_out (tr_out ), .dary_out (dary_out ), .debug_freq (debug_freq ), .debug_freq_change (debug_freq_change), .debug_tr_count (debug_tr_count ) ); ttop_S_005X u_ttop_S_005X( .clock100 (clk_beam_100m ), .clkdv (clk_beam_12_5m ), .clk50 (clk_beam_50m ), .n_rst (pwdown_gpio_o_100M_d3), //interface Vio .CLK (beam_clk ), .DATA (data_out ), .EN (en_out ), .DARY (dary_out ), .TR (tr_out ), //TR Com_Tr_TR_N , .CLK_TR ({CLK_TR[0] ,CLK_TR[1] ,CLK_TR[2] ,CLK_TR[3] } ), .DATA_TR ({DATA_TR[0],DATA_TR[1],DATA_TR[2],DATA_TR[3] } ), .SYN_TR ({SYN_TR[0] ,SYN_TR[1] ,SYN_TR[2] ,SYN_TR[3] } ), .SEL_TR ({SEL_TR[0] ,SEL_TR[1] ,SEL_TR[2] ,SEL_TR[3] } ), .SEL4_TR ({SEL1_TR[3],SEL2_TR[3],SEL3_TR[3],SEL4_TR[3] } ), .SEL3_TR ({SEL1_TR[2],SEL2_TR[2],SEL3_TR[2],SEL4_TR[2] } ), .SEL2_TR ({SEL1_TR[1],SEL2_TR[1],SEL3_TR[1],SEL4_TR[1] } ), .SEL1_TR ({SEL1_TR[0],SEL2_TR[0],SEL3_TR[0],SEL4_TR[0] } ),//sel4是高使 .TR_TR ({TR_TR[0],TR_TR[1],TR_TR[2],TR_TR[3] } ), //DLY .T_DLY(T_DLY), .R_DLY(R_DLY), //test .LED0 ( ), .LED1 ( ), .test1( ), .test2( ), .test3( ), .test4( ), .test5( ), .test6( ), .test7( ), .test8( ) ); //****************************************************************************** //******************************* ILAs and VIOs ******************************* //****************************************************************************** ila_c2c_dma_tx u_ila_c2c_dma_tx ( .clk (u_c2c_bridge_dma.clk ), // input wire clk .probe0 (u_c2c_bridge_dma.c2c_tx_fifo_tdata ), // input wire [31:0] probe0 .probe1 (u_c2c_bridge_dma.c2c_tx_fifo_tlast ), // input wire [0:0] probe1 .probe2 (u_c2c_bridge_dma.c2c_tx_fifo_tready), // input wire [0:0] probe2 .probe3 (u_c2c_bridge_dma.c2c_tx_fifo_tvalid), // input wire [0:0] probe3 .probe4 (u_c2c_bridge_dma.rst ), // input wire [0:0] probe4 .probe5 (u_c2c_bridge_dma.c2c_dout ), // input wire [0:0] probe5 .probe6 (u_c2c_bridge_dma.tx_data_32 ) // input wire [31:0] probe6 ); ila_c2c_dma_rx u_ila_c2c_dma_rx ( .clk (u_c2c_bridge_dma.c2c_clkin ), // input wire clk .probe0 (u_c2c_bridge_dma.c2c_rx_fifo_tdata ), // input wire [31:0] probe0 .probe1 (u_c2c_bridge_dma.c2c_rx_fifo_tlast ), // input wire [0:0] probe1 .probe2 (u_c2c_bridge_dma.c2c_rx_fifo_tready), // input wire [0:0] probe2 .probe3 (u_c2c_bridge_dma.c2c_rx_fifo_tvalid), // input wire [0:0] probe3 .probe4 (u_c2c_bridge_dma.rx_state ), // input wire [3:0] probe4 .probe5 (u_c2c_bridge_dma.rx_state_next ), // input wire [3:0] probe5 .probe6 (u_c2c_bridge_dma.rx_data_cnt ), // input wire [36:0] probe6 .probe7 (u_c2c_bridge_dma.rx_frame_length ), // input wire [31:0] probe7 .probe8 (u_c2c_bridge_dma.rx_data_32 ), // input wire [31:0] probe8 .probe9 (u_c2c_bridge_dma.c2c_din ) // input wire [0:0] probe9 ); ila_glink u_ila_glink ( .clk (glink_ila_clk ), // input wire clk .probe0 (u_glink_top.glink_rst ), // input wire [0:0] probe0 .probe1 (u_glink_top.smartnc_trans_trig ), // input wire [0:0] probe1 .probe2 (u_glink_top.smartnc_trans_reset ), // input wire [0:0] probe2 .probe3 (u_glink_top.smartnc_trans_idle ), // input wire [0:0] probe3 .probe4 (u_glink_top.smartnc_trans_err ), // input wire [0:0] probe4 .probe5 (u_glink_top.smartnc_intf_tx_fifo_wdata ), // input wire [15:0] probe5 .probe6 (u_glink_top.smartnc_intf_tx_fifo_wr_en ), // input wire [0:0] probe6 .probe7 (u_glink_top.smartnc_intf_tx_fifo_afull ), // input wire [0:0] probe7 .probe8 (u_glink_top.smartnc_intf_rx_fifo_empty ), // input wire [0:0] probe8 .probe9 (u_glink_top.smartnc_intf_rx_fifo_rdata ), // input wire [15:0] probe9 .probe10(u_glink_top.smartnc_intf_rx_fifo_rd_en ), // input wire [0:0] probe10 .probe11(u_glink_top.smartnt_intf_cmd_proc_req ), // input wire [0:0] probe11 .probe12(u_glink_top.smartnt_intf_cmd_proc_ack ), // input wire [0:0] probe12 .probe13(u_glink_top.smartnt_intf_rx_fifo_empty ), // input wire [0:0] probe13 .probe14(u_glink_top.smartnt_intf_rx_fifo_rdata ), // input wire [15:0] probe14 .probe15(u_glink_top.smartnt_intf_rx_fifo_rd_en ), // input wire [0:0] probe15 .probe16(u_glink_top.smartnt_intf_tx_fifo_wdata ), // input wire [15:0] probe16 .probe17(u_glink_top.smartnt_intf_tx_fifo_wr_en ), // input wire [0:0] probe17 .probe18(u_glink_top.glink_ip_clk ), // input wire [0:0] probe18 .probe19(u_glink_top.glink_ip_rst_n ) // input wire [0:0] probe19 ); ila_glink_2 u_ila_glink_2 ( .clk (ps_clk ), // input wire clk .probe0(u_glink_top.i_node_id ), // input wire [11:0] probe0 .probe1(u_glink_top.i_node_id_par ), // input wire [0:0] probe1 .probe2(u_glink_top.i_smartnc_2nd_cfg), // input wire [15:0] probe2 .probe3(u_glink_top.i_smartnc_3rd_cfg), // input wire [15:0] probe3 .probe4(u_glink_top.i_smartnt_cfg ) // input wire [15:0] probe4 ); ila_dma_fifo u_ila_dma_fifo ( .clk (glink_ip_clk ), // input wire clk .probe0(glink_tx_fifo_tdata ), // input wire [15:0] probe0 .probe1(glink_tx_fifo_tlast ), // input wire [0:0] probe1 .probe2(glink_tx_fifo_tready), // input wire [0:0] probe2 .probe3(glink_tx_fifo_tvalid), // input wire [0:0] probe3 .probe4(glink_rx_fifo_tdata ), // input wire [15:0] probe4 .probe5(glink_rx_fifo_tlast ), // input wire [0:0] probe5 .probe6(glink_rx_fifo_tready), // input wire [0:0] probe6 .probe7(glink_rx_fifo_tvalid) // input wire [0:0] probe7 ); ila_beam u_ila_beam ( .clk (clk_beam_100m ), // input wire clk .probe0 (clk_beam_12_5m ), // input wire [0:0] probe0 .probe1 (clk_beam_50m ), // input wire [0:0] probe1 .probe2 (beam_locked ), // input wire [0:0] probe2 .probe3 (beam_clk ), // input wire [0:0] probe3 .probe4 (data_out ), // input wire [0:0] probe4 .probe5 (en_out ), // input wire [0:0] probe5 .probe6 (dary_out ), // input wire [0:0] probe6 .probe7 (tr_out ), // input wire [0:0] probe7 .probe8 (CLK_TR ), // input wire [3:0] probe8 .probe9 (DATA_TR ), // input wire [3:0] probe9 .probe10(SYN_TR ), // input wire [3:0] probe10 .probe11(SEL_TR ), // input wire [3:0] probe11 .probe12(SEL1_TR ), // input wire [3:0] probe12 .probe13(SEL2_TR ), // input wire [3:0] probe13 .probe14(SEL3_TR ), // input wire [3:0] probe14 .probe15(SEL4_TR ), // input wire [3:0] probe15 .probe16(TR_TR ), // input wire [3:0] probe16 .probe17(T_DLY ), // input wire [0:0] probe17 .probe18(R_DLY ), // input wire [0:0] probe18 .probe19(debug_freq ), // input wire [15:0] probe19 .probe20(debug_freq_change), // input wire [0:0] probe20 .probe21(debug_tr_count ) // input wire [63:0] probe21 ); ila_en_creat_in u_ila_en_creat_in ( .clk (u_antenna_interface.clk_in ), // input wire clk .probe0(u_antenna_interface.data_in ), // input wire [0:0] probe0 .probe1(u_antenna_interface.tr_in ), // input wire [0:0] probe1 .probe2(u_antenna_interface.dary_in ), // input wire [0:0] probe2 .probe3(u_antenna_interface.data_in_9 ), // input wire [8:0] probe0 .probe4(u_antenna_interface.rx_bitcnt ), // input wire [15:0] probe1 .probe5(u_antenna_interface.rx_state ), // input wire [3:0] probe4 .probe6(u_antenna_interface.recv_down ), // input wire [0:0] probe6 .probe7(u_antenna_interface.fifo_data_in), // input wire [0:0] probe8 .probe8(u_antenna_interface.fifo_wr_en ) // input wire [0:0] probe9 ); ila_en_creat_out u_ila_en_creat_out ( .clk (u_antenna_interface.clk_out ), // input wire clk .probe0 (u_antenna_interface.en_out ), // input wire [0:0] probe0 .probe1 (u_antenna_interface.data_out ), // input wire [0:0] probe1 .probe2 (u_antenna_interface.tr_out ), // input wire [0:0] probe2 .probe3 (u_antenna_interface.dary_out ), // input wire [0:0] probe3 .probe4 (u_antenna_interface.tx_bitcnt ), // input wire [15:0] probe2 .probe5 (u_antenna_interface.rest_cnt ), // input wire [15:0] probe3 .probe6 (u_antenna_interface.tx_state ), // input wire [3:0] probe5 .probe7 (u_antenna_interface.recv_down_d3 ), // input wire [0:0] probe7 .probe8 (u_antenna_interface.data_out_reg ), // input wire [0:0] probe10 .probe9 (u_antenna_interface.fifo_rd_en ), // input wire [0:0] probe11 .probe10(u_antenna_interface.en_out_reg ), // input wire [0:0] probe12 .probe11(u_antenna_interface.beam_clk_reg ), // input wire [0:0] probe13 .probe12(u_antenna_interface.beam_clk_reg_d2) // input wire [0:0] probe14 ); endmodule